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6 i9 n2 S/ K/ q9 B6 Q3 }$ ?DATE: 07-25-2014 HOTFIX VERSION: 0328 @( ~$ e1 x; c8 [6 V
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9 S( ^) h4 h5 R3 v0 x9 eCCRID PRODUCT PRODUCTLEVEL2 TITLE* A0 a, [( e2 J% F
===================================================================================================================================* ?$ U8 U) n- {/ s
381127 SPECCTRA CROSSTALK Specctra xtalk reports aren't correct6 o T( G/ y2 g# m+ r
616770 allegro_EDITOR COLOR Remove the APPLY button in the Color Dialog window.
( U) d% d! Q2 S6 {* `$ k982944 ALLEGRO_EDITOR COLOR seperate the Etch to the Shape and the the Cline in the visibilitywindow
: J: S/ G8 \! m6 ^982995 ALLEGRO_EDITOR INTERACTIV Shown infomation for the selected physical symbols# F$ i) H- [8 V# \
1024832 Pspice PROBE Shows wrong data & header whenexporting trace to .txt
' m% _! X, ]" _6 S9 W* F% y1063258 PSPICE AA_OPT curve fit fails with error same data works in 16.5 Simulation error: outof range of data
; c2 k' }! y. K; A1112360 PSPICE AA_OPT Advacne analysis gives runtime error whileusing Optimizer in attached design
! k/ u) d3 K- m1154323 PCB_LIBRARIAN VERIFICATION Con2con is choosing incorrect Primitivefrom Chips file and failing FTB Checks, ~& g1 w1 [# q+ T
1184690 concept_HDL CORE Weird behavior of genview forsplit hierarchical blocks
" @8 R G9 ~, u- Y# q o1212577 PSPICE MODELEDITOR IBIS translation fails without anyinformation in log file$ e; n9 ^/ ^% u/ M( I$ i
1213204 ALLEGRO_EDITOR PLACEMENT Place Manually with existing fixed netbehaving incorrectly
2 e6 }' v+ a7 Z. Z( E* D1213837 ALLEGRO_EDITOR INTERACTIV When copying a stacked via the temphighlight does not display on the last layer of the stack.
. F' Q! i6 F9 b; d& Q1216519 SPECCTRA ROUTE Autorouter will not add BB viabetween uvia within the BGA area
& G4 n* L5 P4 w4 `& \0 e8 V1220655 PSPICE DEHDL_NETLISTER Support for automatic addition for Powersource and Ground Node for Globals inDEHDL PSpice netlisting/ W h2 Z! Z* L& @- F8 B
1223018 CAPTURE OTHER Diff pair Auto Setup not workingfor the buses.+ U" p- `9 R$ C4 I& B
1225689 PSPICE AA_SMOKE Smoke analysis crashes with attachedtestcase! L5 c ~6 R: i: r( t/ h
1232124 CONCEPT_HDL COMP_BROWSER unable to generate ppt_options.dat file infirst go3 B+ u$ s$ z2 a# p4 J! T+ q5 M C
1235059 PCB_LIBRARIAN IMPORT_CSV pin_delays not being imported into PDV3 M' w% s+ Q3 h0 i" W0 f
1238815 CAPTURE OTHER Capture doesn?t retain more than191 library in add part/capture.ini under part selector configured libraries
7 d1 J7 I7 D* ?: b5 C1239241 ALLEGRO_EDITOR INTERACTIV Via replacement doesn't replace withcorrect via but right padstack name.
' W+ p! {6 A5 a+ s1240201 ALLEGRO_EDITOR EDIT_ETCH RPD DRC unresolved evenif HUD turnsGreen
' d* w3 F! ~& ?4 ?3 D8 [" c9 X1240314 PSPICE SIMULATOR Getting internal error,oveRFlow for thesecond run
z9 u) O8 r5 V. D& h% w- C9 U1242805 ALLEGRO_EDITOR DRC_CONSTR no_drc_progress_meter variable hangsallegro after running update drc! C" Q( Q: U/ ^! D$ z: p
1243267 ADW TDA URL to TDO-SharePoint should bedefined in CPM File+ T+ X6 f# M. `5 u M9 `
1244857 ADW TDA Policy File Variables not workingcorrectly in policy file
, e' u! }7 e3 f- T1245779 CONCEPT_HDL CONSTRAINT_MGR Obsolete objects in DEHDL CM0 b) @1 c" g( U4 Y- [, m" _3 D0 D
1246811 CIS EXPLORER Option to keep the part type tree inCIS explorer expanded on every invoke) K" E% @2 ]: U* Y r M: n& }
1246964 PSPICE PROBE Simulation Crashes in 16.6 butrunning successfully in 16.5" D6 f" Z3 M+ k# d3 s/ H3 O
1248782 CONCEPT_HDL CORE Display winning physical bus names(occurrence mode) in the the lower block of an Hierarchical design
9 ~8 \- K" t8 @! Q+ ^* L( p4 k1249238 CONCEPT_HDL CORE Uprev from 16.3 splatters textaround sch page$ p( {0 i8 B' Z4 i
1249692 ALLEGRO_EDITOR GRAPHICS 3D Viewer is wrong when resizing itswindow.
- o; K1 P& V! K8 q0 S1249850 ALLEGRO_EDITOR SHAPE With shape_rki_autoclip RouteKeepin to Shape DRC is created
% ^$ M. Y8 V2 o& J/ L0 i6 Z& C: G& B' B1250683 ALLEGRO_EDITOR INTERACTIV devpath corrupts if edited from userpreferences.
$ d1 d# ~" }; J# C3 Z2 F9 B1 I) Y5 G1252059 ALLEGRO_EDITOR INTERACTIV Preference Editor is unable to delete aprevious path entry for library paths. Y, v5 N% N6 A. _& l
1253563 SIP_LAYOUT DEGASSING Not getting degassing voids when closeto shape in center of design) H8 t9 @5 x5 t* ~+ M( n5 K+ G4 ]
1254319 ALLEGRO_EDITOR GRAPHICS ENH: Functionality to change the 3DModel color for more realistic view
' U% Z$ m L' a2 s: ]6 M1254562 ALLEGRO_EDITOR DATABASE Unable to delete a subclass that existonly on classes Package Keepout, Package Keepin and Route Keepin.
3 C2 ]" Y& }: r8 w" E1255169 CONCEPT_HDL OTHER ADW (BPc) Packager should reportthe specific corrupt directive in the .cpm file! d. ~# D( {+ _4 R$ s
1255573 ALLEGRO_EDITOR DRC_CONSTR Need soldermask DRC checks when same netvia and smd pad overlaps
* T7 X* b3 h* }+ E1257950 CONSTRAINT_MGR SCHEM_FTB Changing xnet name on Allegro CM.8 l/ q( a7 Z% h) I6 Z h& f) a- S
1258165 F2B DESIGNVARI changing visibility of Probe_number invariant schematic changes it to $Porbe_number( O) @0 S- K: c
1258274 PCB_LIBRARIAN VERIFICATION con2con crash with no notification orerror message' ?) S( E- ]' _2 q
1258860 CAPTURE PROJECT_MANAGER Bug: Text Editor (File> New> VHDL File)filters characters from Text
+ y( K5 \& n+ w9 H1 E% Z8 e1258872 CONCEPT_HDL CORE Objects are copied (instead ofmoved) when moved from sheet to sheet
, f8 N0 e' E: O6 p. W1259284 CONCEPT_HDL PDF HDL_POWER ( global) net does notget transferred to the published pdf/ g2 a$ E/ M( d1 B; b$ X! l
1259375 CONCEPT_HDL CORE Help link to cdnUsers.org needs tobe changed
8 r# X3 B7 t X" D. ]# \1259860 ALLEGRO_EDITOR INTERACTIV Edit > Mirror does not displayasymmetrical pad correctly when the footprint is attached to cursor.
4 M' U$ o5 d$ v: M1260002 ALLEGRO_EDITOR INTERACTIV Alt sym hard is not obeyed when usingEdit > Move > Mirror7 n. v* N. z5 x8 V7 u! }5 }9 S, o
1260006 ALLEGRO_EDITOR PLACEMENT funckey r iange 90 rotation issue
! s7 e0 B& a; } Q: O$ o1260667 ALLEGRO_EDITOR EDIT_ETCH Allegro crashes when running AICCcommand on few Diff Pair traces.
* l8 A, G& {! X% Q( x+ d1 }+ U1260763 CONCEPT_HDL CORE Export Physical fails with $TEMPentry in Setup-Tools: o) C( G2 d7 w4 G, L
1260847 SIP_LAYOUT SYMB_EDIT_APPMOD Border texts seen astriangles.
. z1 p" @- U$ i/ u8 x1260948 ALLEGRO_EDITOR SHAPE Dynamic ground shape is shorting tovia of a different net at layer 4 & 5 in this design
# j' W3 W/ E, d1262011 ALLEGRO_EDITOR PLACEMENT Key Properties on Component Instance/Definition on available to use with Quickplace by Property
. B9 z z a& b+ y1 B5 z1262322 ALLEGRO_EDITOR PADS_IN Pads_in can not translate routekeepout which specified for the all layers.
! ?" q$ S9 N. D/ Z8 ], B1 N1262626 CONCEPT_HDL CORE PROBE NUMBER attributes lost fromthe nets after upreving the design8 y# U' a! n/ u" E' M
1263592 PCB_LIBRARIAN VERIFICATION Unable to check in Schematic Model due topc.db file" c4 F; o/ I# K: h
1263685 ALLEGRO_EDITOR INTERACTIV Editing Photo Width value from non zero tozero allegro gives warning- Value must be greater or greater to zero
( ]8 S" A. v4 @& l) p. d1263704 ALLEGRO_EDITOR EDIT_ETCH Bug - AiTR wrongly deletes blind viasand do reroutes.
0 T" i6 P9 K; |' j1265120 ALLEGRO_EDITOR SHAPE Require voids in dynamic shapes touse pad value/ e$ _4 m% e( X7 ~4 d
1265275 ALLEGRO_EDITOR DRC_TIMING_CHK When XNETS are dissolved by removing theModels all Physical and Spacing NetClass associations are lost! d8 G7 N1 e% c1 b: a
1265633 PSPICE SIMULATOR Bias point result is different inconsecutive simulation run of the attached project, O3 l% m3 s; G- C
1266349 ALLEGRO_EDITOR PLACEMENT Rotating symbol while placement showwrong angle of rotation than the placed angle when Angle is set in DesignParameter
) y7 j/ r( l( d* F2 w1267541 PSPICE PROBE pspice.exe does not exit when runfrom command line( [9 y. v& ?* R8 ]2 L w; i
1267707 ALLEGRO_EDITOR PLACEMENT Mirror Command - preselect/postselectbug with general edit mode
9 T- _( j8 O2 U6 } M3 _1268299 PSPICE STABILITY Pspice crash on attached design" ~1 y3 k3 m" P1 h% I$ D
1270879 ALLEGRO_EDITOR COLOR Color view save creates .color fileusing older extension- `6 M9 d/ S5 j3 V! F
1271295 SIP_LAYOUT DIE_STACK_EDITOR Die stack editor supportneeded for large variant combination designs.
$ \9 M6 Q: V0 P% v9 g1 i1271385 CONCEPT_HDL CORE Locked property can still be added
/ J" \! q- V, Q5 K5 `0 H3 P1271853 APD OTHER When using the beta "shape tocline" command, add improved messages and partial completion of individualsegs in error.
4 d( l$ O2 M- y( u3 ~6 B- t0 Y1272197 CONCEPT_HDL CORE concepthdl_menu.txt containsinvalid Variants menu
$ m4 M) r3 ?2 I$ n- P0 {1272318 CAPTURE GEN_BOM BOM_IGNORE not working for CaptureBOM on hierarchical designs.
H+ p) K6 P) }/ a& _1272743 ALLEGRO_EDITOR PADS_IN PADS Library Translator does not openthe Options dialog window.# R, D: Y& _1 V* k: p/ A' x
1273517 F2B PACKAGERXL Netrev error - ERROR(40) Object notfound in database# p3 S+ i1 Z9 k0 j
1274000 ALLEGRO_EDITOR DATABASE PCB layer can't be removed) Z- T9 c* f2 q) g! x1 D# E0 f
1274530 ALLEGRO_EDITOR INTERACTIV Add Circle radius value changes nexttime using this command% B ?3 M; a9 i. {% q3 V: O. {
1274697 PSPICE AA_MC pspiceaa crashes when runningAdvanced analysis monte carlo for the attached design
8 u6 i4 ~ x4 g m% v2 t! t( k1275154 CONCEPT_HDL CORE Hierarchical Blocks lose refdesignators when moved to another page8 I4 n/ |7 B/ r* s4 N- l" J
1275724 GRE CORE AiDT delete another clines
! l3 F! b# k. c7 G8 l1275831 ALLEGRO_EDITOR DRC_CONSTR Waived DRCs return when usingmulti-thread DRC check$ U! O; b9 b. ^7 \5 N5 i; v
1275834 CONCEPT_HDL CORE ERROR (SPCOCD-569) on global bus
5 N4 Y* q- s5 i' f3 E1 s; g X! K1276334 ALLEGRO_EDITOR PADS_IN PADS Library Import problem withoutlines! }( D' Z9 y5 R! P% {* u5 s
1277062 ALLEGRO_EDITOR PLACEMENT Swapping parts from top to bottomOrientation changes' s. ^" R' g% i8 z/ s0 k( \
1278746 ALLEGRO_EDITOR DRC_CONSTR Package to package DRC allowsplace_bound_top in 0 spacing has drc in 16.6 version.
; ]/ {. n. E7 M1278804 CONCEPT_HDL COPY_PROJECT Copy project crashes* h' b# j0 s: I4 M2 a6 v+ j/ B" r* c! a
1279362 ALLEGRO_EDITOR INTERACTIV User skill file makes Allegro Icons goneaway) p; |4 d% n8 x5 F$ Y7 M; Z; t2 C+ B
1279619 ALLEGRO_EDITOR DRC_CONSTR Netgroup in a Netclass doesn't inheritSpacing Cset8 T2 i' ]; X7 V9 t7 l; J& r
1279815 CONCEPT_HDL CORE Text > Change and RMB Editordoes not allow multiple text edits6 H" \& Z9 ]9 Z9 F. a3 t
1279876 ALLEGRO_EDITOR DATABASE Using the Curved option in Filletsresults in a pad to shape DRC9 Y, i9 s/ Q2 w% a. L
1280435 F2B BOM BOMHDL with variant repeats thePART_NUMBER value* h! R' _+ F- t2 m
1281669 CONCEPT_HDL COMP_BROWSER Match Any radio button in ComponentBrowser didn't work.% L) s6 O1 B. M, x" K
1282001 ALLEGRO_EDITOR DRC_CONSTR Updating the DRCs on this design causethe DRC count to change on every update: e$ v6 {7 e8 `& f/ |" p8 d
1282480 SIP_LAYOUT WIREBOND Info on the Wire Count property needsto be updated indicating that it is a User Defined Property" V+ A, ^/ S4 p B+ [
1283952 ALLEGRO_EDITOR PLOTTING Published pdf does not show dotted orphantom lines
- o: E* r) ~, p% I" y- x1283957 ALLEGRO_EDITOR INTERACTIV Replace padstack in "Single ViaReplace Mode" is changing netname of the vias with the latest hotfix ofAllegro 16.6
$ M$ `' f# ~( o/ f$ M) p1285588 ALLEGRO_EDITOR DRC_CONSTR Dynamic phase control has wrong analysisresult when add rectangle test bead in Clines.! ]% T7 y3 j' i" k. H' _) ]5 c
1286743 ALLEGRO_EDITOR SHAPE Getting copper islands in thedesign after running the Delete Plating Bar command
, J, i8 K" H; U, V y0 @1287215 ALLEGRO_VIEWER OTHER Allegro viewer plus does notsupport constraint regions+ r) |+ o ~% N4 _& ?2 \( a
1288808 APD LOGIC Derive Assignment stalls out orwon?t finish and appears to run out of database room.
/ }' `2 h \( C& ~1289251 ALLEGRO_EDITOR SCHEM_FTB Pin escapes (clines and vias) notinheriting new net name from a pin with a new net name.
& U& d0 L5 Z; R& ]1 h1289293 F2B DESIGNVARI Warning 04: Cannot merge the variantproperties on variant instance C119 component with same canonical path notpresent8 d# J2 m. e, Y1 k2 }: I$ b
1289809 SCM VERILOG_IMPORT User not able to import a verilog netlistinto SCM" a; e% s0 e; L4 b! z; Y% F
1290696 CONCEPT_HDL CORE Copying a net name repeatedlycauses it to go off grid: C* R: I& [/ C R& n6 }
1291162 CONCEPT_HDL CREFER crefer crashes when selectinggenerate cross refernece for all nets selected& z S1 m2 t5 r1 c' K- a
1291285 SIP_LAYOUT IMPORT_DATA Replacing a Die with the Die Text inWizard causes some Clines to Shift, creating new DRCs.
# C4 a E, x# y1291658 ALLEGRO_EDITOR INTERACTIV Cannot add Frectangle to Group6 y# c* n6 Z7 P# s- w
1292180 ALLEGRO_EDITOR SKILL Allegro Crash while performingquery contents of "Maximum_Cavity_Size" with the skill command'axlDBGetPropDictEntry'
3 T& W* p6 Q2 Z- p+ d* c" W1292210 CONCEPT_HDL CORE DEHDL crash if design wasopened with -nonetlistuprev option.1 P/ C* ~$ O$ V, f$ i/ V
1292278 SIP_LAYOUT WIREBOND When creating Wirebonds by Importing aWirebond File, (wbt) the wirebonds are not on the correct Die layer
2 ?" z9 A1 C. |+ }& [' z+ H$ u3 S1292282 SIP_LAYOUT INTERACTIVE Getting Multiple GUIs when the WirebondImport is open and we select outside the command GUI.
; i* W A' W! ^3 @9 h) k; a1293381 SIP_LAYOUT IMPORT_DATA Import SPD2 error+ y: S; Y: q, G, i
1293889 CONCEPT_HDL PAGE_MGMT page name regression result deleted bynetassembler
/ }- Z( E6 ~) `" n5 P1294124 ALLEGRO_EDITOR INTERACTIV Samsung Mobile division wants todisappear the grids in the display window when zoom-out function executes inthe allegr1 @8 W; t- f% j) c) L: B+ Q6 J7 K/ e
1294749 ALLEGRO_EDITOR ARTWORK Null pad is flagged as an error thatbreak Thales automatic tape out/ `. L8 R/ H+ k. @* y6 x
1294777 ALLEGRO_EDITOR SYMBOL Mechanical symbols missed on STEPresult |
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发表于 2014-7-30 15:35
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