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) l* c9 N, c$ T4 K) GDATE: 07-25-2014 HOTFIX VERSION: 032
, x. Z" v; I! W. o, I===================================================================================================================================: J4 H' j7 O9 B1 B- s6 L; H
CCRID PRODUCT PRODUCTLEVEL2 TITLE& @6 p6 n5 N, J* a4 y' J
===================================================================================================================================$ a& |) q; A& ?; x) `! D
381127 SPECCTRA CROSSTALK Specctra xtalk reports aren't correct9 H" G8 r. I! f2 O5 e% h# _" @; w* n; P
616770 allegro_EDITOR COLOR Remove the APPLY button in the Color Dialog window.) F0 h( S5 K. L0 P9 m
982944 ALLEGRO_EDITOR COLOR seperate the Etch to the Shape and the the Cline in the visibilitywindow" @. D! \$ ^& u$ } d% {8 Z: ^
982995 ALLEGRO_EDITOR INTERACTIV Shown infomation for the selected physical symbols
6 N; B+ v9 l2 k6 Y8 n+ r. a1024832 Pspice PROBE Shows wrong data & header whenexporting trace to .txt
$ R8 h0 i6 r# e( z2 Y8 {- l8 j' R1063258 PSPICE AA_OPT curve fit fails with error same data works in 16.5 Simulation error: outof range of data% B C. ` J/ U
1112360 PSPICE AA_OPT Advacne analysis gives runtime error whileusing Optimizer in attached design! O: B/ E5 _' ?& R0 _+ x
1154323 PCB_LIBRARIAN VERIFICATION Con2con is choosing incorrect Primitivefrom Chips file and failing FTB Checks3 z' @1 Y3 d1 ^9 Z8 V5 z
1184690 concept_HDL CORE Weird behavior of genview forsplit hierarchical blocks4 W, Y- A( A7 M# Y |8 m4 Y6 G, X
1212577 PSPICE MODELEDITOR IBIS translation fails without anyinformation in log file
: o4 \+ a* |1 A3 H3 i; C4 R0 c& L1213204 ALLEGRO_EDITOR PLACEMENT Place Manually with existing fixed netbehaving incorrectly
4 m) R2 [ I4 Q& I3 L, i& x0 ^1213837 ALLEGRO_EDITOR INTERACTIV When copying a stacked via the temphighlight does not display on the last layer of the stack.
, A! e4 J% K6 ?% n2 [, ]3 T) V& `# r1216519 SPECCTRA ROUTE Autorouter will not add BB viabetween uvia within the BGA area
5 b7 {0 Z6 v' R9 }/ w; c; @1220655 PSPICE DEHDL_NETLISTER Support for automatic addition for Powersource and Ground Node for Globals inDEHDL PSpice netlisting
4 @. R+ o& R3 p$ p1223018 CAPTURE OTHER Diff pair Auto Setup not workingfor the buses.
+ Y: `+ j, k+ H m6 q4 U1225689 PSPICE AA_SMOKE Smoke analysis crashes with attachedtestcase
3 i! u2 l: f# e4 u1232124 CONCEPT_HDL COMP_BROWSER unable to generate ppt_options.dat file infirst go
' ?# S+ r+ A0 z1235059 PCB_LIBRARIAN IMPORT_CSV pin_delays not being imported into PDV# E: [- F6 u, `. E4 F% h
1238815 CAPTURE OTHER Capture doesn?t retain more than191 library in add part/capture.ini under part selector configured libraries
' H* {! ~% U. }, n1239241 ALLEGRO_EDITOR INTERACTIV Via replacement doesn't replace withcorrect via but right padstack name.
7 ]% E4 F Z% ?$ [2 p8 A4 Y1240201 ALLEGRO_EDITOR EDIT_ETCH RPD DRC unresolved evenif HUD turnsGreen
E0 s! P$ s5 w& R4 E1240314 PSPICE SIMULATOR Getting internal error,oveRFlow for thesecond run
( i1 v* `. I: x9 C+ |1242805 ALLEGRO_EDITOR DRC_CONSTR no_drc_progress_meter variable hangsallegro after running update drc
% T1 K, [% G( o$ E1243267 ADW TDA URL to TDO-SharePoint should bedefined in CPM File
0 n) l0 z8 ^% M ?3 y1244857 ADW TDA Policy File Variables not workingcorrectly in policy file8 u9 ^2 q9 Z4 x
1245779 CONCEPT_HDL CONSTRAINT_MGR Obsolete objects in DEHDL CM% x, \5 q' r; n( h. {
1246811 CIS EXPLORER Option to keep the part type tree inCIS explorer expanded on every invoke1 V' e% i) J4 x. S1 @9 F0 U6 q' {
1246964 PSPICE PROBE Simulation Crashes in 16.6 butrunning successfully in 16.5' Q3 B/ g/ f3 X* j8 c
1248782 CONCEPT_HDL CORE Display winning physical bus names(occurrence mode) in the the lower block of an Hierarchical design
+ z% G W3 v$ E- e5 E% g1249238 CONCEPT_HDL CORE Uprev from 16.3 splatters textaround sch page; |( C5 H& F" x9 b# o5 \) c |
1249692 ALLEGRO_EDITOR GRAPHICS 3D Viewer is wrong when resizing itswindow.4 {' b* ?6 G7 f2 M% L
1249850 ALLEGRO_EDITOR SHAPE With shape_rki_autoclip RouteKeepin to Shape DRC is created j: }1 i& W4 `. n' Q _/ D
1250683 ALLEGRO_EDITOR INTERACTIV devpath corrupts if edited from userpreferences.
( f& t* j7 x6 [8 _) q1252059 ALLEGRO_EDITOR INTERACTIV Preference Editor is unable to delete aprevious path entry for library paths9 ]! W K _; d7 Y
1253563 SIP_LAYOUT DEGASSING Not getting degassing voids when closeto shape in center of design9 b: ?, u2 P2 C8 B; ~
1254319 ALLEGRO_EDITOR GRAPHICS ENH: Functionality to change the 3DModel color for more realistic view
0 I2 @1 v% e, A' n3 |! u$ u1254562 ALLEGRO_EDITOR DATABASE Unable to delete a subclass that existonly on classes Package Keepout, Package Keepin and Route Keepin.
/ s2 Z% i1 s: C1255169 CONCEPT_HDL OTHER ADW (BPc) Packager should reportthe specific corrupt directive in the .cpm file
6 N% Y$ w0 b; R& A& X1255573 ALLEGRO_EDITOR DRC_CONSTR Need soldermask DRC checks when same netvia and smd pad overlaps
4 u: A. _$ a; E! q- I0 t) e, K1257950 CONSTRAINT_MGR SCHEM_FTB Changing xnet name on Allegro CM.2 E, d' e# a( }2 F+ L% B& w
1258165 F2B DESIGNVARI changing visibility of Probe_number invariant schematic changes it to $Porbe_number3 D9 X' d" S$ b8 M1 B+ I
1258274 PCB_LIBRARIAN VERIFICATION con2con crash with no notification orerror message$ B. t4 P4 _6 N! U. ?- F9 x! ^& c. a
1258860 CAPTURE PROJECT_MANAGER Bug: Text Editor (File> New> VHDL File)filters characters from Text1 ^5 ]8 P0 G0 \. n& {
1258872 CONCEPT_HDL CORE Objects are copied (instead ofmoved) when moved from sheet to sheet, n. }- I" O: B$ f" t/ p/ t
1259284 CONCEPT_HDL PDF HDL_POWER ( global) net does notget transferred to the published pdf
% b( t9 x) e! @8 f1259375 CONCEPT_HDL CORE Help link to cdnUsers.org needs tobe changed {; l# o6 v& O+ D9 N: R' e7 o
1259860 ALLEGRO_EDITOR INTERACTIV Edit > Mirror does not displayasymmetrical pad correctly when the footprint is attached to cursor.6 s' a7 j0 j5 E9 q
1260002 ALLEGRO_EDITOR INTERACTIV Alt sym hard is not obeyed when usingEdit > Move > Mirror
9 s3 y: d0 ]* b9 P+ H1260006 ALLEGRO_EDITOR PLACEMENT funckey r iange 90 rotation issue4 _& [9 b6 e: S7 n) W3 i
1260667 ALLEGRO_EDITOR EDIT_ETCH Allegro crashes when running AICCcommand on few Diff Pair traces.
4 }' ~5 I9 r) u/ X9 h2 j( c1260763 CONCEPT_HDL CORE Export Physical fails with $TEMPentry in Setup-Tools! U n" P$ C/ i' n& j
1260847 SIP_LAYOUT SYMB_EDIT_APPMOD Border texts seen astriangles.
o* d+ l3 i0 M$ ~# o: L( G1260948 ALLEGRO_EDITOR SHAPE Dynamic ground shape is shorting tovia of a different net at layer 4 & 5 in this design
% k! Q. n8 [2 w9 Y1262011 ALLEGRO_EDITOR PLACEMENT Key Properties on Component Instance/Definition on available to use with Quickplace by Property$ V+ j8 C+ @' y/ o
1262322 ALLEGRO_EDITOR PADS_IN Pads_in can not translate routekeepout which specified for the all layers.1 v2 d4 M6 P+ ?
1262626 CONCEPT_HDL CORE PROBE NUMBER attributes lost fromthe nets after upreving the design, s+ X; N( H* @( y }1 {
1263592 PCB_LIBRARIAN VERIFICATION Unable to check in Schematic Model due topc.db file1 ~, ]: e |6 G
1263685 ALLEGRO_EDITOR INTERACTIV Editing Photo Width value from non zero tozero allegro gives warning- Value must be greater or greater to zero+ k" X* R" e7 l* G3 g
1263704 ALLEGRO_EDITOR EDIT_ETCH Bug - AiTR wrongly deletes blind viasand do reroutes.
( ^# ?9 ^ C/ X1265120 ALLEGRO_EDITOR SHAPE Require voids in dynamic shapes touse pad value8 `9 z, y% _4 M% s) o# n! b9 ?3 r
1265275 ALLEGRO_EDITOR DRC_TIMING_CHK When XNETS are dissolved by removing theModels all Physical and Spacing NetClass associations are lost
) ^" Q& M9 G; |1265633 PSPICE SIMULATOR Bias point result is different inconsecutive simulation run of the attached project% x6 {5 [- |) y4 p2 f9 ~$ e
1266349 ALLEGRO_EDITOR PLACEMENT Rotating symbol while placement showwrong angle of rotation than the placed angle when Angle is set in DesignParameter$ ^. g3 T0 H- k3 k( x1 X$ ]
1267541 PSPICE PROBE pspice.exe does not exit when runfrom command line
" `) O$ @" q+ p) z1 Q6 c- Q1267707 ALLEGRO_EDITOR PLACEMENT Mirror Command - preselect/postselectbug with general edit mode
, i- ~. R3 w _- M3 y1268299 PSPICE STABILITY Pspice crash on attached design
: E. W8 w3 H! I. L( B1270879 ALLEGRO_EDITOR COLOR Color view save creates .color fileusing older extension
. Q) C- x3 w3 q/ \: y6 l1271295 SIP_LAYOUT DIE_STACK_EDITOR Die stack editor supportneeded for large variant combination designs.# E/ f5 ]5 Y2 i! T# x0 L6 w
1271385 CONCEPT_HDL CORE Locked property can still be added5 }! ]+ W9 }" {. t" x6 W0 L: F
1271853 APD OTHER When using the beta "shape tocline" command, add improved messages and partial completion of individualsegs in error.
6 }' s% [ L6 E' H1272197 CONCEPT_HDL CORE concepthdl_menu.txt containsinvalid Variants menu
% ^% N. j# [6 X; t& J1272318 CAPTURE GEN_BOM BOM_IGNORE not working for CaptureBOM on hierarchical designs.. m. A2 l' I7 ? G
1272743 ALLEGRO_EDITOR PADS_IN PADS Library Translator does not openthe Options dialog window.
: o6 F: |/ L5 V# T4 R8 h1273517 F2B PACKAGERXL Netrev error - ERROR(40) Object notfound in database0 ^+ D1 ` B3 S% t% I6 \4 y5 O/ J2 h3 [
1274000 ALLEGRO_EDITOR DATABASE PCB layer can't be removed1 {8 a8 Z$ [# J6 Z1 @ v
1274530 ALLEGRO_EDITOR INTERACTIV Add Circle radius value changes nexttime using this command8 ^. q; ^3 |9 K0 S! s4 ^
1274697 PSPICE AA_MC pspiceaa crashes when runningAdvanced analysis monte carlo for the attached design6 ^' e8 y* t. D
1275154 CONCEPT_HDL CORE Hierarchical Blocks lose refdesignators when moved to another page- v# l3 L+ N0 D; @7 p! ~. t+ s
1275724 GRE CORE AiDT delete another clines% D ~6 T9 y1 |& W; s; o
1275831 ALLEGRO_EDITOR DRC_CONSTR Waived DRCs return when usingmulti-thread DRC check- {, @% ~, ?; E2 l9 j
1275834 CONCEPT_HDL CORE ERROR (SPCOCD-569) on global bus! Y: o5 k( _9 A) Y; K+ k: o
1276334 ALLEGRO_EDITOR PADS_IN PADS Library Import problem withoutlines; F1 E$ `8 p3 C7 H6 t
1277062 ALLEGRO_EDITOR PLACEMENT Swapping parts from top to bottomOrientation changes
0 I4 h' @6 G- S1 A- m' ? k1278746 ALLEGRO_EDITOR DRC_CONSTR Package to package DRC allowsplace_bound_top in 0 spacing has drc in 16.6 version.
6 r, a# P) G% ^" e7 Y7 t" F$ l1 J1278804 CONCEPT_HDL COPY_PROJECT Copy project crashes% e5 V* n5 |* m
1279362 ALLEGRO_EDITOR INTERACTIV User skill file makes Allegro Icons goneaway
8 J6 g. _3 b, ~4 B" g1279619 ALLEGRO_EDITOR DRC_CONSTR Netgroup in a Netclass doesn't inheritSpacing Cset ]& v# Y6 U! D& g* d! J8 V
1279815 CONCEPT_HDL CORE Text > Change and RMB Editordoes not allow multiple text edits8 u6 ~3 h% Z) j6 @
1279876 ALLEGRO_EDITOR DATABASE Using the Curved option in Filletsresults in a pad to shape DRC
`/ i( w- N- X# |4 |1280435 F2B BOM BOMHDL with variant repeats thePART_NUMBER value
* g: t6 x0 n5 q5 w1281669 CONCEPT_HDL COMP_BROWSER Match Any radio button in ComponentBrowser didn't work." n X" y+ B; `( _$ W
1282001 ALLEGRO_EDITOR DRC_CONSTR Updating the DRCs on this design causethe DRC count to change on every update+ [/ T8 P' m2 }, v+ G B( U
1282480 SIP_LAYOUT WIREBOND Info on the Wire Count property needsto be updated indicating that it is a User Defined Property% I' m$ u: }9 @2 s! E
1283952 ALLEGRO_EDITOR PLOTTING Published pdf does not show dotted orphantom lines/ P# }5 ?& w1 b/ G$ R
1283957 ALLEGRO_EDITOR INTERACTIV Replace padstack in "Single ViaReplace Mode" is changing netname of the vias with the latest hotfix ofAllegro 16.6
/ J( k: Z# w/ ^1285588 ALLEGRO_EDITOR DRC_CONSTR Dynamic phase control has wrong analysisresult when add rectangle test bead in Clines.* } l3 `( @0 F0 q
1286743 ALLEGRO_EDITOR SHAPE Getting copper islands in thedesign after running the Delete Plating Bar command
; ^: X0 h7 |& C" A) m8 w1287215 ALLEGRO_VIEWER OTHER Allegro viewer plus does notsupport constraint regions
8 s( `: Q8 b3 S% z/ D0 [' O( V1288808 APD LOGIC Derive Assignment stalls out orwon?t finish and appears to run out of database room.
7 \; ^3 E9 [8 K' C. R# H! \- m% ~( k1289251 ALLEGRO_EDITOR SCHEM_FTB Pin escapes (clines and vias) notinheriting new net name from a pin with a new net name.( C( i8 m7 P6 Q" I8 a( g! c
1289293 F2B DESIGNVARI Warning 04: Cannot merge the variantproperties on variant instance C119 component with same canonical path notpresent
. q, E8 G" M2 {# l9 j/ G, o% L1289809 SCM VERILOG_IMPORT User not able to import a verilog netlistinto SCM+ F' r H3 S0 Y, O! v5 t
1290696 CONCEPT_HDL CORE Copying a net name repeatedlycauses it to go off grid
! M& V2 A8 c) d& B1 Y! g1291162 CONCEPT_HDL CREFER crefer crashes when selectinggenerate cross refernece for all nets selected* a5 A2 E( z: `( \0 k
1291285 SIP_LAYOUT IMPORT_DATA Replacing a Die with the Die Text inWizard causes some Clines to Shift, creating new DRCs.$ ~9 Y8 d, h6 s' L; ^, c
1291658 ALLEGRO_EDITOR INTERACTIV Cannot add Frectangle to Group
# o5 A- m1 s0 e6 Q1292180 ALLEGRO_EDITOR SKILL Allegro Crash while performingquery contents of "Maximum_Cavity_Size" with the skill command'axlDBGetPropDictEntry'
7 F* Z/ D: r' J5 z% o1292210 CONCEPT_HDL CORE DEHDL crash if design wasopened with -nonetlistuprev option.
' F" }# l+ y# `! L! K1292278 SIP_LAYOUT WIREBOND When creating Wirebonds by Importing aWirebond File, (wbt) the wirebonds are not on the correct Die layer& s( i. R4 u' ^/ b
1292282 SIP_LAYOUT INTERACTIVE Getting Multiple GUIs when the WirebondImport is open and we select outside the command GUI.
Z M) S6 ?1 ?+ I1293381 SIP_LAYOUT IMPORT_DATA Import SPD2 error
?3 b7 Q: ?5 K+ p, V1293889 CONCEPT_HDL PAGE_MGMT page name regression result deleted bynetassembler" U" c/ @/ E4 k, g9 d
1294124 ALLEGRO_EDITOR INTERACTIV Samsung Mobile division wants todisappear the grids in the display window when zoom-out function executes inthe allegr
. Z+ ]+ b, p7 p0 i! Q! S( V: D1294749 ALLEGRO_EDITOR ARTWORK Null pad is flagged as an error thatbreak Thales automatic tape out
F' D, x' }8 U* w9 K) z1294777 ALLEGRO_EDITOR SYMBOL Mechanical symbols missed on STEPresult |
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发表于 2014-7-30 15:35
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