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allegro 中报如下错怎么解决？
: D1 L, J' {+ t0 ~. cWARNINGS:
" @- t1 h+ T) SDml model tdr_out is duplicated 2 times in libraries( V- c% Y% B; G% v: \% j
D:\cadence\SPB_16.6\share\local\pcb\signal\cds_samples.dml D:\Cadence\SPB_16.6\share\pcb\signal\cds_samples.dml.
% O3 M- U# b8 K( JDml model se_test_fixture is duplicated 2 times in libraries
3 }% V2 q- {4 P6 l D:\Cadence\SPB_16.6\share\local\pcb\signal\cds_samples.dml D:\Cadence\SPB_16.6\share\pcb\signal\cds_samples.dml.' b) y# o/ P/ `0 z0 B5 A; K3 Q$ d
Dml model scope_in is duplicated 2 times in libraries
+ w6 @) ^$ \% u) ]/ Q D:\Cadence\SPB_16.6\share\local\pcb\signal\cds_samples.dml D:\Cadence\SPB_16.6\share\pcb\signal\cds_samples.dml.' s' w+ W% L$ F+ L8 d
Dml model resistorPack_850 is duplicated 2 times in libraries: b% Z# ^2 L, _' h4 L* |3 e
D:\Cadence\SPB_16.6\share\local\pcb\signal\cds_samples.dml D:\Cadence\SPB_16.6\share\pcb\signal\cds_samples.dml.
$ z0 v( f9 \. w5 J- Q- o+ ]( P7 ZDml model resistor50 is duplicated 2 times in libraries
E2 a( V5 K3 z% f ? D:\Cadence\SPB_16.6\share\local\pcb\signal\cds_samples.dml D:\Cadence\SPB_16.6\share\pcb\signal\cds_samples.dml.; [9 @5 a6 e6 W# S5 N- B
Dml model p14u1_sparam_pkg is duplicated 2 times in libraries3 c, r, b" E9 r& P6 c* P4 r; V
D:\Cadence\SPB_16.6\share\local\pcb\signal\cds_samples.dml D:\Cadence\SPB_16.6\share\pcb\signal\cds_samples.dml.
j1 q: W; k: w) a1 GDml model p14u1_modsel is duplicated 2 times in libraries# H5 P4 u, o) [! E+ k* z
D:\Cadence\SPB_16.6\share\local\pcb\signal\cds_samples.dml D:\Cadence\SPB_16.6\share\pcb\signal\cds_samples.dml.
2 F# s x: r9 _% d! F7 jDml model p14u1_diffPair is duplicated 2 times in libraries" K( g3 c7 I1 q% ~( \' f
D:\Cadence\SPB_16.6\share\local\pcb\signal\cds_samples.dml D:\Cadence\SPB_16.6\share\pcb\signal\cds_samples.dml.5 t7 `, e3 T% a
Dml model p14u1 is duplicated 2 times in libraries2 |) D7 C% g( W; n# p
D:\Cadence\SPB_16.6\share\local\pcb\signal\cds_samples.dml D:\Cadence\SPB_16.6\share\pcb\signal\cds_samples.dml.
( c" R( h3 n2 [0 d: L* o' k) GDml model lvdsload is duplicated 2 times in libraries
! z3 C/ R/ g$ F I( N4 \3 g- b3 y D:\Cadence\SPB_16.6\share\local\pcb\signal\cds_samples.dml D:\Cadence\SPB_16.6\share\pcb\signal\cds_samples.dml.8 L4 ?& ]3 @' Y1 B$ A
Dml model inductor15nH is duplicated 2 times in libraries
$ r3 ]$ W! X2 Q; l' Z D:\Cadence\SPB_16.6\share\local\pcb\signal\cds_samples.dml D:\Cadence\SPB_16.6\share\pcb\signal\cds_samples.dml.
4 e+ v; ]/ T W o! f3 mDml model capacitor20pF is duplicated 2 times in libraries& j) p4 W8 Y) y8 Q& x0 [" e
D:\Cadence\SPB_16.6\share\local\pcb\signal\cds_samples.dml D:\Cadence\SPB_16.6\share\pcb\signal\cds_samples.dml.% T1 T- F/ S0 b& j. k8 C: |( o7 E
Dml model cable_espice is duplicated 2 times in libraries3 o8 w1 ^. ]8 y/ n$ s6 Z
D:\Cadence\SPB_16.6\share\local\pcb\signal\cds_samples.dml D:\Cadence\SPB_16.6\share\pcb\signal\cds_samples.dml.
/ Y, u. q* v0 ~! a0 j# @Dml model blm2_pos is duplicated 2 times in libraries
. f( W; _( L9 @2 n; y, w2 W D:\Cadence\SPB_16.6\share\local\pcb\signal\cds_samples.dml D:\Cadence\SPB_16.6\share\pcb\signal\cds_samples.dml.6 d9 n. x" I$ k8 j/ s* o
Dml model TestPt_ESpice is duplicated 2 times in libraries
4 o6 L% R% B! d$ F7 Q& N9 y3 t D:\Cadence\SPB_16.6\share\local\pcb\signal\cds_samples.dml D:\Cadence\SPB_16.6\share\pcb\signal\cds_samples.dml.
; _8 ?4 S& e p* GDml model ScopeProbe2 is duplicated 2 times in libraries! b$ t# Y# U) ~
D:\Cadence\SPB_16.6\share\local\pcb\signal\cds_samples.dml D:\Cadence\SPB_16.6\share\pcb\signal\cds_samples.dml.. R, ~# ]9 J4 \/ e# y( _* b. x
Dml model ScopeProbe1 is duplicated 2 times in libraries
, {( l& ]' H) L- A9 J( a D:\Cadence\SPB_16.6\share\local\pcb\signal\cds_samples.dml D:\Cadence\SPB_16.6\share\pcb\signal\cds_samples.dml.
4 R3 K6 X U5 D( l! `0 HDml model R50_withpkg is duplicated 2 times in libraries
4 r) c+ ~& h) f% r8 \5 q: o, C D:\Cadence\SPB_16.6\share\local\pcb\signal\cds_samples.dml D:\Cadence\SPB_16.6\share\pcb\signal\cds_samples.dml.
( s" L. S/ K7 ^2 g( BDml model PCIxload is duplicated 2 times in libraries
Z) g# N3 v# W, j; y; d1 m; g D:\Cadence\SPB_16.6\share\local\pcb\signal\cds_PCIx_samples.dml D:\Cadence\SPB_16.6\share\pcb\signal\cds_PCIx_samples.dml.; ]. S$ A! Y) j/ ~0 V
Dml model FourWireCable is duplicated 2 times in libraries9 [3 c- S6 `6 ?1 R, M g
D:\Cadence\SPB_16.6\share\local\pcb\signal\cds_samples.dml D:\Cadence\SPB_16.6\share\pcb\signal\cds_samples.dml.! p$ ~8 U( y) @* O0 |& J
Dml model EightPin_3p3v is duplicated 2 times in libraries4 {/ |7 h R" D7 O, \
D:\Cadence\SPB_16.6\share\local\pcb\signal\cds_samples.dml D:\Cadence\SPB_16.6\share\pcb\signal\cds_samples.dml.
1 ?; y$ t0 ~0 xDml model EightPin_2p5v is duplicated 2 times in libraries8 K5 x3 t _6 }' @! ~
D:\Cadence\SPB_16.6\share\local\pcb\signal\cds_samples.dml D:\Cadence\SPB_16.6\share\pcb\signal\cds_samples.dml./ K9 Y$ n9 f$ p, z$ @8 f
Dml model EightPin_1p8v is duplicated 2 times in libraries
: g% `3 J2 T5 Y% r D:\Cadence\SPB_16.6\share\local\pcb\signal\cds_samples.dml D:\Cadence\SPB_16.6\share\pcb\signal\cds_samples.dml.
) d% }1 D, y* Z: c( MDml model DummyProbe is duplicated 2 times in libraries
& H$ j# [2 R' O, n2 N3 n D:\Cadence\SPB_16.6\share\local\pcb\signal\cds_iocells.dml D:\Cadence\SPB_16.6\share\pcb\signal\cds_iocells.dml.
# T; w7 m) i7 A! o: s# {% ~Dml model CDS_lvds_out is duplicated 2 times in libraries; I/ b; g( R/ |' {4 Z
D:\Cadence\SPB_16.6\share\local\pcb\signal\cds_iocells.dml D:\Cadence\SPB_16.6\share\pcb\signal\cds_iocells.dml.$ j7 P W9 E6 d, |$ Y( K
Dml model CDS_lvds_in is duplicated 2 times in libraries
) H" }2 [5 T( r$ {& e. ^; B D:\Cadence\SPB_16.6\share\local\pcb\signal\cds_iocells.dml D:\Cadence\SPB_16.6\share\pcb\signal\cds_iocells.dml.
, v k, D$ I4 }0 z" Q. r7 eDml model CDS_lvds_device is duplicated 2 times in libraries0 Z0 r8 M8 T r/ }! @1 F
D:\Cadence\SPB_16.6\share\local\pcb\signal\cds_samples.dml D:\Cadence\SPB_16.6\share\pcb\signal\cds_samples.dml.
$ b8 A; s7 g% \5 k4 R' R: ^1 [% YDml model CDS_Pkg16DIP is duplicated 2 times in libraries9 B/ Q) a$ j8 ]' D, x
D:\Cadence\SPB_16.6\share\local\pcb\signal\cds_packages.dml D:\Cadence\SPB_16.6\share\pcb\signal\cds_packages.dml.' R: F% B; R2 T. T
Dml model CDS_Pkg14DIP_Sparse is duplicated 2 times in libraries
& `; q! e% R" r% L) C( K! x D:\Cadence\SPB_16.6\share\local\pcb\signal\cds_packages.dml D:\Cadence\SPB_16.6\share\pcb\signal\cds_packages.dml.$ d' n; P4 [7 O" v9 A8 Y4 n
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发表于 2014-5-8 08:50
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支持！
反对！