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Allegro 中报错Dml model tdr_out is duplicated 2 times in libraries!详情如下!

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发表于 2014-5-8 08:50 | 只看该作者 回帖奖励 |倒序浏览 |阅读模式

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allegro 中报如下错怎么解决?
1 x) T3 m- Z: ZWARNINGS:3 U! O3 z# x% k4 }2 W+ f3 a
Dml model tdr_out is duplicated 2 times in libraries6 z# l  W$ X$ H3 T8 s% E
         D:\cadence\SPB_16.6\share\local\pcb\signal\cds_samples.dml D:\Cadence\SPB_16.6\share\pcb\signal\cds_samples.dml.
: `5 n' U5 I* ^" P, HDml model se_test_fixture is duplicated 2 times in libraries9 _, I9 P; ]/ P  F
         D:\Cadence\SPB_16.6\share\local\pcb\signal\cds_samples.dml D:\Cadence\SPB_16.6\share\pcb\signal\cds_samples.dml.3 C$ H$ ^! A9 H9 ~, H, B
Dml model scope_in is duplicated 2 times in libraries/ z! t  Z, C) ?* b4 b
         D:\Cadence\SPB_16.6\share\local\pcb\signal\cds_samples.dml D:\Cadence\SPB_16.6\share\pcb\signal\cds_samples.dml.
  f! _- I7 I2 Y" C4 J1 w- vDml model resistorPack_850 is duplicated 2 times in libraries; t: Y6 c9 c4 J" @" m
         D:\Cadence\SPB_16.6\share\local\pcb\signal\cds_samples.dml D:\Cadence\SPB_16.6\share\pcb\signal\cds_samples.dml.; ]" ~& t0 m& D
Dml model resistor50 is duplicated 2 times in libraries  D2 a2 W- [8 |9 \8 ^& u
         D:\Cadence\SPB_16.6\share\local\pcb\signal\cds_samples.dml D:\Cadence\SPB_16.6\share\pcb\signal\cds_samples.dml.
: o$ y9 _- k8 @" I9 }' lDml model p14u1_sparam_pkg is duplicated 2 times in libraries: v0 U1 D' O! X, q0 l- @
         D:\Cadence\SPB_16.6\share\local\pcb\signal\cds_samples.dml D:\Cadence\SPB_16.6\share\pcb\signal\cds_samples.dml.% n( V7 {0 s1 R3 U7 R: N
Dml model p14u1_modsel is duplicated 2 times in libraries
' K+ E1 J2 M0 t         D:\Cadence\SPB_16.6\share\local\pcb\signal\cds_samples.dml D:\Cadence\SPB_16.6\share\pcb\signal\cds_samples.dml.
+ _9 r! b5 S7 f9 C7 D3 ?Dml model p14u1_diffPair is duplicated 2 times in libraries8 q0 w4 u# k- Z0 f
         D:\Cadence\SPB_16.6\share\local\pcb\signal\cds_samples.dml D:\Cadence\SPB_16.6\share\pcb\signal\cds_samples.dml.
6 `8 H4 b, R9 G: LDml model p14u1 is duplicated 2 times in libraries
8 Y/ P$ W, [2 J         D:\Cadence\SPB_16.6\share\local\pcb\signal\cds_samples.dml D:\Cadence\SPB_16.6\share\pcb\signal\cds_samples.dml., ]; M0 V: B; d6 a( M; [7 u6 N
Dml model lvdsload is duplicated 2 times in libraries
, P% z$ B+ l0 @% B9 }0 y/ g! {, g. D) w# h         D:\Cadence\SPB_16.6\share\local\pcb\signal\cds_samples.dml D:\Cadence\SPB_16.6\share\pcb\signal\cds_samples.dml.1 ~- f: V, B4 c$ I. P
Dml model inductor15nH is duplicated 2 times in libraries# G. {# }! G  e: W; B
         D:\Cadence\SPB_16.6\share\local\pcb\signal\cds_samples.dml D:\Cadence\SPB_16.6\share\pcb\signal\cds_samples.dml.2 j, r9 c2 f* k3 X0 k" _' @
Dml model capacitor20pF is duplicated 2 times in libraries
# @6 `2 d! v9 c! h         D:\Cadence\SPB_16.6\share\local\pcb\signal\cds_samples.dml D:\Cadence\SPB_16.6\share\pcb\signal\cds_samples.dml.
* k8 `% J9 e( g% D/ XDml model cable_espice is duplicated 2 times in libraries4 \3 [& i* V. |8 e9 U
         D:\Cadence\SPB_16.6\share\local\pcb\signal\cds_samples.dml D:\Cadence\SPB_16.6\share\pcb\signal\cds_samples.dml.
* \; A* Q' |! B3 aDml model blm2_pos is duplicated 2 times in libraries$ l6 o  r" }; G  z! s- E8 R* p
         D:\Cadence\SPB_16.6\share\local\pcb\signal\cds_samples.dml D:\Cadence\SPB_16.6\share\pcb\signal\cds_samples.dml.
8 N6 L( @' Y- vDml model TestPt_ESpice is duplicated 2 times in libraries" Z/ K' E3 j( U4 ^
         D:\Cadence\SPB_16.6\share\local\pcb\signal\cds_samples.dml D:\Cadence\SPB_16.6\share\pcb\signal\cds_samples.dml.
. c7 |0 [' _1 R( E, S3 EDml model ScopeProbe2 is duplicated 2 times in libraries- L; K( B, t4 x1 m$ `- v( V0 L9 M
         D:\Cadence\SPB_16.6\share\local\pcb\signal\cds_samples.dml D:\Cadence\SPB_16.6\share\pcb\signal\cds_samples.dml.
  |, Y& V& ~6 f. m$ S% MDml model ScopeProbe1 is duplicated 2 times in libraries1 L3 Z1 g  h) y
         D:\Cadence\SPB_16.6\share\local\pcb\signal\cds_samples.dml D:\Cadence\SPB_16.6\share\pcb\signal\cds_samples.dml.9 m7 w# Q$ y0 n: J( ]1 d
Dml model R50_withpkg is duplicated 2 times in libraries
5 L& v; m% Y; ^3 c         D:\Cadence\SPB_16.6\share\local\pcb\signal\cds_samples.dml D:\Cadence\SPB_16.6\share\pcb\signal\cds_samples.dml.0 {* s/ X# a! E8 r* q( p& B; E6 T
Dml model PCIxload is duplicated 2 times in libraries
( [9 @2 |& t  j; v5 }2 d5 E! o3 Y         D:\Cadence\SPB_16.6\share\local\pcb\signal\cds_PCIx_samples.dml D:\Cadence\SPB_16.6\share\pcb\signal\cds_PCIx_samples.dml.
+ [& E) f: z8 lDml model FourWireCable is duplicated 2 times in libraries( R8 q/ c# _3 q; e" O) X2 J
         D:\Cadence\SPB_16.6\share\local\pcb\signal\cds_samples.dml D:\Cadence\SPB_16.6\share\pcb\signal\cds_samples.dml.0 G# H& S( N' ]2 J: {) f
Dml model EightPin_3p3v is duplicated 2 times in libraries
% ?- r3 l7 n6 s5 N9 I         D:\Cadence\SPB_16.6\share\local\pcb\signal\cds_samples.dml D:\Cadence\SPB_16.6\share\pcb\signal\cds_samples.dml.
& r$ m1 T3 t8 V" DDml model EightPin_2p5v is duplicated 2 times in libraries
0 u$ K' |! b6 }         D:\Cadence\SPB_16.6\share\local\pcb\signal\cds_samples.dml D:\Cadence\SPB_16.6\share\pcb\signal\cds_samples.dml., n# }9 t; m; C; |/ q0 t- E
Dml model EightPin_1p8v is duplicated 2 times in libraries) _6 k+ D1 O8 E6 p0 n
         D:\Cadence\SPB_16.6\share\local\pcb\signal\cds_samples.dml D:\Cadence\SPB_16.6\share\pcb\signal\cds_samples.dml.1 c" V& i/ e! E) v
Dml model DummyProbe is duplicated 2 times in libraries) A2 K; P/ K. l8 ?& ]2 V
         D:\Cadence\SPB_16.6\share\local\pcb\signal\cds_iocells.dml D:\Cadence\SPB_16.6\share\pcb\signal\cds_iocells.dml.
. d, L  m. k# ?* E& I6 U- WDml model CDS_lvds_out is duplicated 2 times in libraries
$ I! C- V$ P' z6 u" C         D:\Cadence\SPB_16.6\share\local\pcb\signal\cds_iocells.dml D:\Cadence\SPB_16.6\share\pcb\signal\cds_iocells.dml.
2 V: A4 }3 x& x8 uDml model CDS_lvds_in is duplicated 2 times in libraries
( L" x; p! f% z         D:\Cadence\SPB_16.6\share\local\pcb\signal\cds_iocells.dml D:\Cadence\SPB_16.6\share\pcb\signal\cds_iocells.dml.
& `% F% r! I8 _1 z1 n5 T# P+ v/ aDml model CDS_lvds_device is duplicated 2 times in libraries
  E' c* g1 ?, U: k# ]; E         D:\Cadence\SPB_16.6\share\local\pcb\signal\cds_samples.dml D:\Cadence\SPB_16.6\share\pcb\signal\cds_samples.dml.
: `2 ]5 b/ R6 n! mDml model CDS_Pkg16DIP is duplicated 2 times in libraries9 X& O, [# B! i6 S' Q) ]+ Y' R
         D:\Cadence\SPB_16.6\share\local\pcb\signal\cds_packages.dml D:\Cadence\SPB_16.6\share\pcb\signal\cds_packages.dml.
' s) d9 r0 ?8 d) R4 G$ ZDml model CDS_Pkg14DIP_Sparse is duplicated 2 times in libraries
6 f+ e( n3 @) f4 Q: D         D:\Cadence\SPB_16.6\share\local\pcb\signal\cds_packages.dml D:\Cadence\SPB_16.6\share\pcb\signal\cds_packages.dml.% l) X0 g. E$ ^( \8 p
4 N- z3 t" i2 x& [$ u# |

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