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SPB_16.6 27号补丁下载链接--Hotfix_SPB16.60.027_wint_1of1.exe

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发表于 2014-4-26 15:15 | 只看该作者 回帖奖励 |倒序浏览 |阅读模式

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本帖最后由 Csec 于 2014-4-28 11:04 编辑
+ x: V% E. q' |. b! [" |+ T$ o" j- N# F6 M2 S- }9 M) b
http://sw.cadence.com/P/download ... e4d05&file=.exe0 r2 D$ U. L' y2 R
更新百度网盘下载链接!
% |2 E2 M  K, q4 C$ {http://pan.baidu.com/s/1mgwSsPy
( h3 C) e( Z7 z6 j" R- a$ z- M: I1 _0 A
DATE: 04-25-2014   HOTFIX VERSION: 027
$ R" f, x: n0 I* I4 m* G) L1 z===================================================================================================================================' F: G2 z: W' H( ~' W" {4 I
CCRID   PRODUCT        PRODUCTLEVEL2   TITLE2 l' k: |/ F( G7 R+ m
===================================================================================================================================
8 F" [" [8 M* X) f2 J5 I; J308701  CONSTRAINT_MGR OTHER            Needs to delete user defined schedule in CM
4 `6 {2 Z% D8 S9 ?$ V9 B481674  allegro_EDITOR pads_IN          No board file saved from PADS_in; M0 e9 b* P( e" D) b) ]
982929  ALLEGRO_EDITOR EDIT_ETCH        can't route on NC pin and other that are not pin.
* G3 L  j& G: b, \1012783 FSP            OTHER            Need Undo Command in FSP
: N* j8 e' K: Z1017381 ALLEGRO_EDITOR DRC_CONSTR       Need Dynamic Phase to be able to measure back to the Drive Pins.
* l. X( L; |! Z) y$ H6 X& X% h1072673 PCB_LIBRARIAN  GRAPHICAL_EDITOR Copy paste goes offgrid if mouse is moved) k$ {& O- v9 W
1073231 concept_HDL    CORE             Copy-paste of signal names goes off-grid in Windows mode.
0 `' p& X, {. \1 V( M% \1105371 CONCEPT_HDL    INTERFACE_DESIGN Strange behavior when shorting two Net groups
* A1 a- f0 ]6 g) v1116498 CIS            LINK_DATABASE_PA link database with modified part results in Capture crash
* k# x, D5 C; {1118632 ALLEGRO_EDITOR GRAPHICS         Text display refresh issue while in Edit > text command" ]- m) y$ O, y" y( m* P8 m
1155821 SIG_INTEGRITY  LIBRARY          Xnet are not recalculated correctly when model is changed on the Series switch part defined as discrete with Espice mode
3 i4 z- ?$ q3 J( b/ w: ?1157372 ALLEGRO_EDITOR DRC_CONSTR       Dynamic phase for Diff Pairs not reporting back to Driver pin if pin escapes present
, H8 j8 n6 g2 @: ]1171951 ALLEGRO_EDITOR CREATE_SYM       Jumper has a limited of count when it add to list.
! T8 n3 X5 L6 s8 G$ T' V) w1180871 CAPTURE        LIBRARY_EDITOR   Copied parts don't retain pin name and pin number settings  W& w: ~! T. ?/ d9 F: q
1185575 SIP_LAYOUT     DIE_STACK_EDITOR Updating symbols causes the graphics for the Assy layer to change from Bottom to Top.
' a& j$ Y" B3 I  Q1185772 PCB_LIBRARIAN  CORE             VALID_PACK_TYPE warning when cell was opened in PDV
. O$ M; z) N* h0 ?( k' d1192377 CAPTURE        SCHEMATIC_EDITOR Pin name/number position is incorrect on schematic if it is changed for a rotated part.5 u7 w9 X. P. Z
1202654 ALLEGRO_EDITOR GRAPHICS         Zoom using mouse wheel shall maintain the center co-ordinates8 N$ T8 m5 z& b$ c8 i
1208031 ALLEGRO_EDITOR INTERACTIV       Snap to Pin for via during Copy command do not snap to connect point everytime7 ~; u+ n! R: C& T3 S% D! o
1208478 Pspice         PROBE            Attached project gives overflow error with marching ON.
1 w5 p  @0 U$ R" i1210015 CONCEPT_HDL    CORE             The value of $PN should be not turned on spin or rotate symbol
- k2 e$ T& @8 R3 U1210425 CONCEPT_HDL    CORE             When moving a circuit tool reports that connectivity has changed% f4 `6 O2 I) c6 e0 f2 d
1215858 ALLEGRO_EDITOR SHAPE            Force update does not void cline with the shape4 @8 D2 U5 [0 p. [+ ]2 q
1215906 ALLEGRO_EDITOR SHAPE            Dynamic shape fill smooth failed when copying to other layers
) C: u8 J$ d# X- O1216358 CONCEPT_HDL    CORE             Can we improve our export BOM function to check if user did export physical function before exporting BOM?1 O5 o& p) r: T+ @$ u" k& Y
1217364 CONCEPT_HDL    OTHER            Netlist reports fail because error: GScald failed.
' q% F; n7 t6 c) W7 D" v2 m; k1217529 CONCEPT_HDL    CORE             ADW checks do not catch single quotes in PTF values; J. b  f; `8 e+ U" K8 s
1217556 F2B            PACKAGERXL       signal name change not sent to Allegro after packaging. r6 W! ~0 H$ |& G8 r3 b. ^
1219283 ALLEGRO_EDITOR DRC_CONSTR       Show constraint is inconsistent when displaying region information
5 G. q. O# D+ L+ V( x) ~1220078 F2B            PACKAGERXL       Export Physical crashes when ALL the part pins are added
4 u. s2 J5 D+ o' I- ]8 X$ v5 y- x1220393 CONSTRAINT_MGR CONCEPT_HDL      HDL import physical from board file will annotate CM data back to HDL which includes cross-section thickness.2 \- V2 C" e( N+ V1 j- X, C1 k% F
1220540 ALLEGRO_EDITOR GRAPHICS         Need an option to see the pads inside the internal plane shapes! \/ z/ ~9 \8 O
1220936 CONCEPT_HDL    CORE             About crash by vpadd/vpdelete command on Linux; P& o  Q" }" l% ?" L0 x. @
1221059 ALLEGRO_EDITOR DRC_CONSTR       Get a "Shape to Thru Via Spacing" DRC error only the first time when the shape is manually voided.
9 M6 Z+ N4 m+ b4 a( ^% _: b$ R6 ^1221182 ADW            TDA              Team Design with SAMBA- m% m' `( Y4 O$ T# r5 [5 ~
1222442 CONSTRAINT_MGR UI_FORMS         Duplicate pin pairs appear in DiffPair
  s" w- j$ _" Q: X. M/ p1223175 CONCEPT_HDL    CONSTRAINT_MGR   Schematic crashes when opened6 b" o. O7 y9 j& ?/ G
1223533 ALLEGRO_EDITOR GRAPHICS         Why the through pins for STEP models are shown at an offset when viewed in 3D inside Package Symbol?
# X  ^$ R% Z6 J' I9 @6 q$ o1223680 CONSTRAINT_MGR ECS_APPLY        Improve ECSet mapping by allowing user to address ambiguity of Parts  z# p9 \0 a5 U/ @1 R2 E1 T
1224156 SIG_INTEGRITY  SIGWAVE          Exporting spreadsheet with filter Subitems in SigWave exports all waveforms
0 j& U( l* i7 v6 w1224417 ALLEGRO_EDITOR PLOTTING         Hidden font pattern is not showing correct in 16.5 version also 16.6 version.
% P' R& \9 z9 i# \1224704 F2B            DESIGNVARI       There is no lock for the variant.dat file - multiple users can open the editor1 F6 b8 t; F- Q: U' |: D
1224968 ALLEGRO_EDITOR INTERACTIV       Delete >(RMB click) Cut> Snap Pick to>off grid loction does not work for lines.# R0 }2 H/ ]3 u3 P1 o
1224982 CONCEPT_HDL    PDF              commandline publishpdf does not work when there are spaces in the path
. i0 m/ [. R+ D" U- {# V. y1225114 CAPTURE        GENERAL          H-pins added after netgroup pin get color as of netgroup pin
# Z, r7 m4 F: y' p% p5 r# d1225494 CAPTURE        DRC              Different DRC results for Entire design and selection
4 w9 r- ]9 `% J1226153 ALLEGRO_EDITOR INTERFACES       Export STEP should include PART_NUMBER property0 ^* |: X" ^+ d
1226235 ALLEGRO_EDITOR EDIT_ETCH        Enhancement to include Pin_delay of descrete forming Xnet9 |/ d, W( @. ~% F; j! I$ g
1226372 CAPTURE        GENERATE_PART    ENH: Functionality to add pin spacing in New Part From Spreadsheet& l, u, J. Y, F  a  o% Z
1226477 CONCEPT_HDL    CORE             DE HDL縮 `Allowed Global Shorts?  function is inconvenient for Global Signal# o% n& q! G4 F7 V# d( P/ l
1226813 SIP_LAYOUT     LEFDEF_IF        ERROR SPMHLD-120 when importing a DEF file. Request to increase the number of characters/line in a .cml file2 I* W( W$ u: }& I) L
1227453 ALLEGRO_EDITOR SHAPE            Addition of Fillet generate Pin to Shape Spacing DRC errors and DBDOCTOR errors! O& ?2 u: f2 v! L4 [
1227461 ALLEGRO_EDITOR SHAPE            Sliding a cline for certain net changes the thermal relief connects for pins connected to another net from 4 to 5,6,7,88 ^- T' T' N7 o2 _( f1 C  D
1227469 CIS            DBC_CFG_WIZARD   Oracle Views not visible on Step2 of CIS Configuration; y0 }3 k3 Q& g! T3 y+ S
1227780 CAPTURE        ANNOTATE         Inconsistent behaviour when annotating heterogeneous part
, B" B* N" r) F& j1227831 CONCEPT_HDL    CORE             Pin text and H-block name in upper case
* P6 G& k6 h# q1227954 CONCEPT_HDL    OTHER            supress check for global signals when wires are unconnected to pins
& N4 M4 M# Y) X1228190 ALLEGRO_EDITOR OTHER            Unable to close the 'usage' window during license selection
3 v' n5 A. o) m2 x. W3 R9 `! m$ j1228899 CONSTRAINT_MGR INTERACTIV       Export/Import constraints in "overwrite" mode from same design shows different results when imported second time.1 w6 ]+ q/ B- |# j& y
1228934 ALLEGRO_EDITOR EDIT_ETCH        The "View Active Layer" option like the Board Station should be provided for dynamic layer visibility.
8 b& P% K- F5 [& j# i: F1229316 ALLEGRO_EDITOR EDIT_ETCH        When routing with Hug only enabled we were able to route through other routes(sometimes Hug).
3 A5 G* Y6 w2 T' g1229545 CONSTRAINT_MGR OTHER            Allegro indicate bundle scheduled nets in CM
" o: n5 ~6 l) O8 D; X. Z8 n2 T1230056 ALLEGRO_EDITOR GRAPHICS         Bug: 3D View of Mechanical Symbol with the drill hole defined
, E5 n1 D4 E' @& z, Y7 Q9 ]1230432 CONCEPT_HDL    CORE             No Description information in BOM, M' E$ H' d& L! j! |
1231148 F2B            DESIGNVARI       The variant.dat file is not updated with library PTF changes. @2 @0 ^( o, {$ ?( O( a
1231625 F2B            DESIGNSYNC       VDD at command line needs to support sch2sch and test variable to write out report files+ N- L8 X4 k- n! N  P1 ^3 K
1231697 CONCEPT_HDL    CORE             If any locked files exist force a pop-up dialog restricting certain commands
" @5 o$ @  U2 @' f4 S& f* M/ O8 {1231767 CONCEPT_HDL    OTHER            Unable to find under the search options single bit vector nets( b3 t8 x/ q% \
1231961 ALLEGRO_EDITOR SHAPE            Shapes not updating to smooth unless we use force update and as a result false DRC's appear in board.
) h3 K1 {. M! r5 ?5 `% t1232100 CONCEPT_HDL    skill            Unable to execute the SKILL commands in viewer mode7 h) g9 H) Y6 S0 V. [' [) I
1232336 CONSTRAINT_MGR CONCEPT_HDL      cmFeedback takes 5hrs to complete during Import Physical* J4 A, f9 n  X& x( P( O
1232710 F2B            DESIGNVARI       Dehdl crash while moving component in variant viewer mode+ y; ]. j+ x1 X3 r# b6 k! m
1233894 F2B            PACKAGERXL       The page data is missing in the pst* and PCB files
+ j+ R9 p4 f1 l1235785 CONCEPT_HDL    CREFER           cref_from_list custom text is not subsitituted in complex hierarchy
1 }; r- d+ K) ?. d5 T# T9 L$ e1235928 CAPTURE        SCHEMATIC_EDITOR OleObject modifications not saved
, p* \2 b% \, }. }1236065 CAPTURE        PART_EDITOR      Mirrored part after being edited get pin name locations incorrect9 B3 F, {, f4 G# S: Q8 H  q: m
1236071 ALLEGRO_EDITOR SHAPE            Airgap for Octagonal Pads ignores DRC Value when Thermal set
: i% E9 _, Q1 _( v" W" R1236072 CONCEPT_HDL    CORE             Page 122 cannot be saved as logical page 119 has different page mapping in connectivity data and schematic5 I7 D* R, v! X0 \8 r+ U% t
1236161 CONCEPT_HDL    CORE             Import Design shows the current project pages9 i& d% }3 r* q3 Q+ e, U$ V8 u
1236432 ALLEGRO_EDITOR PADS_IN          pads_in doesnot translate via and shape in some instances.8 @9 ]9 X  L, @! N* G2 L# Z" V
1236557 CONCEPT_HDL    PDF              Running Publish PDF on command line in linux doesn't output progress until completion
" t3 [- g, d, x% A: l5 R6 {1236589 CONCEPT_HDL    PDF              Enhancement license failure error should appear in pdfpuplisher  log file
* i" N' u7 a' z* y7 k+ M1236644 ALLEGRO_EDITOR EDIT_ETCH        create fanout deletes shape
% z3 M/ l8 Y" n9 V$ A$ g0 |1236689 ALLEGRO_EDITOR GRAPHICS         Graphics displays extraneous lines when panning or zooming% Y3 p8 ?9 }6 {" {" a* o
1236781 F2B            PACKAGERXL       Export Physical produces empty files2 k3 x( u9 a* L
1237331 PSPICE         ENVIRONMENT      pspice.exe <cir file name> - hangs when run2 N" r  U" B+ j
1237400 CIS            EXPLORER         Capture hangs on 2 consecutive runs of `refresh symbol from lib? command( [" `  w: e* g* I, E0 X$ J
1237437 CONCEPT_HDL    CONSTRAINT_MGR   CM Crash when saving after restore from definition4 b7 e1 R& J- x+ P4 u& k" k( c# C
1237862 CONSTRAINT_MGR OTHER            A way to remove the RAVEL markers from the Constraint Manager.
! f3 ^$ m1 h: q7 Y& a/ {3 _3 ?8 D% ^1238852 CAPTURE        GENERAL          signal list not updated for buses: S: h0 s1 e+ x, ^5 |( M# r
1238856 FSP            DE-HDL_SCHEMATIC FSP schematic generation crashes) x8 v/ D4 }: T% c$ ?/ k
1239079 ALLEGRO_EDITOR INTERACTIV       The 16.6 Padstack > Replace function leaves old padstack.
' D; u7 U. ~3 Q' u1239706 CONSTRAINT_MGR ANALYSIS         The reflection result on a differential signal in the CM when Measurement location is DIE9 l2 `# c: m* Y" E' {
1239763 PSPICE         PROBE            Cannot modify text label if right y axis is active
: S7 X& W4 z& ~' i4 r1240276 ALLEGRO_EDITOR GRAPHICS         Printing to PDF from SigXp is giving unreadable images
4 Q) ~  ~* @% ^+ W5 R1 g% T# q1240356 CAPTURE        IMPORT/EXPORT    Can縯 import SDT schematic to Capture.
+ e0 t8 z$ k( b+ O1240502 F2B            PACKAGERXL       Corrupt cfg_package does not stop PackagerXL from completing' q' }% f) E- P- t* H8 h
1240607 ALLEGRO_EDITOR OTHER            Footprint of screw hole got shift in DXF file  W: ^: @1 L% g
1240670 ALLEGRO_EDITOR PLACEMENT        Select multiple parts and Rotate makes them immovable( X: E; l5 b9 f2 Q; v( t# y
1240773 CAPTURE        DRC              DRC check reports error for duplicate NetGroup Reference in complex hierarchy
0 W% I  X% Z* f" n, o4 P1 q1240845 SIG_EXPLORER   EXTRACTTOP       Narrowband via models for Mirrored BB Vias not extracted in in the interconn.iml and this gives bad ringing in waveforms
; l0 m- w/ X' @4 b* A& {1241634 ALLEGRO_EDITOR OTHER            Netshort for pad-pad connect not working) [! c4 e# `$ T
1241776 CONCEPT_HDL    CORE             In hierarchal design not all pages are getting printed.
! v8 q/ e2 h$ O% Y1241788 CONSTRAINT_MGR CONCEPT_HDL      Issues with changing focus in Constraint manager using keys on keyboard
, S( B3 B1 O$ k1242683 ALLEGRO_EDITOR INTERACTIV       Color View Save replaces file without warning# J) r; s* i9 |9 F1 u5 o: z: {
1242818 ALLEGRO_EDITOR PLACEMENT        Placement edit mirror option places component on wrong side! G6 S$ ~  X3 c" f6 I
1242847 ALLEGRO_EDITOR GRAPHICS         Need an option to suppress Via Holes in 3D Viewer
7 E6 z0 O2 S# W! U" L1242923 ADW            COMPONENT_BROWSE UCB reports Missing From DB only after selecting the Row in the search results
3 E- L( ?' l* \5 @6 D1243609 CONCEPT_HDL    CORE             autoprop for occurrence properties
- e: I: X8 l: H7 t& k/ I0 L1243682 F2B            DESIGNVARI       after undocking variant icon cannot be redocked back to GUI
% g' I' e' w. J# G: m4 x1243686 ALLEGRO_EDITOR GRAPHICS         Invoking Edit->Text, the infinite cursor disappears until edit mode is changed.$ d8 @- a0 {8 ^
1243715 CAPTURE        PART_EDITOR      Pin name positioning get changed after rotating or mirroring5 t$ X; e9 c3 m
1244945 CONCEPT_HDL    PDF              PDF Publisher does not include image when file is not located in the root folder
( x4 V5 I! ?0 G- g" o$ R# d- [1245568 CONCEPT_HDL    CORE             Dual unselect needed for wires attached to other net/source and property is not deselected when component is
5 L+ V# [) X+ l* ~4 i# L1245819 F2B            PACKAGERXL       wrong injected properties information passed during packaging of the design/ J4 l8 i5 u% l
1245916 SCM            CONCEPT_IMPORT   Where does the folder location reside for DEHDL imported blocks?
& a1 {3 R4 M6 e& x( i' ^1246347 CONSTRAINT_MGR CONCEPT_HDL      DEHDL crash if environment variable path has trailing backslash character
8 E" }- `' _: |# W8 \1246896 ALLEGRO_EDITOR DFA              DFA_UPDATE on Linux reports err message if the path has Upper case characters
9 y$ {/ k2 t6 M( }& i8 B1247019 SIP_LAYOUT     DIE_STACK_EDITOR SiP Layout - refresh/update symbols is mirroring the assembly drawing data on DIE that is placed ChipDown
" ~$ [# Z  @! A1247037 CAPTURE        LIBRARY_EDITOR   Copy & Paste of library parts resets pin name and number+ C. t. z3 V: _) b1 y
1247089 CONCEPT_HDL    CORE             Group Align or Distribute > Left/Center/Right crashes DEHDL. s$ {0 S1 I: @' A7 v# R
1247163 CONCEPT_HDL    PDF              Physical Net Names in PDF not maintained
/ b$ p7 U' g! j+ |1 e! r! y1247462 CONCEPT_HDL    CORE             Text issue while moving with bounding box
! g5 [' t; w2 r1247464 ALLEGRO_EDITOR UI_FORMS         When using the define B/B via UI the end layer dropdown arrow is partially covered
. [6 x6 Q! |3 i1 P/ `3 b1249063 CONCEPT_HDL    CONSTRAINT_MGR   CM and SigXP doesn縯 respect PACK_IGNORE at components
, s) o0 u; d* P3 U) p; ?/ n7 z; f1250270 CONCEPT_HDL    CORE             Part Manager Update places wrong parts
8 {: B! n$ g3 }- r% T4 ^1251206 ALLEGRO_EDITOR ARTWORK          Aperture command cannot create appropriate aperture automatically from design.  W' i$ w4 R# @% Z; N
1251356 ALLEGRO_EDITOR INTERFACES       Some STEP models are missing in 3D view of footprint, although all components have STEP model mapped in footprint
9 A% V3 j+ Z* q9 T! t5 d1251845 ALLEGRO_EDITOR EXTRACT          Crosshatch arcs do not extract correctly/ E! H, Z/ M# U, k
1252143 APD            OTHER            When using the beta "shape to cline" command the tool is removing the shape instead of converting it.% p7 e/ s$ D  p
1252737 SIP_LAYOUT     OTHER            SiP Layout - Option to create shapes from Pins for WLP wafer level packaging technologies, i: S( }" _, k6 Z$ u' ~
1253424 SCM            SCHGEN           Export Schematics Crashes System Architect
, o( Y2 L6 {2 R, o/ r1253508 ALLEGRO_EDITOR INTERFACES       Bug - Export IPC2581 exports Crosshatch shapes as filled
, N$ [/ Z3 \1 v! K1253554 SIP_LAYOUT     OTHER            SiP Layout - Add Netlist Spreadsheet export to SiP layout to help with connectivity auditing
. l# ^, f) W. G& o" W1254578 SPIF           OTHER            Specctra crash with Error -1073741819 for Auto router* C% v# J7 j4 a; _2 _
1254637 ALLEGRO_EDITOR DRC_TIMING_CHK   adding nets to a net group causes constraint assignment error7 u8 v, ?6 W: B* ^! Q8 B, f
1254676 GRE            IFP_INTERACTIVE  Rake Lines disappear when Auto-Interactive Breakout is enabled.
1 p9 C) K' C& Y  ]& x. s1 @1255067 SIG_INTEGRITY  REPORTS          Allegro hangs on Net Parasitc Report generation: s3 X* J  T- l, `2 a# J$ E* W
1255267 ALLEGRO_EDITOR SKILL            axlDBGetPropDictEntry does not return a list of all objects
$ T7 |( T4 F. {1255383 SIP_LAYOUT     IC_IO_EDITING    cant move bumps or driver in app mode4 G7 L% U: P# n% Z: B
1255703 ALLEGRO_EDITOR SKILL            axlCNSSetPhysical and axlCNSGetPhysical return nil if a constraint set name is provided# w1 i+ b7 h' L" n  F" ?
1255759 ALLEGRO_EDITOR INTERFACES       Change the silkscreen OUTLINE from layerFunction DOCUMENT to layerFunction BOARD_OUTLINE
8 Q# {8 O# e, k/ B& g1256457 CONCEPT_HDL    CONSTRAINT_MGR   Extracting a XNet from CM crashes the tool
1 C/ O2 E2 d* j! p4 E, W6 J1256597 GRE            CORE             Allegro GRE crashes while running Plan Spatial, on a particular design
8 `' i7 R3 E3 P% D3 i3 W1256650 ASI_PI         GUI              PFE - Cannot generate model file error when using company decap library% T8 C* G# Y: w* j+ |: z2 P2 s
1256837 SIP_LAYOUT     DIE_EDITOR       Open and close of die editor takes too long
3 e7 Q* r  {/ o' n& E3 R9 s1 M1257732 CONSTRAINT_MGR OTHER            Bug - Export Analysis Results in CM makes Allegro crash# G$ W5 H5 X0 v) ~
1257755 ALLEGRO_EDITOR OTHER            Editing time in Display > Status seems to be logging wrong time; [7 T5 j. F5 x# u( Z+ P
1258029 APD            WIREBOND         The bondwire lost after import the wire information/ X/ O' F' ~& M. ]. m. B4 B4 P
1258979 APD            NC               NC Drill: There is difference of number of drills.. l; G; |7 f" J' o
1259484 SIP_LAYOUT     OTHER            SiP - calc min airgap calculate minimum airgap beta feature improvement
2 K3 X$ v! w1 g9 X' p9 v9 Y1 K4 h$ j1259677 CONCEPT_HDL    CORE             hier_write -forcereset cause component prop change.
7 c# l  R5 f3 d6 R3 w1259913 ALLEGRO_EDITOR UI_FORMS         Unable to save setting of "use secondary step models in 3D viewer"
- I, G4 @" D# m) `1261758 ALLEGRO_EDITOR EDIT_ETCH        Auto Interactive Delay tune (AiDT) is deleting clines
% w5 U4 w8 d' a/ G' R$ V( L5 Y' b1262543 ALLEGRO_EDITOR MANUFACT         merge shape results in moved void
6 L" `7 Y# m, S) S5 L2 g, Q1264767 ALLEGRO_EDITOR DRC_TIMING_CHK   XNET is choosing to resolve to a different name from 16.5 to 16.6 and is causing constraint loss
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发表于 2014-5-2 14:58 | 只看该作者
myexpma 发表于 2014-4-29 23:51: ^$ K, z6 B& _
安装时前面有几个图片出现crc错误,忽略过去了,但是后面有exe文件也有crc错误,因此中止了更新,希望版主 ...
; k& C, C% }/ R) E  M
应该是百度客户端的问题,一旦断线,重新开始的东西就不对了!遇到过好多次。文件本身应该没有问题,刚下载,数字签名没问题。
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发表于 2014-4-27 21:59 | 只看该作者
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    [LV.7]常住居民III

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    发表于 2014-4-26 17:16 | 只看该作者
    finezhang 发表于 2014-4-26 17:09
    : L2 a, o& o5 R( j好像不能下载

    3 D* u& U0 p$ b5 |1 l8 k+ t谢谢楼主的分享            好像不能下载

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    已更新百度网盘下载链,见16楼!  发表于 2014-4-28 10:50

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    2#
    发表于 2014-4-26 16:08 | 只看该作者
    谢谢楼主的分享

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    3#
    发表于 2014-4-26 17:09 | 只看该作者
    好像不能下载

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    已更新百度网盘下载链,见16楼!  发表于 2014-4-28 10:50

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    5#
    发表于 2014-4-26 17:30 | 只看该作者
    我用迅雷下载,速度比较慢啊

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    已更新百度网盘下载链,见16楼!  发表于 2014-4-28 10:54

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    6#
    发表于 2014-4-26 17:39 | 只看该作者
    本帖最后由 zhongwaiting 于 2014-4-26 17:48 编辑 * c! A+ V! i5 U" R' n! U

    3 c0 t1 c/ g! d- k( l! k/ D请哪位大虾给一个百度网盘链接!& P% z  k8 h8 Y# w. E! ~9 ]. X  l
    网络的下载速度跟不上软件的更新!

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    已更新百度网盘下载链,见16楼!  发表于 2014-4-28 10:56

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    7#
    发表于 2014-4-26 21:30 | 只看该作者
    请问怎么打补丁?需要重新安装Candence么?

    点评

    首先把spb_16.5文件夹命名为spb_16.5old(反正和spb_16.5不一样就行了)。 在cadence目录里面建立一个新的空文件夹命名为spb_16.5,并把spb_16.5old的compnts.dat拷贝到空的spb_16.5中 安装HOTFIX补丁到空的spb...  发表于 2014-4-28 11:00

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    8#
    发表于 2014-4-27 07:12 | 只看该作者
    16.5补丁出到多少啦?

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    9#
    发表于 2014-4-27 07:31 | 只看该作者
    现在Download失败了

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    已更新百度网盘下载链,见16楼!  发表于 2014-4-28 11:00

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    10#
    发表于 2014-4-27 07:39 | 只看该作者
    链接无法打开,请放置在百度网盘

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    已更新百度网盘下载链,见16楼!  发表于 2014-4-28 11:01

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    11#
    发表于 2014-4-27 21:13 | 只看该作者
    链接无效,不能下载,鉴定完毕。

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    已更新百度网盘下载链,见16楼!  发表于 2014-4-28 11:02

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    13#
    发表于 2014-4-28 08:49 | 只看该作者
    谢谢楼主分享,请问有转存baidu盘的么,这个链接下载不了

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    已更新百度网盘下载链,见16楼!  发表于 2014-4-28 11:03

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    14#
    发表于 2014-4-28 08:59 | 只看该作者
    谢谢啊,要是有其它网盘的下载地址就更好了,cadence下载有点慢8 E2 ^' ?, ^; G7 S9 Y
    不过还是要十分感谢分享
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