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本帖最后由 Csec 于 2014-4-28 11:04 编辑 ! e0 Y( c, q$ P1 d0 \8 ]7 m+ X
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http://sw.cadence.com/P/download ... e4d05&file=.exe$ O& g( V3 {8 ?
更新百度网盘下载链接！+ s7 S/ P" r4 w; M4 D1 N( p' y
http://pan.baidu.com/s/1mgwSsPy
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( K% }) N- O7 i3 zDATE: 04-25-2014 HOTFIX VERSION: 027: e- @' P7 i' X& C5 `/ Y
===================================================================================================================================1 _' i; A! T' Y/ m
CCRID PRODUCT PRODUCTLEVEL2 TITLE
/ P! e& G2 R0 ~* L! v- l% d===================================================================================================================================3 q& U3 U7 C' T. i
308701 CONSTRAINT_MGR OTHER Needs to delete user defined schedule in CM/ P# I3 a8 j2 u U7 j c
481674 allegro_EDITOR pads_IN No board file saved from PADS_in
2 R9 e& F% b5 s1 E982929 ALLEGRO_EDITOR EDIT_ETCH can't route on NC pin and other that are not pin.' N, u: Z& p3 g
1012783 FSP OTHER Need Undo Command in FSP- E! m: e6 n* x* a0 P r
1017381 ALLEGRO_EDITOR DRC_CONSTR Need Dynamic Phase to be able to measure back to the Drive Pins.# g5 k, N7 F1 t B% J2 Q/ n
1072673 PCB_LIBRARIAN GRAPHICAL_EDITOR Copy paste goes offgrid if mouse is moved# Y2 M3 O8 c; D, L
1073231 concept_HDL CORE Copy-paste of signal names goes off-grid in Windows mode.
5 w; v8 Q8 h% X& d; \( z1105371 CONCEPT_HDL INTERFACE_DESIGN Strange behavior when shorting two Net groups
: L. z. O! T- [9 M) i) y3 P1116498 CIS LINK_DATABASE_PA link database with modified part results in Capture crash
$ F) \* H) w. Q+ D1118632 ALLEGRO_EDITOR GRAPHICS Text display refresh issue while in Edit > text command& K' x; P" H3 i
1155821 SIG_INTEGRITY LIBRARY Xnet are not recalculated correctly when model is changed on the Series switch part defined as discrete with Espice mode
0 d$ j! O/ M! z1 t8 U$ U1157372 ALLEGRO_EDITOR DRC_CONSTR Dynamic phase for Diff Pairs not reporting back to Driver pin if pin escapes present
3 n5 u. u) O8 \. ]$ |2 w1 M1171951 ALLEGRO_EDITOR CREATE_SYM Jumper has a limited of count when it add to list.
$ f5 c8 H+ W- U, X" s& U! A+ z2 l1180871 CAPTURE LIBRARY_EDITOR Copied parts don't retain pin name and pin number settings- A6 ~3 j- n; T: O9 W+ t
1185575 SIP_LAYOUT DIE_STACK_EDITOR Updating symbols causes the graphics for the Assy layer to change from Bottom to Top.
) x6 W" f z& L1185772 PCB_LIBRARIAN CORE VALID_PACK_TYPE warning when cell was opened in PDV
! k" x& ]2 B8 z2 {2 q6 M5 A$ ?1192377 CAPTURE SCHEMATIC_EDITOR Pin name/number position is incorrect on schematic if it is changed for a rotated part.
+ g, a8 ~) d% J: ~4 O- d2 |# g$ k1202654 ALLEGRO_EDITOR GRAPHICS Zoom using mouse wheel shall maintain the center co-ordinates# x- h- O+ U1 Z. N. C* k* X
1208031 ALLEGRO_EDITOR INTERACTIV Snap to Pin for via during Copy command do not snap to connect point everytime% f; D. J1 D: i' a& g. f2 t+ ]
1208478 Pspice PROBE Attached project gives overflow error with marching ON.
, n6 I [2 k, W8 {; w1210015 CONCEPT_HDL CORE The value of $PN should be not turned on spin or rotate symbol
3 j8 h0 n, {0 l% |5 p+ d/ ?0 z7 D1210425 CONCEPT_HDL CORE When moving a circuit tool reports that connectivity has changed
5 U5 O+ O T3 G s# d' k1 k1215858 ALLEGRO_EDITOR SHAPE Force update does not void cline with the shape
9 ^+ Q6 A6 Z3 |4 M1215906 ALLEGRO_EDITOR SHAPE Dynamic shape fill smooth failed when copying to other layers
L4 t1 |. U1 G1 `8 |3 ~1216358 CONCEPT_HDL CORE Can we improve our export BOM function to check if user did export physical function before exporting BOM?
, s) Q: G9 V" y/ Q1217364 CONCEPT_HDL OTHER Netlist reports fail because error: GScald failed.
8 K* Y O B, ~, q* J1217529 CONCEPT_HDL CORE ADW checks do not catch single quotes in PTF values: H) o& p+ @9 I" ^& \! s. Z
1217556 F2B PACKAGERXL signal name change not sent to Allegro after packaging
7 \1 `7 K9 ]1 t" m( O1219283 ALLEGRO_EDITOR DRC_CONSTR Show constraint is inconsistent when displaying region information' d3 N: p6 j! A
1220078 F2B PACKAGERXL Export Physical crashes when ALL the part pins are added
) b* i6 f& X# g9 ~4 H j$ t' l1220393 CONSTRAINT_MGR CONCEPT_HDL HDL import physical from board file will annotate CM data back to HDL which includes cross-section thickness.% Z- V7 l- \: _, ?2 q: N# }% D
1220540 ALLEGRO_EDITOR GRAPHICS Need an option to see the pads inside the internal plane shapes
! v; e$ \0 r- E0 a2 r) K1220936 CONCEPT_HDL CORE About crash by vpadd/vpdelete command on Linux4 T# j5 A0 f7 K8 G% o' x) T( ]8 w0 z
1221059 ALLEGRO_EDITOR DRC_CONSTR Get a "Shape to Thru Via Spacing" DRC error only the first time when the shape is manually voided.0 h# H1 g1 [" I; K$ e
1221182 ADW TDA Team Design with SAMBA
, i3 o: z4 e9 v1222442 CONSTRAINT_MGR UI_FORMS Duplicate pin pairs appear in DiffPair
8 m* y* f$ }0 F' p6 R% b' C7 X2 V1223175 CONCEPT_HDL CONSTRAINT_MGR Schematic crashes when opened
: T4 t' k- B) w1 ~; F, |- k1223533 ALLEGRO_EDITOR GRAPHICS Why the through pins for STEP models are shown at an offset when viewed in 3D inside Package Symbol?
% s4 m& e4 F) w# { n1223680 CONSTRAINT_MGR ECS_APPLY Improve ECSet mapping by allowing user to address ambiguity of Parts
" e7 s* F$ w! I2 C1224156 SIG_INTEGRITY SIGWAVE Exporting spreadsheet with filter Subitems in SigWave exports all waveforms
. e7 k- u* \$ b1224417 ALLEGRO_EDITOR PLOTTING Hidden font pattern is not showing correct in 16.5 version also 16.6 version.) Z( W4 ^* ?% s! y7 g
1224704 F2B DESIGNVARI There is no lock for the variant.dat file - multiple users can open the editor1 U( n$ Z8 ?3 V0 l
1224968 ALLEGRO_EDITOR INTERACTIV Delete >(RMB click) Cut> Snap Pick to>off grid loction does not work for lines.5 F- e+ Y( ]$ k+ B- O1 u. g
1224982 CONCEPT_HDL PDF commandline publishpdf does not work when there are spaces in the path7 W5 j& _$ Q0 M' `$ M ^
1225114 CAPTURE GENERAL H-pins added after netgroup pin get color as of netgroup pin# S+ B3 L) y2 t
1225494 CAPTURE DRC Different DRC results for Entire design and selection
: Y6 {. p# N" X1226153 ALLEGRO_EDITOR INTERFACES Export STEP should include PART_NUMBER property7 }" M! P% x; O: z7 M
1226235 ALLEGRO_EDITOR EDIT_ETCH Enhancement to include Pin_delay of descrete forming Xnet5 b5 h, v3 U% t# v* N5 l* ^0 {
1226372 CAPTURE GENERATE_PART ENH: Functionality to add pin spacing in New Part From Spreadsheet) D. m' c8 `* z Y- r/ @
1226477 CONCEPT_HDL CORE DE HDL縮 `Allowed Global Shorts? function is inconvenient for Global Signal
" @ K( [5 v( ^1226813 SIP_LAYOUT LEFDEF_IF ERROR SPMHLD-120 when importing a DEF file. Request to increase the number of characters/line in a .cml file
E+ V- O) l, a$ L: q1227453 ALLEGRO_EDITOR SHAPE Addition of Fillet generate Pin to Shape Spacing DRC errors and DBDOCTOR errors* d1 S7 |' o4 R( d
1227461 ALLEGRO_EDITOR SHAPE Sliding a cline for certain net changes the thermal relief connects for pins connected to another net from 4 to 5,6,7,8
7 M9 Q9 O; C- `6 N# r) ^* i1227469 CIS DBC_CFG_WIZARD Oracle Views not visible on Step2 of CIS Configuration
/ @! k6 f7 J# G2 v' D8 A2 |. e- ?1227780 CAPTURE ANNOTATE Inconsistent behaviour when annotating heterogeneous part
% A! G; {" ^, w1227831 CONCEPT_HDL CORE Pin text and H-block name in upper case6 u) q M0 R6 C& X
1227954 CONCEPT_HDL OTHER supress check for global signals when wires are unconnected to pins2 q& r1 i- a' L, R
1228190 ALLEGRO_EDITOR OTHER Unable to close the 'usage' window during license selection
, o9 T+ I4 D0 ~7 l* {5 w$ e0 T. |& A1228899 CONSTRAINT_MGR INTERACTIV Export/Import constraints in "overwrite" mode from same design shows different results when imported second time.
B8 a& O4 }& K8 W% J$ M2 m1 B1228934 ALLEGRO_EDITOR EDIT_ETCH The "View Active Layer" option like the Board Station should be provided for dynamic layer visibility.. e8 i0 e1 X* n2 _! ~2 v
1229316 ALLEGRO_EDITOR EDIT_ETCH When routing with Hug only enabled we were able to route through other routes(sometimes Hug).
& A6 x: P R. v9 G1229545 CONSTRAINT_MGR OTHER Allegro indicate bundle scheduled nets in CM
# k; b. D1 M, J, ^8 {% P7 ^1230056 ALLEGRO_EDITOR GRAPHICS Bug: 3D View of Mechanical Symbol with the drill hole defined7 A p5 W8 j; J( f: u, a1 a0 }- W
1230432 CONCEPT_HDL CORE No Description information in BOM; Y8 B& ?* B4 N9 h# i/ D
1231148 F2B DESIGNVARI The variant.dat file is not updated with library PTF changes# Z, O7 h6 K; q+ ^, e* D8 b
1231625 F2B DESIGNSYNC VDD at command line needs to support sch2sch and test variable to write out report files! k- k8 R d2 u) h) }
1231697 CONCEPT_HDL CORE If any locked files exist force a pop-up dialog restricting certain commands1 g4 @8 p2 S1 d7 q" a8 u; d# L% i
1231767 CONCEPT_HDL OTHER Unable to find under the search options single bit vector nets
, r' V X8 A; V8 _5 X A0 S1231961 ALLEGRO_EDITOR SHAPE Shapes not updating to smooth unless we use force update and as a result false DRC's appear in board.6 \" ~/ c& c2 }$ O! {* a, j
1232100 CONCEPT_HDL skill Unable to execute the SKILL commands in viewer mode: d: o+ F4 P& R H& J5 _+ f
1232336 CONSTRAINT_MGR CONCEPT_HDL cmFeedback takes 5hrs to complete during Import Physical9 D0 m( n" V9 }5 l @# f4 X2 {
1232710 F2B DESIGNVARI Dehdl crash while moving component in variant viewer mode5 k& {; t; s$ D
1233894 F2B PACKAGERXL The page data is missing in the pst* and PCB files
7 Z* b. W+ W) @2 u1235785 CONCEPT_HDL CREFER cref_from_list custom text is not subsitituted in complex hierarchy
, r5 v+ C6 M) Y0 B: I1235928 CAPTURE SCHEMATIC_EDITOR OleObject modifications not saved
# P0 a6 Y. N9 j" Z I1236065 CAPTURE PART_EDITOR Mirrored part after being edited get pin name locations incorrect
, R% |! N1 I, t4 }8 M1236071 ALLEGRO_EDITOR SHAPE Airgap for Octagonal Pads ignores DRC Value when Thermal set
5 K, L/ ]: ~; ]9 j( K* U0 B/ Q1236072 CONCEPT_HDL CORE Page 122 cannot be saved as logical page 119 has different page mapping in connectivity data and schematic
" s$ ~4 R4 d) v/ E9 @8 N$ I1236161 CONCEPT_HDL CORE Import Design shows the current project pages9 q6 g' F/ I6 m" F# |9 Q
1236432 ALLEGRO_EDITOR PADS_IN pads_in doesnot translate via and shape in some instances., w* e& ^/ F7 U8 d
1236557 CONCEPT_HDL PDF Running Publish PDF on command line in linux doesn't output progress until completion8 z- R% _2 L. L
1236589 CONCEPT_HDL PDF Enhancement license failure error should appear in pdfpuplisher log file7 O( n, ~/ H9 E: `8 K
1236644 ALLEGRO_EDITOR EDIT_ETCH create fanout deletes shape5 T. v' l: U* t/ y4 D, g8 m
1236689 ALLEGRO_EDITOR GRAPHICS Graphics displays extraneous lines when panning or zooming8 M: H' K$ S' I8 R
1236781 F2B PACKAGERXL Export Physical produces empty files
3 S/ d4 Z) y, S# p1237331 PSPICE ENVIRONMENT pspice.exe <cir file name> - hangs when run
8 D5 b. Q+ F+ i: k7 X4 A/ a* L1237400 CIS EXPLORER Capture hangs on 2 consecutive runs of `refresh symbol from lib? command
" v- a+ J$ @+ d7 l& B1237437 CONCEPT_HDL CONSTRAINT_MGR CM Crash when saving after restore from definition
# G) K4 [2 _! H1237862 CONSTRAINT_MGR OTHER A way to remove the RAVEL markers from the Constraint Manager.5 |7 F* y8 D. p' s- H( J
1238852 CAPTURE GENERAL signal list not updated for buses9 M2 K8 ?) U$ [4 C* s9 u
1238856 FSP DE-HDL_SCHEMATIC FSP schematic generation crashes4 n% o* {% B9 W+ h D) M
1239079 ALLEGRO_EDITOR INTERACTIV The 16.6 Padstack > Replace function leaves old padstack.
; |" t4 i) u* U0 y- J1239706 CONSTRAINT_MGR ANALYSIS The reflection result on a differential signal in the CM when Measurement location is DIE0 v. ~8 Z: J3 ]1 s- F
1239763 PSPICE PROBE Cannot modify text label if right y axis is active C! Q5 X& ]4 @
1240276 ALLEGRO_EDITOR GRAPHICS Printing to PDF from SigXp is giving unreadable images: Q* K8 A3 K6 B( @
1240356 CAPTURE IMPORT/EXPORT Can縯 import SDT schematic to Capture.
, @# w# E) m% n" M9 i. d7 ]1 O9 x1240502 F2B PACKAGERXL Corrupt cfg_package does not stop PackagerXL from completing" [& r4 C+ e. O6 x
1240607 ALLEGRO_EDITOR OTHER Footprint of screw hole got shift in DXF file. y$ F1 c) q. h$ q- R. F5 n; J
1240670 ALLEGRO_EDITOR PLACEMENT Select multiple parts and Rotate makes them immovable
7 [ m! \9 ^$ m; x1240773 CAPTURE DRC DRC check reports error for duplicate NetGroup Reference in complex hierarchy U; I2 ]5 u9 x) p+ {
1240845 SIG_EXPLORER EXTRACTTOP Narrowband via models for Mirrored BB Vias not extracted in in the interconn.iml and this gives bad ringing in waveforms
" }! _: o2 _2 }6 o3 Z& k1241634 ALLEGRO_EDITOR OTHER Netshort for pad-pad connect not working0 d1 C! ^; E2 N% ?* M
1241776 CONCEPT_HDL CORE In hierarchal design not all pages are getting printed.
' P' S1 F% O& s; T% s# p1241788 CONSTRAINT_MGR CONCEPT_HDL Issues with changing focus in Constraint manager using keys on keyboard
5 j x: W5 Z( i. w1 F6 `# P1242683 ALLEGRO_EDITOR INTERACTIV Color View Save replaces file without warning
$ N1 f! X0 O8 A/ d* @. W" g2 j: y1242818 ALLEGRO_EDITOR PLACEMENT Placement edit mirror option places component on wrong side
/ j' d/ Q3 r% S- b) ]: N1242847 ALLEGRO_EDITOR GRAPHICS Need an option to suppress Via Holes in 3D Viewer3 q0 R `# t" j( ^% l3 r& d
1242923 ADW COMPONENT_BROWSE UCB reports Missing From DB only after selecting the Row in the search results
# f/ D# K& s9 ^& e, a& Z1243609 CONCEPT_HDL CORE autoprop for occurrence properties& ]" |5 y8 e& Q" u+ t8 @
1243682 F2B DESIGNVARI after undocking variant icon cannot be redocked back to GUI
! `1 g" s7 U2 y8 V1243686 ALLEGRO_EDITOR GRAPHICS Invoking Edit->Text, the infinite cursor disappears until edit mode is changed.3 P T/ k' U2 l: [, Z9 v
1243715 CAPTURE PART_EDITOR Pin name positioning get changed after rotating or mirroring
0 U, K6 f$ S: q& p- a7 h1244945 CONCEPT_HDL PDF PDF Publisher does not include image when file is not located in the root folder+ C. C; y$ \( U( X# U
1245568 CONCEPT_HDL CORE Dual unselect needed for wires attached to other net/source and property is not deselected when component is6 z7 i4 S# O# i! d6 z1 o5 i
1245819 F2B PACKAGERXL wrong injected properties information passed during packaging of the design
4 `- x, |) |3 h, U2 E0 [6 r q1245916 SCM CONCEPT_IMPORT Where does the folder location reside for DEHDL imported blocks?1 Q# n; [& e& c
1246347 CONSTRAINT_MGR CONCEPT_HDL DEHDL crash if environment variable path has trailing backslash character
- n; L7 X; S+ O( j) b- h2 j) \1246896 ALLEGRO_EDITOR DFA DFA_UPDATE on Linux reports err message if the path has Upper case characters: i; s% u( y- N# m) k. }, k
1247019 SIP_LAYOUT DIE_STACK_EDITOR SiP Layout - refresh/update symbols is mirroring the assembly drawing data on DIE that is placed ChipDown) P, ^+ b7 x' Y; ^
1247037 CAPTURE LIBRARY_EDITOR Copy & Paste of library parts resets pin name and number' U1 N2 r& N' K8 \3 S8 K3 c
1247089 CONCEPT_HDL CORE Group Align or Distribute > Left/Center/Right crashes DEHDL
9 X" V; \& E8 d7 J/ o3 k1247163 CONCEPT_HDL PDF Physical Net Names in PDF not maintained& N: r1 ]6 a0 N0 p& l2 M0 t$ }* _
1247462 CONCEPT_HDL CORE Text issue while moving with bounding box' | f: }8 O: Z, }% V
1247464 ALLEGRO_EDITOR UI_FORMS When using the define B/B via UI the end layer dropdown arrow is partially covered
" ]5 N+ U: u5 a; z( g1249063 CONCEPT_HDL CONSTRAINT_MGR CM and SigXP doesn縯 respect PACK_IGNORE at components
1 E/ `; P# _4 J' Q# S7 K1250270 CONCEPT_HDL CORE Part Manager Update places wrong parts
$ Y: Y6 `- @# x, s5 x% {6 I7 G1251206 ALLEGRO_EDITOR ARTWORK Aperture command cannot create appropriate aperture automatically from design.
+ O! u W' z+ Z) X* e7 ~+ J n6 _1251356 ALLEGRO_EDITOR INTERFACES Some STEP models are missing in 3D view of footprint, although all components have STEP model mapped in footprint, R; o+ y d8 t' y/ R, l- V
1251845 ALLEGRO_EDITOR EXTRACT Crosshatch arcs do not extract correctly4 ]6 ?3 ]/ u% h8 V7 j. ]
1252143 APD OTHER When using the beta "shape to cline" command the tool is removing the shape instead of converting it.+ `6 M D9 {; E$ _! I( H
1252737 SIP_LAYOUT OTHER SiP Layout - Option to create shapes from Pins for WLP wafer level packaging technologies
1 r6 J% [- [1 F) C8 Q$ r1253424 SCM SCHGEN Export Schematics Crashes System Architect
6 z, S! l' r9 X) j& z1253508 ALLEGRO_EDITOR INTERFACES Bug - Export IPC2581 exports Crosshatch shapes as filled! w' O& W2 B! T1 h
1253554 SIP_LAYOUT OTHER SiP Layout - Add Netlist Spreadsheet export to SiP layout to help with connectivity auditing' v, d3 D' o2 l
1254578 SPIF OTHER Specctra crash with Error -1073741819 for Auto router
+ U _2 z+ a& n0 e1254637 ALLEGRO_EDITOR DRC_TIMING_CHK adding nets to a net group causes constraint assignment error7 ~% ]* r- |6 M5 V
1254676 GRE IFP_INTERACTIVE Rake Lines disappear when Auto-Interactive Breakout is enabled.
- Y& @/ }* t2 w" b# w5 e& y1255067 SIG_INTEGRITY REPORTS Allegro hangs on Net Parasitc Report generation: h1 _; Z: O- Z2 l8 Y& L( d
1255267 ALLEGRO_EDITOR SKILL axlDBGetPropDictEntry does not return a list of all objects4 E9 X+ |3 f# N( W- b" M5 w
1255383 SIP_LAYOUT IC_IO_EDITING cant move bumps or driver in app mode+ y n) ?! v6 D* r4 g, E$ `, i
1255703 ALLEGRO_EDITOR SKILL axlCNSSetPhysical and axlCNSGetPhysical return nil if a constraint set name is provided
. ?9 s8 V t2 m/ r* m O5 m. _1255759 ALLEGRO_EDITOR INTERFACES Change the silkscreen OUTLINE from layerFunction DOCUMENT to layerFunction BOARD_OUTLINE' s+ w. c3 e: D& e) I
1256457 CONCEPT_HDL CONSTRAINT_MGR Extracting a XNet from CM crashes the tool/ B, N" s% y, F4 [; i" j
1256597 GRE CORE Allegro GRE crashes while running Plan Spatial, on a particular design% d o" o' u5 T
1256650 ASI_PI GUI PFE - Cannot generate model file error when using company decap library7 s& g' Y6 w& [+ R$ J, b0 O
1256837 SIP_LAYOUT DIE_EDITOR Open and close of die editor takes too long" @" \; K4 x+ J1 G% U
1257732 CONSTRAINT_MGR OTHER Bug - Export Analysis Results in CM makes Allegro crash$ |; U0 |" B, H# M
1257755 ALLEGRO_EDITOR OTHER Editing time in Display > Status seems to be logging wrong time
/ v# R$ g8 j' _( L9 t1258029 APD WIREBOND The bondwire lost after import the wire information
a4 p# r& n1 C2 A: C1258979 APD NC NC Drill: There is difference of number of drills.
- v/ c9 p& L* H& r3 j. T. X1259484 SIP_LAYOUT OTHER SiP - calc min airgap calculate minimum airgap beta feature improvement
0 V" x. {6 D# [, [+ X4 @! |1259677 CONCEPT_HDL CORE hier_write -forcereset cause component prop change.
, Z# X. l/ j6 n0 h5 Q; ^8 \7 x1259913 ALLEGRO_EDITOR UI_FORMS Unable to save setting of "use secondary step models in 3D viewer": i% K! G% o" k& @: A7 U5 U
1261758 ALLEGRO_EDITOR EDIT_ETCH Auto Interactive Delay tune (AiDT) is deleting clines! W2 a5 @8 W* k3 d# j
1262543 ALLEGRO_EDITOR MANUFACT merge shape results in moved void
' y5 x9 h8 u- [, G* Z# \1264767 ALLEGRO_EDITOR DRC_TIMING_CHK XNET is choosing to resolve to a different name from 16.5 to 16.6 and is causing constraint loss' t" p- c1 [5 f) k9 E/ Z( J# ?
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发表于 2014-4-26 15:15
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发表于 2014-4-27 21:59
