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本帖最后由 Csec 于 2014-4-28 11:04 编辑 8 P. L7 r6 S6 z7 i
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http://sw.cadence.com/P/download ... e4d05&file=.exe
' q# T4 t, H$ d. o v更新百度网盘下载链接！9 }/ E/ {4 y5 H1 v0 C# Q
http://pan.baidu.com/s/1mgwSsPy) K5 v1 i: z5 k+ M6 {$ u
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DATE: 04-25-2014 HOTFIX VERSION: 027 t0 b0 r- D( f+ ^% p1 v
===================================================================================================================================
3 {& E4 {% R4 Y7 iCCRID PRODUCT PRODUCTLEVEL2 TITLE+ _3 R- x$ V: V- q; h. x
===================================================================================================================================9 y/ N& w( i6 T5 Q0 n p' l
308701 CONSTRAINT_MGR OTHER Needs to delete user defined schedule in CM
+ ~$ ^: Q& p w! `1 k; A- E: o481674 allegro_EDITOR pads_IN No board file saved from PADS_in0 F% k6 ^# K8 S2 Y2 P1 ]+ D4 ?
982929 ALLEGRO_EDITOR EDIT_ETCH can't route on NC pin and other that are not pin.
# ~! o8 [. B$ Q; ~9 F8 P1012783 FSP OTHER Need Undo Command in FSP# ?7 X3 j* @# D. \* J5 I1 i7 I
1017381 ALLEGRO_EDITOR DRC_CONSTR Need Dynamic Phase to be able to measure back to the Drive Pins.
: c" F8 g( }1 C) z H7 \0 E1072673 PCB_LIBRARIAN GRAPHICAL_EDITOR Copy paste goes offgrid if mouse is moved
, X" }. X* k" ]: Z1073231 concept_HDL CORE Copy-paste of signal names goes off-grid in Windows mode.
* q# @3 y' [! \: ?2 Q- e1105371 CONCEPT_HDL INTERFACE_DESIGN Strange behavior when shorting two Net groups
3 W2 g: Q- j ], m1116498 CIS LINK_DATABASE_PA link database with modified part results in Capture crash
2 M1 Q: a' m) B3 s& G8 y0 u9 @1118632 ALLEGRO_EDITOR GRAPHICS Text display refresh issue while in Edit > text command
& r- f& W9 Y) O! |7 W7 M v! [: K1 P1155821 SIG_INTEGRITY LIBRARY Xnet are not recalculated correctly when model is changed on the Series switch part defined as discrete with Espice mode6 m5 I, E7 V9 v& ~9 \' k
1157372 ALLEGRO_EDITOR DRC_CONSTR Dynamic phase for Diff Pairs not reporting back to Driver pin if pin escapes present- z8 S+ E6 W6 {3 h6 P
1171951 ALLEGRO_EDITOR CREATE_SYM Jumper has a limited of count when it add to list.. J: a" T! l) b) \! x
1180871 CAPTURE LIBRARY_EDITOR Copied parts don't retain pin name and pin number settings
}' J) h9 }( ]! f) L0 _- w1185575 SIP_LAYOUT DIE_STACK_EDITOR Updating symbols causes the graphics for the Assy layer to change from Bottom to Top., I" m( J) T: m2 l0 l
1185772 PCB_LIBRARIAN CORE VALID_PACK_TYPE warning when cell was opened in PDV
8 x& K+ `( `6 h% \1192377 CAPTURE SCHEMATIC_EDITOR Pin name/number position is incorrect on schematic if it is changed for a rotated part.% x0 E( O F0 p Y r% S) r
1202654 ALLEGRO_EDITOR GRAPHICS Zoom using mouse wheel shall maintain the center co-ordinates. `6 t6 z% `$ }4 j
1208031 ALLEGRO_EDITOR INTERACTIV Snap to Pin for via during Copy command do not snap to connect point everytime3 I! S2 } @: x9 Q7 O6 _
1208478 Pspice PROBE Attached project gives overflow error with marching ON.
* q0 ]7 u" X7 u0 V8 Z1210015 CONCEPT_HDL CORE The value of $PN should be not turned on spin or rotate symbol
+ s4 [% ~! ~' |& L5 p1210425 CONCEPT_HDL CORE When moving a circuit tool reports that connectivity has changed
% |6 E7 @ m2 l1215858 ALLEGRO_EDITOR SHAPE Force update does not void cline with the shape
9 V7 b b) V1 e6 G& d1 {1215906 ALLEGRO_EDITOR SHAPE Dynamic shape fill smooth failed when copying to other layers4 J3 L3 d3 x3 [' g# k% @) B
1216358 CONCEPT_HDL CORE Can we improve our export BOM function to check if user did export physical function before exporting BOM?& b- N- g W3 ~, a% w- Y/ f' }
1217364 CONCEPT_HDL OTHER Netlist reports fail because error: GScald failed.
/ m B7 }! ?4 Q# j i6 t1217529 CONCEPT_HDL CORE ADW checks do not catch single quotes in PTF values* _: r2 |/ ^& o: Q
1217556 F2B PACKAGERXL signal name change not sent to Allegro after packaging n8 @3 z d0 r9 i3 i
1219283 ALLEGRO_EDITOR DRC_CONSTR Show constraint is inconsistent when displaying region information
4 b8 ]- F0 s/ V' d; u6 n1220078 F2B PACKAGERXL Export Physical crashes when ALL the part pins are added" D8 Y: U c* G' ~4 B2 |% {
1220393 CONSTRAINT_MGR CONCEPT_HDL HDL import physical from board file will annotate CM data back to HDL which includes cross-section thickness.- N) u* r6 _5 k7 O3 j/ v8 l3 B
1220540 ALLEGRO_EDITOR GRAPHICS Need an option to see the pads inside the internal plane shapes
/ E( `5 a- U4 E1 z( b: S% f1220936 CONCEPT_HDL CORE About crash by vpadd/vpdelete command on Linux
* s8 _% r# ~# j5 r( @3 @1221059 ALLEGRO_EDITOR DRC_CONSTR Get a "Shape to Thru Via Spacing" DRC error only the first time when the shape is manually voided.
3 M( ~1 e) w/ ] k0 ~( C- o# C1221182 ADW TDA Team Design with SAMBA
" m9 J6 x9 C, F7 {1222442 CONSTRAINT_MGR UI_FORMS Duplicate pin pairs appear in DiffPair
2 v/ i. s$ j" p9 g1223175 CONCEPT_HDL CONSTRAINT_MGR Schematic crashes when opened
* E' ?0 u0 s* M1223533 ALLEGRO_EDITOR GRAPHICS Why the through pins for STEP models are shown at an offset when viewed in 3D inside Package Symbol?
* T5 b9 j& ]: l+ Y1223680 CONSTRAINT_MGR ECS_APPLY Improve ECSet mapping by allowing user to address ambiguity of Parts
1 ]9 @, `2 C0 G1224156 SIG_INTEGRITY SIGWAVE Exporting spreadsheet with filter Subitems in SigWave exports all waveforms
: |: t& p0 \) ~) d; E7 g1224417 ALLEGRO_EDITOR PLOTTING Hidden font pattern is not showing correct in 16.5 version also 16.6 version.
8 L' [! S- V4 ^' A* s1224704 F2B DESIGNVARI There is no lock for the variant.dat file - multiple users can open the editor
, @9 x3 w0 w0 ]3 V! @1224968 ALLEGRO_EDITOR INTERACTIV Delete >(RMB click) Cut> Snap Pick to>off grid loction does not work for lines.# s$ N: D1 l' ]" X" d
1224982 CONCEPT_HDL PDF commandline publishpdf does not work when there are spaces in the path
% O' J" V0 r5 r3 L" L8 p* ?2 J: J1225114 CAPTURE GENERAL H-pins added after netgroup pin get color as of netgroup pin
; a( ]$ o& N6 w+ p4 H& c1225494 CAPTURE DRC Different DRC results for Entire design and selection8 I2 ]% A( o4 s% f4 `+ r3 E0 O, S
1226153 ALLEGRO_EDITOR INTERFACES Export STEP should include PART_NUMBER property
- ?& ?$ h6 s) t$ q+ g5 ]; ^: G) n1226235 ALLEGRO_EDITOR EDIT_ETCH Enhancement to include Pin_delay of descrete forming Xnet3 ?/ i7 |7 V# J
1226372 CAPTURE GENERATE_PART ENH: Functionality to add pin spacing in New Part From Spreadsheet% C# }# w( w& W5 M6 R9 G9 _
1226477 CONCEPT_HDL CORE DE HDL縮 `Allowed Global Shorts? function is inconvenient for Global Signal
( V9 g2 j& L+ ~/ F1226813 SIP_LAYOUT LEFDEF_IF ERROR SPMHLD-120 when importing a DEF file. Request to increase the number of characters/line in a .cml file% n' D( P! F% F4 N/ s- \
1227453 ALLEGRO_EDITOR SHAPE Addition of Fillet generate Pin to Shape Spacing DRC errors and DBDOCTOR errors
+ l1 y* L: B1 S4 _1227461 ALLEGRO_EDITOR SHAPE Sliding a cline for certain net changes the thermal relief connects for pins connected to another net from 4 to 5,6,7,82 R! b7 J: a* F: G3 `/ W
1227469 CIS DBC_CFG_WIZARD Oracle Views not visible on Step2 of CIS Configuration1 f* |" [ y7 z6 B
1227780 CAPTURE ANNOTATE Inconsistent behaviour when annotating heterogeneous part
/ d- |, f2 H6 C) c z" B" ^, b; N1227831 CONCEPT_HDL CORE Pin text and H-block name in upper case5 Z9 g& m0 V! n8 w K2 G4 t; J# p9 m9 [
1227954 CONCEPT_HDL OTHER supress check for global signals when wires are unconnected to pins% [$ }0 V6 }8 K8 n0 W8 F
1228190 ALLEGRO_EDITOR OTHER Unable to close the 'usage' window during license selection5 v( i6 _# j4 ?7 g4 w1 `. X3 m
1228899 CONSTRAINT_MGR INTERACTIV Export/Import constraints in "overwrite" mode from same design shows different results when imported second time.
0 b# E* x- L& Z9 @# u1228934 ALLEGRO_EDITOR EDIT_ETCH The "View Active Layer" option like the Board Station should be provided for dynamic layer visibility.
: U# z8 b. g3 O3 g( g1229316 ALLEGRO_EDITOR EDIT_ETCH When routing with Hug only enabled we were able to route through other routes(sometimes Hug).
& y) G$ [( `5 m2 X0 j/ U+ v: \ N1229545 CONSTRAINT_MGR OTHER Allegro indicate bundle scheduled nets in CM/ u2 n9 w% p, l7 |9 O
1230056 ALLEGRO_EDITOR GRAPHICS Bug: 3D View of Mechanical Symbol with the drill hole defined
0 v2 h; |! @6 W" S1230432 CONCEPT_HDL CORE No Description information in BOM2 ~" D* Q- Z2 L+ q$ e
1231148 F2B DESIGNVARI The variant.dat file is not updated with library PTF changes
0 I. W5 N( h6 u0 K1231625 F2B DESIGNSYNC VDD at command line needs to support sch2sch and test variable to write out report files( p1 c7 Q+ u" |) H
1231697 CONCEPT_HDL CORE If any locked files exist force a pop-up dialog restricting certain commands
8 @/ k2 a7 t. r0 b: u, h) ?" e1231767 CONCEPT_HDL OTHER Unable to find under the search options single bit vector nets: c- B' |( p* ]$ f. @9 ^$ o/ _
1231961 ALLEGRO_EDITOR SHAPE Shapes not updating to smooth unless we use force update and as a result false DRC's appear in board.
/ Y. D1 C. @6 C2 X: _6 |' ?1232100 CONCEPT_HDL skill Unable to execute the SKILL commands in viewer mode) h) P& D8 C- B2 w4 J2 x3 K
1232336 CONSTRAINT_MGR CONCEPT_HDL cmFeedback takes 5hrs to complete during Import Physical
8 P: t% T- F) w6 h% y9 t' }& W1232710 F2B DESIGNVARI Dehdl crash while moving component in variant viewer mode
3 \' ]" ^2 F# x0 H1233894 F2B PACKAGERXL The page data is missing in the pst* and PCB files- f/ y2 t9 H! T
1235785 CONCEPT_HDL CREFER cref_from_list custom text is not subsitituted in complex hierarchy! [) i9 j! p x# G
1235928 CAPTURE SCHEMATIC_EDITOR OleObject modifications not saved
% o6 L3 ~! x7 [( S% L" r1236065 CAPTURE PART_EDITOR Mirrored part after being edited get pin name locations incorrect# i: M/ F4 O. }# N$ Z( F
1236071 ALLEGRO_EDITOR SHAPE Airgap for Octagonal Pads ignores DRC Value when Thermal set
6 Y7 M. z6 P' }, s1 d3 Y1236072 CONCEPT_HDL CORE Page 122 cannot be saved as logical page 119 has different page mapping in connectivity data and schematic+ h) A1 X9 T' }. m) B6 q) z/ d) l
1236161 CONCEPT_HDL CORE Import Design shows the current project pages
, V0 [$ }7 J/ }' i' j. R% e1236432 ALLEGRO_EDITOR PADS_IN pads_in doesnot translate via and shape in some instances.
5 P" w. T. W/ ]* G& T8 s! K1236557 CONCEPT_HDL PDF Running Publish PDF on command line in linux doesn't output progress until completion
2 m7 I1 g' f) ~/ a$ T- m1236589 CONCEPT_HDL PDF Enhancement license failure error should appear in pdfpuplisher log file
) b8 Z0 Q+ E1 i2 j" N1 v2 |) C1236644 ALLEGRO_EDITOR EDIT_ETCH create fanout deletes shape
1 C# }1 P; p6 F2 S3 b: T1236689 ALLEGRO_EDITOR GRAPHICS Graphics displays extraneous lines when panning or zooming4 B! m& K$ K, t' m' ~/ \8 M
1236781 F2B PACKAGERXL Export Physical produces empty files! C: n: A3 B/ v% }. p
1237331 PSPICE ENVIRONMENT pspice.exe <cir file name> - hangs when run- |' p6 |* U2 y
1237400 CIS EXPLORER Capture hangs on 2 consecutive runs of `refresh symbol from lib? command( E/ u) @* s3 k) X7 \4 ^7 Y
1237437 CONCEPT_HDL CONSTRAINT_MGR CM Crash when saving after restore from definition
9 b* `2 \: U8 u# D1 d' w: ]$ c& x1237862 CONSTRAINT_MGR OTHER A way to remove the RAVEL markers from the Constraint Manager.. A! t- S: e1 J+ A
1238852 CAPTURE GENERAL signal list not updated for buses
* @( x; Y7 D1 ^* l( o# S1238856 FSP DE-HDL_SCHEMATIC FSP schematic generation crashes& M6 R" g7 X5 o: T# M# y( ~
1239079 ALLEGRO_EDITOR INTERACTIV The 16.6 Padstack > Replace function leaves old padstack.( S/ P6 |2 b' x+ t4 n$ E4 F# ?
1239706 CONSTRAINT_MGR ANALYSIS The reflection result on a differential signal in the CM when Measurement location is DIE
6 ^, ]: v, w( n1239763 PSPICE PROBE Cannot modify text label if right y axis is active3 D! I5 ^0 }+ [+ |4 L6 b; b3 e
1240276 ALLEGRO_EDITOR GRAPHICS Printing to PDF from SigXp is giving unreadable images3 i. x, s8 k0 A' U6 K
1240356 CAPTURE IMPORT/EXPORT Can縯 import SDT schematic to Capture.
. L1 P# M7 [$ F* O: ^* A H8 d1240502 F2B PACKAGERXL Corrupt cfg_package does not stop PackagerXL from completing
3 E$ l0 q/ C9 J' |+ ]1240607 ALLEGRO_EDITOR OTHER Footprint of screw hole got shift in DXF file1 ~$ g: Q( D# U3 `+ x+ Z( p5 U
1240670 ALLEGRO_EDITOR PLACEMENT Select multiple parts and Rotate makes them immovable
w- G5 i! j" R; x1240773 CAPTURE DRC DRC check reports error for duplicate NetGroup Reference in complex hierarchy# R# U: ]; W& ]8 H! _" g+ C" A
1240845 SIG_EXPLORER EXTRACTTOP Narrowband via models for Mirrored BB Vias not extracted in in the interconn.iml and this gives bad ringing in waveforms
: Q& }5 ~* y' n1241634 ALLEGRO_EDITOR OTHER Netshort for pad-pad connect not working
- D+ B. | o7 ^! e1241776 CONCEPT_HDL CORE In hierarchal design not all pages are getting printed.2 {! S7 M' H, _, F5 v0 A8 o
1241788 CONSTRAINT_MGR CONCEPT_HDL Issues with changing focus in Constraint manager using keys on keyboard
! \! L7 ~ J: p+ N' {8 y) B7 o0 w1242683 ALLEGRO_EDITOR INTERACTIV Color View Save replaces file without warning2 ~' v' C9 k8 q5 W
1242818 ALLEGRO_EDITOR PLACEMENT Placement edit mirror option places component on wrong side- e. b: r4 K, Q# i1 y3 c
1242847 ALLEGRO_EDITOR GRAPHICS Need an option to suppress Via Holes in 3D Viewer
9 u: Z; u4 z2 X% x" f# z) Z$ v% T+ M1242923 ADW COMPONENT_BROWSE UCB reports Missing From DB only after selecting the Row in the search results
" u9 k1 p1 S0 l" Y; @9 e7 Z1243609 CONCEPT_HDL CORE autoprop for occurrence properties
9 @# ~6 ^! G) G1 @1243682 F2B DESIGNVARI after undocking variant icon cannot be redocked back to GUI! o+ @9 t; s6 c" ~ U5 C# P
1243686 ALLEGRO_EDITOR GRAPHICS Invoking Edit->Text, the infinite cursor disappears until edit mode is changed.
0 s* Z9 W1 I$ |1243715 CAPTURE PART_EDITOR Pin name positioning get changed after rotating or mirroring1 T& T. C) x2 u/ a0 V
1244945 CONCEPT_HDL PDF PDF Publisher does not include image when file is not located in the root folder+ y5 r4 i8 @3 D- k3 d0 f
1245568 CONCEPT_HDL CORE Dual unselect needed for wires attached to other net/source and property is not deselected when component is
/ }8 ~" N6 l$ K' v; [1245819 F2B PACKAGERXL wrong injected properties information passed during packaging of the design
' E/ w( G5 b6 ]. S, u& N; B$ b1245916 SCM CONCEPT_IMPORT Where does the folder location reside for DEHDL imported blocks?
, o3 [- G1 } Q, v* |8 y+ a3 G6 l! {1246347 CONSTRAINT_MGR CONCEPT_HDL DEHDL crash if environment variable path has trailing backslash character
& K: c- e. O9 l1 B3 b; R! l1246896 ALLEGRO_EDITOR DFA DFA_UPDATE on Linux reports err message if the path has Upper case characters2 [5 Z1 m4 C) C3 c K& m) J7 u1 G
1247019 SIP_LAYOUT DIE_STACK_EDITOR SiP Layout - refresh/update symbols is mirroring the assembly drawing data on DIE that is placed ChipDown
$ |9 a. ~5 o0 a! P: h% v1247037 CAPTURE LIBRARY_EDITOR Copy & Paste of library parts resets pin name and number- I6 |7 S+ P, H& o
1247089 CONCEPT_HDL CORE Group Align or Distribute > Left/Center/Right crashes DEHDL% ~& X8 {5 M5 H; d8 D
1247163 CONCEPT_HDL PDF Physical Net Names in PDF not maintained( |# B1 K9 `8 ?5 S
1247462 CONCEPT_HDL CORE Text issue while moving with bounding box
. _1 S! u2 u' I. Q; W% I1247464 ALLEGRO_EDITOR UI_FORMS When using the define B/B via UI the end layer dropdown arrow is partially covered5 {' y" I0 t' Q$ \
1249063 CONCEPT_HDL CONSTRAINT_MGR CM and SigXP doesn縯 respect PACK_IGNORE at components7 b! F* c4 ]4 ]! d) |' _& D7 b
1250270 CONCEPT_HDL CORE Part Manager Update places wrong parts; |, M- H# w1 s, L
1251206 ALLEGRO_EDITOR ARTWORK Aperture command cannot create appropriate aperture automatically from design.) o8 x1 E. O0 S) |. ^- {
1251356 ALLEGRO_EDITOR INTERFACES Some STEP models are missing in 3D view of footprint, although all components have STEP model mapped in footprint
. t6 k. `: S+ k) A, b }* U1251845 ALLEGRO_EDITOR EXTRACT Crosshatch arcs do not extract correctly
) J4 p6 B+ U! D r, J; [! [* L& v1252143 APD OTHER When using the beta "shape to cline" command the tool is removing the shape instead of converting it.; a* [2 _& t# ?
1252737 SIP_LAYOUT OTHER SiP Layout - Option to create shapes from Pins for WLP wafer level packaging technologies
% @# a9 `. f+ O5 u, \3 |- Z# ?1253424 SCM SCHGEN Export Schematics Crashes System Architect
1 t& G* g3 a& Y2 S% T1253508 ALLEGRO_EDITOR INTERFACES Bug - Export IPC2581 exports Crosshatch shapes as filled
6 Y2 F5 @# a R- U1253554 SIP_LAYOUT OTHER SiP Layout - Add Netlist Spreadsheet export to SiP layout to help with connectivity auditing
/ r% F7 ^- v% v. z* ]1 s$ M: g1254578 SPIF OTHER Specctra crash with Error -1073741819 for Auto router
2 B9 V% e4 V; q6 ~5 [1 ]1254637 ALLEGRO_EDITOR DRC_TIMING_CHK adding nets to a net group causes constraint assignment error# T/ ]3 r& z9 T7 m& i: n. r
1254676 GRE IFP_INTERACTIVE Rake Lines disappear when Auto-Interactive Breakout is enabled." w- E+ u3 x5 S5 A, t8 M4 H
1255067 SIG_INTEGRITY REPORTS Allegro hangs on Net Parasitc Report generation
* U3 W7 O& {* r% v1255267 ALLEGRO_EDITOR SKILL axlDBGetPropDictEntry does not return a list of all objects) B( D8 d& O4 Y; i" a5 e
1255383 SIP_LAYOUT IC_IO_EDITING cant move bumps or driver in app mode6 X' P p3 |0 j; S- q" @9 m
1255703 ALLEGRO_EDITOR SKILL axlCNSSetPhysical and axlCNSGetPhysical return nil if a constraint set name is provided
2 |& A3 A* R$ I9 Z/ T' k1255759 ALLEGRO_EDITOR INTERFACES Change the silkscreen OUTLINE from layerFunction DOCUMENT to layerFunction BOARD_OUTLINE
5 V; N2 S0 @* H* E1256457 CONCEPT_HDL CONSTRAINT_MGR Extracting a XNet from CM crashes the tool3 |1 }- `2 _3 S+ N6 X
1256597 GRE CORE Allegro GRE crashes while running Plan Spatial, on a particular design) U2 C: J" p& P$ w7 x4 G2 {
1256650 ASI_PI GUI PFE - Cannot generate model file error when using company decap library7 ^" ^0 i7 h! A; K: ~
1256837 SIP_LAYOUT DIE_EDITOR Open and close of die editor takes too long
: ^$ { l5 _& ^6 n* X1257732 CONSTRAINT_MGR OTHER Bug - Export Analysis Results in CM makes Allegro crash
1 `' k! q" |' \ x. h& r; y( T1257755 ALLEGRO_EDITOR OTHER Editing time in Display > Status seems to be logging wrong time
. }& X5 u7 {+ `' s1258029 APD WIREBOND The bondwire lost after import the wire information
* }1 l( ]9 o- B5 S! j% k6 }! i1258979 APD NC NC Drill: There is difference of number of drills.
' S; a7 V4 R* }7 ` T+ L& `; m- L1259484 SIP_LAYOUT OTHER SiP - calc min airgap calculate minimum airgap beta feature improvement% Q) B; i) m q( S& U
1259677 CONCEPT_HDL CORE hier_write -forcereset cause component prop change.
* y/ V2 K- C* X& l2 M1259913 ALLEGRO_EDITOR UI_FORMS Unable to save setting of "use secondary step models in 3D viewer"0 n" C% k4 ?6 C6 s( R
1261758 ALLEGRO_EDITOR EDIT_ETCH Auto Interactive Delay tune (AiDT) is deleting clines
1 J2 L" \0 H( r) f, m6 |8 z8 p8 `1262543 ALLEGRO_EDITOR MANUFACT merge shape results in moved void
6 _ g( V/ c( e {0 ?1264767 ALLEGRO_EDITOR DRC_TIMING_CHK XNET is choosing to resolve to a different name from 16.5 to 16.6 and is causing constraint loss
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发表于 2014-4-26 15:15
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发表于 2014-4-27 21:59
