|
|
本帖最后由 lvsy 于 2014-4-16 10:05 编辑
* K# K( D) T/ g( d% I2 [2 o' d
# W; I$ |, \: Y: I( }可以！对于Altera的FPGA，JTAG接口不是VCCIO供电的，它有专用的电源VCCPD，VCCPD的电压不能小于VCCIO。
2 V) L2 Z! i1 e4 P( T# P
+ ?" `# D6 S/ _% V如果是xilinx的FPGA，7系列也是可以的。设置CFGBVS管脚，接GND。9 @' V9 c j) l: g2 [( \: p8 H1 w
; U; p6 m, k) |( \+ O; O
The 7 series devices support configuration interfaces with 3.3V, 2.5V, 1.8V, or 1.5V I/O. The
3 D( j j U4 G1 t" d; u6 W( W0 }configuration interfaces include the JTAG pins in bank 0, the dedicated configuration pins7 C- O( s9 v' Z/ {2 h! i
in bank 0, and the pins related to specific configuration modes in bank 14 and bank 15. To4 g, y: r7 ]: r" Y* o
support the appropriate configuration interface voltage on bank 0, bank 14, and bank 15,& O8 v/ d" Z3 Z, e8 X3 _, E7 p
the following is required:( ]5 y7 e* D' b% R) U; ?) b, h4 h
• The configuration banks voltage select pin (CFGBVS) must be set to a High (VCCO_0)
; d: u% Y3 N) K& k. ]6 sor Low (GND) in order to set the configuration and JTAG I/O in banks 0, 14, and 15
3 T0 P* E+ a6 S9 {, y; O( xfor 3.3V/2.5V or 1.8V/1.5 operation, respectively. When CFGBVS is set to Low for
4 b' C) h3 t) z7 h5 j* u1.8V/1.5V I/O operation, the VCCO_0 supply and I/O signals to bank 0 must be 1.8V% ], h4 f0 G6 ?" i/ O
(or lower) to avoid device damage. If CFGBVS is Low, then any I/O pins used for
' r4 g' x1 g4 Q0 R4 r+ d- zconfiguration in banks 14 and 15 must also be powered and operated at 1.8V or 1.5V.
, v" R1 h5 l/ V3 J0 a1 v |
|
/1 
发表于 2014-4-15 18:32
收藏
淘帖
支持！
反对！
楼主