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本帖最后由 lvsy 于 2014-4-16 10:05 编辑
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可以!对于Altera的FPGA,JTAG接口不是VCCIO供电的,它有专用的电源VCCPD,VCCPD的电压不能小于VCCIO。
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e1 x; ?( b8 X( F如果是xilinx的FPGA,7系列也是可以的。设置CFGBVS管脚,接GND。
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The 7 series devices support configuration interfaces with 3.3V, 2.5V, 1.8V, or 1.5V I/O. The' A ?" @3 X( h2 Y. n
configuration interfaces include the JTAG pins in bank 0, the dedicated configuration pins% c7 E+ ?7 \3 l( _/ a4 _5 h7 u
in bank 0, and the pins related to specific configuration modes in bank 14 and bank 15. To2 D5 M6 E3 a. \
support the appropriate configuration interface voltage on bank 0, bank 14, and bank 15,8 y" U/ _0 P3 F/ o5 B: |
the following is required:% k) O8 U$ d# {3 H+ ?6 V9 \
• The configuration banks voltage select pin (CFGBVS) must be set to a High (VCCO_0)( x: T, t5 B& I; E
or Low (GND) in order to set the configuration and JTAG I/O in banks 0, 14, and 15: S1 z" f/ k6 K, S+ n5 m. H
for 3.3V/2.5V or 1.8V/1.5 operation, respectively. When CFGBVS is set to Low for( v% F. X- P0 b `" w2 t8 I& Z& s
1.8V/1.5V I/O operation, the VCCO_0 supply and I/O signals to bank 0 must be 1.8V
/ q6 Y6 _5 `# t6 ?* {(or lower) to avoid device damage. If CFGBVS is Low, then any I/O pins used for% ?* ^8 _ r# e2 E+ a% S
configuration in banks 14 and 15 must also be powered and operated at 1.8V or 1.5V.$ p9 a8 [, c# X
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