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http://pan.baidu.com/s/1eQl7md83 B: R3 v3 Q6 I Z
DATE: 02-14-2014 HOTFIX VERSION: 023
1 Z- n, v7 y$ {===================================================================================================================================
7 h. H/ R7 g- T6 i, w2 H3 ]CCRID PRODUCT PRODUCTLEVEL2 TITLE7 p8 q. N* o3 k$ [
===================================================================================================================================# x1 s9 A* a, k4 Q4 r( a( ?
1120183 F2B DESIGNVARI Variant Editor Filter returns incorrect results.
9 @) }' V" ~- r6 N. Q1202715 SPIF OTHER Objects loose module group attribute after Specctra% b& h5 s E' O9 B9 p' q) d9 I! k
1203443 ADW LRM LRM takes a long time to launch for the first time
: |8 P @! H X% Z& a1207204 concept_HDL CORE schematic tool crashed during save all. y' e3 R8 M+ \& H( E& N. \5 [
1222101 CONCEPT_HDL CORE Pins are shorted on a block by the Block's title delimiter i' g3 V+ ]* x5 Q
1223709 FSP FPGA_SUPPORT Need FSP model of Altera 5AGZME3E3H29C4 FPGA
: R/ M* w! `5 k0 P' ^1224025 allegro_EDITOR INTERFACES The 3D viewer when working on a brd file shows package placed on BOTTOM side of my board while it is present on TOP side
- s" E, C( @+ _% u" A2 W' t1225591 F2B PACKAGERXL Aliased net signals starting with equals sign are not resolved correctly in cmgr- L: k7 Y% C4 J, j: Y1 V
1226480 ALLEGRO_EDITOR EDIT_ETCH Routing time is took to double increase when using the Add Connect because DRC is Allowed.0 }/ Q( h( t7 [! ]1 p
1229234 FLOWS PROJMGR Can't open the part table file from Project Setup
( V" ^6 F- X1 C1 p" w/ p1229555 ALLEGRO_EDITOR ARTWORK IPC-2581 not recognizing pin offsets correctly.
8 X R0 ]/ O, r+ B7 L1229610 FSP FPGA_SUPPORT New FPGA device request - Altera Cyclone V ST: 5CSTFD6D5F31I7" ]( w2 V7 Y$ b7 K6 q- x0 t- f0 v; N
1229664 ALLEGRO_EDITOR SHAPE Shape not voiding different net pins causing shorts with no DRC's9 s& {+ R) p! h5 c7 y
1232601 ALLEGRO_EDITOR MANUFACT Cannot add test point to via on trace.
, R" |6 d7 p3 ?6 s% ~" ]5 o1232772 ALLEGRO_EDITOR DATABASE When applying a place replicate module Allegro crashes% m0 y2 d0 ?3 @$ r! K2 b! a9 z
1233216 SIP_LAYOUT DIE_ABSTRACT_IF Allow more than 2 decimal places for the shrink facor in the add codesign form$ ^# h2 t3 F- @4 z
1233690 PDN_ANALYSIS PCB_STATICIRDROP PDN IRDrop: Mesh mode in Report is incorrect.9 X, E3 @8 K6 h7 Q* r- U
1233977 ALLEGRO_EDITOR INTERFACES single shape copied and rotated fails to create when importing IDX! [1 o1 c' b1 F+ h1 V7 p2 X
1234357 SIP_LAYOUT SCHEMATIC_FTB DSMAIN-335: Dia file(s) error has occurred.7 E/ J% a' G- U
1234450 ALLEGRO_EDITOR INTERFACES clines, pads, etch shapes to be at the same level with the board when viewed in STEP viewer.
0 W/ p2 \: E/ h7 R' K8 d t1235587 Pspice MODELEDITOR PSpice Model Import Wizard does not display symbol graphics for DE-HDL Symbol/ U) c$ o8 _& q$ t8 a/ N; i X
1236571 ALLEGRO_EDITOR GRAPHICS Allegro display lock up and panning issues+ ^% X. e, B8 a- D: k0 R
1237415 ALLEGRO_EDITOR INTERFACES Multidrill pad is exported with single Drill in the STEP File
6 i5 H5 j0 } ^( O' v1237807 ALLEGRO_EDITOR SCHEM_FTB The line feed code of netview.dat |
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发表于 2014-2-18 18:04
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