Hotfix_SPB16.60.023_wint_1of1

steven.ning

http://pan.baidu.com/s/1eQl7md8
DATE: 02-14-2014   HOTFIX VERSION: 023
===================================================================================================================================
- z7 k! ~% z; C. t9 lCCRID   PRODUCT        PRODUCTLEVEL2   TITLE
: C8 @/ D. ]& V* F& T+ h* O% j===================================================================================================================================
1120183 F2B            DESIGNVARI       Variant Editor Filter returns incorrect results.
' q' d2 O8 h  \7 G! C3 J1202715 SPIF           OTHER            Objects loose module group attribute after Specctra
+ ?: N4 k9 d) e6 W( R( k1203443 ADW            LRM              LRM takes a long time to launch for the first time
' ?2 y- F0 Y* E: \' ?1207204 concept_HDL    CORE             schematic tool crashed during save all
1222101 CONCEPT_HDL    CORE             Pins are shorted on a block by the Block's title delimiter
* t7 n# g% K3 A6 \1223709 FSP            FPGA_SUPPORT     Need FSP model of Altera 5AGZME3E3H29C4 FPGA
: @5 Y# E3 e. w( h" g$ l$ P% {1224025 allegro_EDITOR INTERFACES       The 3D viewer when working on a brd file shows package placed on BOTTOM side of my board while it is present on TOP side
- {: D+ D, P: Z5 E1225591 F2B            PACKAGERXL       Aliased net signals starting with equals sign are not resolved correctly in cmgr
1226480 ALLEGRO_EDITOR EDIT_ETCH        Routing time is took to double increase when using the Add Connect because DRC is Allowed.
0 e. j. q  q1 |& D6 P! N, \: ]1229234 FLOWS          PROJMGR          Can't open the part table file from Project Setup
' Z  ?% ?& A" _1 ?1 N( N8 v5 k1229555 ALLEGRO_EDITOR ARTWORK          IPC-2581 not recognizing pin offsets correctly.
1229610 FSP            FPGA_SUPPORT     New FPGA device request - Altera Cyclone V ST: 5CSTFD6D5F31I7
: b' ]& _& |/ J, p* M' K1229664 ALLEGRO_EDITOR SHAPE            Shape not voiding different net pins causing shorts with no DRC's
) g7 s  i# [, A$ R1232601 ALLEGRO_EDITOR MANUFACT         Cannot add test point to via on trace.
1232772 ALLEGRO_EDITOR DATABASE         When applying a place replicate module Allegro crashes
1233216 SIP_LAYOUT     DIE_ABSTRACT_IF  Allow more than 2 decimal places for the shrink facor in the add codesign form
" A3 c* F7 {3 h9 Z4 F+ N1233690 PDN_ANALYSIS   PCB_STATICIRDROP PDN IRDrop: Mesh mode in Report is incorrect.
1233977 ALLEGRO_EDITOR INTERFACES       single shape copied and rotated fails to create when importing IDX
1234357 SIP_LAYOUT     SCHEMATIC_FTB    DSMAIN-335: Dia file(s) error has occurred.
1234450 ALLEGRO_EDITOR INTERFACES       clines, pads, etch shapes to be at the same level with the board when viewed in STEP viewer.
4 {3 W* U/ V. {" z0 k6 I- ?0 Z6 F# P1235587 Pspice         MODELEDITOR      PSpice Model Import Wizard does not display symbol graphics for DE-HDL Symbol
1236571 ALLEGRO_EDITOR GRAPHICS         Allegro display lock up and panning issues
1237415 ALLEGRO_EDITOR INTERFACES       Multidrill pad is exported with single Drill in the STEP File
. d  j0 O: j7 x9 i: d1237807 ALLEGRO_EDITOR SCHEM_FTB        The line feed code of netview.dat

larryfarn

Thanks a lot.

mengshang

点赞，谢谢分享啊

wolfshiao

昨天才重灌16.60.022說,結果進了StartPage頁,就看到有.023出了,
; z6 A: _7 |1 P  q真是暈倒!!!!
% w6 R6 Z, j! O: ^7 a* h- s+ {太感謝steven.ning大大提供這網速快的百度網盤的資料下載了...

yuankai

感谢楼主分享

ziyu

更新太快了。。。

x68049

可以提供另一種下載方式嗎?

steven.ning

http://dl.vmall.com/c0fu1auqa8

linsky2000

楼主给力，两种网盘都上传了！