Hotfix_SPB16.60.022_wint_1of1

steven.ning

http://pan.baidu.com/s/1bnpaZfD

sztyzhi

太快了，刚装了021

suiwinder

正在下载

yuxifeng

能告知补丁包的功能及解决的BUG吗？

steven.ning

yuxifeng 发表于 2014-2-11 10:38
能告知补丁包的功能及解决的BUG吗？

我只是从EDA365网上搬运了一下而已，原来那个下载太慢，我把我下的转到云盘上,速度快，方便大家下载.更新了什么我也不清楚.

jsf120

找了半天，感谢分享

wolf343105

非常感谢steven.ning,祝你马年发大财.

nbxiong

等的花都谢了，更新好慢，跟看美剧似的。。。

steven.ning

wolf343105 发表于 2014-2-11 15:15
非常感谢steven.ning,祝你马年发大财.

; w- P% f6 _, x9 d' G* k0 @1 l9 O谢谢，也祝你马年行大运！

steven.ning

yuxifeng 发表于 2014-2-11 10:38
能告知补丁包的功能及解决的BUG吗？

* t+ d- A; J" Y; R$ ]( v  K8 W6 fDATE: 02-07-2014   HOTFIX VERSION: 022
8 |! {3 P( M2 I7 t/ S9 z) C1 H===================================================================================================================================
CCRID  PRODUCT        PRODUCTLEVEL2   TITLE
* _# O! x/ e5 p# \4 c5 |8 ]===================================================================================================================================
! d' h. y- ~- h' z0 i192358 ALLEGRO_EDITOR PADS_IN         Pad_in does not translate some copper shapes
222141 ALLEGRO_EDITOR PADS_IN          PADS_IN: Extra shapes are created whenimporting PADS design
274314 ALLEGRO_EDITOR PADS_IN         PAD_in boundary defined for flooded area be translated DYN
413919 ALLEGRO_EDITOR PADS_IN         pads_in cannot import width of refdes.
609053 ALLEGRO_EDITOR PADS_IN         "Mils to oversize" of "pads in" did not workcorrectly for MM data.
666214 CONCEPT_HDL    OTHER            Option to increase Line thicknessin publishpdf utility
( h' h6 h, o8 L8 t5 q" V* _) G738482 ALLEGRO_EDITOR GRAPHICS        Export image creates black image with Nvidia GeForce 8400M GS Graphicscard
982950 CONCEPT_HDL    OTHER            change the mouse button for thestroke to have same function with in pcb editor
) o6 B2 s& a" K0 @) a, ?9 }1020886 SIP_LAYOUT     LEFDEF_IF        a quicker way to promote die pins (byimporting macro_pin list)
1032678 CIS            VIEW_DATABASE_PA View Database Partgives incorrect result in complex design with variants.
. u. J+ R/ T& Z4 v1033864 ALLEGRO_EDITOR PADS_IN          pads_in doesnot translates teardropspresent in design
1054862 CONCEPT_HDL    OTHER           Option to increase Linethickness in publishpdf utility
+ T* k( [+ Z: v$ s$ M4 c1055252 FSP            PROCESS          Add a synthesis option to target agroup to contiguous or consecutive banks
1100772 CONSTRAINT_MGR OTHER            In Constraint Manager > DRC >Spacing the Show Element DRC totals are wrong.
+ |# a3 M' _4 d9 ?; X, f+ V1135020 CIS            DESIGN_VARIANT   Variant list is showing wrong results forhierarchical designs
) y. B% D$ L. L# W# _0 _3 i1138951 SIP_LAYOUT     DIE_ABSTRACT_IF  Fix die abstract r/w to properly supportpinnumbers on ports
1140042 CONSTRAINT_MGR OTHER            Diff_Pair lengths and analysis arelost after closing and opening Constraint Manager.
1143662 ALLEGRO_EDITOR INTERACTIV       Enhancement Request for RMB - Snap Pickto  options increased to include Pin edge
1147961 PSPICE         SIMULATOR        Simulation produces no output data
1150874 ALLEGRO_EDITOR PADS_IN          Dimensions in PADS are not translatedcorrectly during pads_in translation
' F, Z+ q* B& U) R* D5 t& I1154184 CONSTRAINT_MGR CONCEPT_HDL      Difference in the way topology isextracted in 16.3 versus 16.6
- h, u: n4 f3 S7 o( V5 P1154770 CAPTURE        PROPERTY_EDITOR  Variant Name property doesn't show value inVariant View mode
5 f& \$ h0 L1 U- c* u' l1158350 CONCEPT_HDL    CORE             Need a warning Message whileimporting a 16.3 sub-design in a 16.6 Design
$ V$ f$ [5 z* g* J, e1162347 ALLEGRO_EDITOR EDIT_ETCH        Enh- Allow new option in Move commandsuch that it allows stretching etch using only 45/90 degree segments directly
/ a8 G1 e/ Y0 k8 ~3 I4 i3 P1165553 ALLEGRO_EDITOR INTERACTIV       Subclass list invoked from the statuswindow does not represent correct colors.
- f3 n& s6 j9 p+ i9 ~  w1168079 FSP            MODEL_EDITOR     Clicking OK or Save As in rules editorallows user to overwrite the master with no warning
1172043 SCM            OTHER            : in pin name causes SCM to crash
1172207 CAPTURE        STABILITY        Capture crash while adding new partfrom Spreadsheet
8 |% i  v8 ?+ ^4 O6 |1172743 ADW            TDA              Allowed character set for thecheck-in comments is too limited
! E4 p' o! Y5 A8 A; Z& J/ }( w1174099 SIP_LAYOUT     WIREBOND         Option to reconnect wire based on 縫in name� in the Wire Bond Replace
1177672 APD            IMPORT_DATA      Netlist-in wizard didn縯 provide detail information about whatcolumns have been ignored by import process
8 s/ X' Q7 G1 r) l/ h, ?4 e, E1177714 CONCEPT_HDL    RF_LAYOUT_DRIVEN RF component's LOCATIONproperty can not be set to invisible
' M5 q- {# r' t) i8 C1177820 CONSTRAINT_MGR INTERACTIV       Done the Allegro command when attemptingto launch CM
, b: ^0 I8 m$ H1 ~1178586 ALLEGRO_EDITOR EDIT_SHAPE       Number of digits displayed after thedecimal point of Shape Creation function does not match the Accuracy of BRD
1179688 PSPICE         STABILITY        pspice crash for particular HOMEvariable vlaue
7 |3 R$ }( U  K, d6 X1179827 SIP_LAYOUT     OTHER            SiP Layout - Spreadsheet to Symbolexport - enable field to add Keywords for data fields to excell cells
# \3 d/ N3 v8 z  M: \$ N5 l1179879 SIP_LAYOUT     STREAM_IF        Data file corrupt when exporting Streamdata from SiP database.
2 g4 m1 I- Z* {& E& K9 M& n( V3 T$ G  m1180164 F2B            BOM              BOM csv data format converts toexcel formats
1180477 ALLEGRO_EDITOR INTERFACES       IPC-356 output is listing a duplicatelocation in the comment section
+ b1 w# F& K4 Y  J1 O1180932 SIP_LAYOUT     OTHER            SiP Layout - Symbol to Spreadsheetadd option for writing to existing spreadsheet
# Q1 U, X2 ?$ v2 B1181377 ALLEGRO_EDITOR INTERACTIV       Pick Releative does not work correctlywith RMB-Move Vertex
! u" B6 |9 `, |( A1181516 ALLEGRO_EDITOR DRC_CONSTR       Getting a "Thru Pin to RouteKeepout Spacing" when there should not be one.
2 A! u( {% \% b- u. l' E6 u1 j1181739 GRE            CORE             Running Plan > Spatial crashesGRE
8 |" }5 ^( ?0 X/ z( z+ B1181935 ALLEGRO_EDITOR DATABASE         Enh. Property that allows internal C-CDRC errors
4 {4 c% D5 A, D1182185 SIP_LAYOUT     OTHER            SiP Layout - Import symbolspreadsheet - suppress Family for the font in the XML spreadsheet
7 U0 P& o+ U- D8 t2 M, P* r1182566 SIP_LAYOUT     OTHER            SiP Layout - Spreadsheet to symbol- Enhance ability of spreadsheet exchange to allow for a portion of a full pinmap
1182599 CONSTRAINT_MGR DATABASE         CM Prop Delay Actuals do not updateafter Z Axis option is turned ON or OFF and Analyze is run.
# I) q0 c9 ^, G: G0 A% D# l1182892 CAPTURE        SCHEMATIC_EDITOR Pspice marker rotationbefore placement
1183682 ALLEGRO_EDITOR DRC_CONSTR       Implement Nodrc_Sym_Pin_Soldermask &Nodrc_Sym_Pin_Pastemask to symbol level
1185445 SIP_LAYOUT     DIE_ABSTRACT_IF  Die abstract export needs to be able toselect xda file type when browsing
2 O, h- |  c9 v: B- ~& y! P1185932 ALLEGRO_EDITOR SHAPE            Soldermask in solder mask void DRC
1185946 CONCEPT_HDL    CORE             Ericsson perfomance testing report5 sept 2013
6 ^8 b+ ?- H% O$ P7 Z1187213 FLOWS          PROJMGR          Unable to lock the directive:backannotate_forward
/ P' x* U% |9 X, ?; M& V1187444 ALLEGRO_EDITOR DRC_CONSTR       With this design Database check promptserror "SPMHGE-47: Error in call to batch DRC"
' `4 d4 j) }( G' E5 A3 y0 d1187597 ALLEGRO_EDITOR DRC_CONSTR       No Package to Package Spacing DRC error,when symbol overlap sideways at 45 degree.
1187723 FSP            PROCESS          Synthesis can fail depending on componentplacement
1188164 SIP_LAYOUT     OTHER            SiP Layout - Spreadsheet interfacesImport Export and Add Component - include Keyword for NET_GROUP
1188245 CONCEPT_HDL    CORE             INFO(SPCOCN-2055): You cannot runthe CHANGE command in a read only schematic
( |/ n& |9 F9 w" z' y/ w1190927 CONCEPT_HDL    CORE             Check sheet does not reportshorted signal/power nets if power symbol is connected to a pin
/ I0 m2 f& J. p! ^/ j1191497 ALLEGRO_EDITOR INTERACTIV       ENH: Adding names to the text blockparameters numbers
1192005 SIP_LAYOUT     IMPORT_DATA      Import SPD2 is missing 1 smart metalshape from file
1 [0 X2 S. Z; c! N" i1192204 ALLEGRO_EDITOR EXTRACT          Need ability to extract vias that arelabeled as microvia
  B* h# A5 j! |1193063 ALLEGRO_EDITOR MANUFACT         TestPrep log displays "Pin is notaccessible from bottom". The component is through hole.
6 ^' u, i# C  R5 {- M4 X* o( W8 J1193418 ALLEGRO_EDITOR GRAPHICS         3D Viewer can`t export image  in both SPB166S015 and SPB165S047
1194305 SIP_LAYOUT     EXPORT_DATA      export package overlay creates file withno package info
2 N+ n5 [. O9 w1194418 APD            IMPORT_DATA      issue when doFile->import->netlist-in wizard
# x8 D9 _6 ?1 L; x0 K. E2 R8 @% b: S1195279 F2B            PACKAGERXL       Ptf files are not being read whenpackaging with Cache
2 {2 s- u/ W& ~9 U, Z1195374 ALLEGRO_EDITOR INTERACTIV       Modules are not showing up in Tools >Module reports
1196603 SIP_LAYOUT     EXPORT_DATA      Change form for "Write PackageOverlay..." to better support longer lists of routing layers
1197302 CONSTRAINT_MGR UI_FORMS         Inconsistancy in selection of objectfor Spacing Constraint Worksheet
1197399 CAPTURE        OTHER            Draw toolbar disappears when usingPrint Preview
1197543 ADW            TDA              TDO does not correctly showdeleted pages
1198033 CONCEPT_HDL    CORE             Signals do not get highlightedwhen Show Physical Net Name is option enabled
& c5 u( x( {+ [7 C+ G4 e  Y1198468 ALLEGRO_EDITOR GRAPHICS         3D_step model does not show thecorrect view in 3D_Viewer when symbols have multiple place_bounds.
7 z% W8 t% {% S$ T1198617 CIS            GEN_BOM          Mech parts are showing with Partreference in CIS BOM
1199764 ALLEGRO_EDITOR SHAPE            Allegro crashes when trying todelete small island on POWER layer.
* j9 C, J3 B0 T% `$ E! t& g* ~1200232 ALLEGRO_EDITOR INTERACTIV       Moving all items including board outlinewhich is made of lines does not move the board outline in General Edit Mode.
1200748 ALLEGRO_EDITOR INTERACTIV       Additional pin edge vertex object tosnap pick
1201056 ALLEGRO_EDITOR DATABASE         Unsupported functionality strip designcreates a .SAV file
1201638 CIS            PART_MANAGER     Part retains previous linking inside thesubgroup
1201834 ALLEGRO_EDITOR PLOTTING         Bug: Import Logo command changesresulting imported object
1202406 SIP_LAYOUT     OTHER            enable the dynamic display of componentpin names for co-design dies in Sip Layout
; h. c& q! U5 @1202431 CONCEPT_HDL    PDF              The publishpdf -variant optionshould have a "no graphics" option
1202717 ALLEGRO_EDITOR DATABASE         About Warning(SPMHA1-108):Illegal linesegment ... end points.
* }" F9 Z4 s' X! j" g1203459 CONSTRAINT_MGR INTERACTIV       Object Report has no mechanism to outputinformation for a specific design.
& U8 C! r+ C' a/ S, j# \4 k) D0 @1204544 F2B            DESIGNVARI       Variant Editor does not warn on save ifno write permissions are on the file
5 N. i5 V  F7 T5 |1205500 FSP            CONSTRAINTS MAPP FSP FPGA port mapping VHDLsyntax
1205952 ALLEGRO_EDITOR GRAPHICS         Step Model for Mechanical Part isvisible in 3D viewer only when Etch Top Subclass is enabled
1206103 SIP_LAYOUT     IC_IO_EDITING    add port name property to pins, and addSkill access I/O driver cell data
2 U, k5 g& ]1 @! o1206546 CAPTURE        ANNOTATE         User assigned refdes are resettingwhen 緼nnotation type� is set to 縇eft-Right� or 縏op-Bottom�
1206561 ALLEGRO_EDITOR GRAPHICS         Not all mechanical symbols made with Stepfiles are displayed in the 3D View
$ m: z% K- \8 i0 U0 @1207125 SIG_INTEGRITY  ASSIGN_TOPOLOGY  ECSet mapping wrong for 2 bit in a 4bit bus
% E5 q! O- U' A: z9 U& f& F: {1 R1207386 CAPTURE        GENERATE_PART    Altera pin file not generating the partproperly
1207629 CAPTURE        TCL_INTERFACE    Bug: GetMACAddresses tcl command notworking
1207994 CAPTURE        TCL_INTERFACE    TCL pdf export in 16.6 fills DOT type pinswith black color
1208017 F2B            DESIGNVARI       sch name is not same when updatingSchematic View while backannotating Variant
3 ]' b( U1 N/ G$ m8 h& m: b& t1209363 ALLEGRO_EDITOR INTERFACES       When placing pins using the polarcommand the tool returns 4500.00 for 45 degrees.
1209769 CONCEPT_HDL    CORE             Top DCF gate information missing
& B+ Z% L, z0 X2 |6 O$ p1210194 CONCEPT_HDL    CONSTRAINT_MGR   HDL crashes with Edit Via List dialog box
1210442 CONCEPT_HDL    INFRA            Save design givesERROR(SPCOCN-1995): Non synchronized constraint property found in schematicpage
$ X: r1 K* T* Z. G: o' t) [1210685 ASI_PI         GUI              User can't edit padstack inPowerDC-lite
1210744 SIG_INTEGRITY  SIGWAVE          SigWave: FFT Mode Display unit seemsnot to be correct
1210829 CAPTURE        NETLIST_VERILOG  Shorted port is missing from verilog file
; _6 B, o7 |/ X1210850 CONCEPT_HDL    CORE             DE-HDL backannotation crashingafter instantiating specific cell from Ericsson BPc Library
1211620 ADW            COMPONENT_BROWSE Component BrowserPerformance
  i9 A6 D& O# J7 O3 ~1212102 ALLEGRO_EDITOR INTERACTIV       Shape edit boundary adds arc mirrored tothe highlighted preview.
' t0 L( x! L( N# z1213294 CONCEPT_HDL    SECTION          DE-HDL windows mode multiple section fails tosection first contactor pin from column of individual pins
0 u! A/ M$ a4 S: R% W) {8 _1213402 APD            DATABASE         The old "ix 0 0" fix  is now causing the features to lose netsentirely.
1213694 ALLEGRO_EDITOR PARTITION        Via connected to Dummy Net pin in Partitiongets connected to shape on the board after importing partition
" e, U* i5 ]2 W8 [! f1214247 CONSTRAINT_MGR UI_FORMS         Selecting the "All" folderin Spacing Constraints in CM does not automatically select the first column forediting
1214320 SIG_INTEGRITY  SIGNOISE         signoise command with -L and -k option
* `! P/ _3 V) Q! Q4 ~7 L/ U1214433 CONCEPT_HDL    CORE             Genview does not update sym_1 withports added to the schematic
5 Z# l! P( a% C+ k# c, k" s/ c1214909 ALLEGRO_EDITOR NC               NC Drill Legend show extra rowsfor drills
1214916 SIP_LAYOUT     OTHER            package design integrity check forvia-pin alignment with fix enabled hangs
0 ^' [4 H4 @1 R1215954 SIG_INTEGRITY  SIMULATION       Cycle.msm does not exist error whensimulating extracted net
( M, v4 ^8 g2 q8 t* u1216328 CAPTURE        STABILITY        Capture crash
1216993 ALLEGRO_EDITOR DRC_TIMING_CHK   Allegro crash on SPB16.50.049
1217450 F2B            BOM              ERROR 233: Output file path doesnot exist
: Z9 m8 @" f5 \* W, d0 d1217612 ALLEGRO_EDITOR INTERACTIV       Replace padstack will not replacepadstacks that have multiple alphabetic characters in the pin name - AB21-AB37
1217823 ALLEGRO_EDITOR INTERACTIV       Compose shape fails with SPMHIS-473
% a: \6 t" \* A# `. \; ~" X! D1217887 ALLEGRO_EDITOR INTERFACES       An undo option to be made available inthe STEP Package Mapping window
1218665 ALLEGRO_EDITOR INTERFACES       In step viewer, the bottom side partsare placed above the pcb board surface
1219053 PSPICE         PROBE            PSpice crash with the attachedDesign
1219067 ALLEGRO_EDITOR EDIT_ETCH        dynamic fillets behavior is unstable
) X5 C. S8 j# Q7 |# b. V- J+ }9 a( ~1219095 ALLEGRO_EDITOR MANUFACT         Design Cross section chart is taperedfor two layer board
9 G0 Z* o1 ~4 X: N5 K  n' h9 p' h; |1219126 ALLEGRO_EDITOR SKILL            Skill issue with axlRefreshSymbol()
1220701 ALLEGRO_EDITOR INTERACTIV       View > Windows > Worldview(showhide view command) fails with command not found
9 m! j: y1 J2 a, c3 G3 l+ T1221057 ALLEGRO_EDITOR REPORTS          Units in Cross section report forspacing is not synced with the design
1221139 ALLEGRO_EDITOR EDIT_ETCH        Delay tune is not tuning differentialpair
1221157 SIP_LAYOUT     IMPORT_DATA      import spd2/na2 file is not importingdata correctly into sip
# C' z% C9 V3 ^  t1221163 SIG_INTEGRITY  GEOMETRY_EXTRACT Simulation aborts withsevere convergence issue when coupled vias is enabled.
* B! A. {" I% P, a8 _* h+ l1221416 ALLEGRO_EDITOR DATABASE         strip design for function type
) U( Q* W- v. O5 q1221931 ALLEGRO_EDITOR DATABASE         Fatal software error when embeddingcomponent
$ r$ g9 T6 R- N0 B  Z1222105 CONCEPT_HDL    CORE             Moving Pins around the edge of aBlock causes the text of the pin to change its text size.
1222124 APD            DATABASE         Same Net DRC's exhibiting inconsistentbehavior.
5 @/ x$ g. S  q1222272 SIG_EXPLORER   EXTRACTTOP       Cannot extract net or open SigXplorerafter selecting a netgroup
3 b$ j4 J6 i0 ~0 _' i2 Z1222329 ALLEGRO_EDITOR SHAPE            STEP-Model  Symbol which has place bound bottom is on Top
1223183 SIP_LAYOUT     BGA_GENERATOR    Getting an incorrect error message whenusing the BGA generator with a long BGA name.
1223662 ALLEGRO_EDITOR REFRESH          Allegro crashes when trying torefresh symbol
" a3 G; b; x, ^1 d1223932 CONCEPT_HDL    CORE             DEHDL block desend does not find1st page if its not page1
1223940 CONSTRAINT_MGR UI_FORMS         Unable to change CLOCK name inSetup/Hold Worksheet under Timing in CM.
' B, O* X0 C8 R: J, ~1224127 SIG_INTEGRITY  IRDROP           Is the old static IRDrop in 16.6officially supported?
9 b3 |  h* Y3 H) t1225492 PCB_LIBRARIAN  CORE             PDV expand vector pins resizessymbol outline to maximum height again
( |( j2 i. U' e. R1225546 CONSTRAINT_MGR ECS_APPLY        nets where the referenced ECS mapscorrectly in constraints manager for front end but not in back end
1226405 ALLEGRO_EDITOR INTERFACES       File > Export > IDF ask for filterconfig file eventhough it is created in same session and stored in parent folder
% k8 L4 H6 [. }* o# J; X1226448 PDN_ANALYSIS   PCB_STATICIRDROP License failure about PDNAnalysis with XL and GXL
: R" \/ u: J8 |3 @+ T1228721 SIP_LAYOUT     OTHER            File Export Netlist Spreadsheetenhance sort to be a natural method per Jedec according to customer