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) |+ ^" c# a/ T/ ^7 u# cDATE: 02-07-2014 HOTFIX VERSION: 022
3 e1 }) O' K5 }- A+ D& u9 j. Q2 j2 l===================================================================================================================================) k% I+ X+ D" U, ]& g3 p5 Q
CCRID PRODUCT PRODUCTLEVEL2 TITLE! b$ Q* N3 Q9 p0 {! n( @# i: Z
===================================================================================================================================' P9 `6 V. |: S, N8 ^
192358 ALLEGRO_EDITOR PADS_IN Pad_in does not translate some copper shapes
s/ @- k6 b4 E7 v1 z5 d$ g222141 ALLEGRO_EDITOR PADS_IN PADS_IN: Extra shapes are created whenimporting PADS design
7 W3 U; U9 S9 I( T9 i' D" v274314 ALLEGRO_EDITOR PADS_IN PAD_in boundary defined for flooded area be translated DYN! b5 L/ ]" c. \* d* ]& ~% P
413919 ALLEGRO_EDITOR PADS_IN pads_in cannot import width of refdes.
" v2 O$ m. l( V6 c6 c. C% ]0 h609053 ALLEGRO_EDITOR PADS_IN "Mils to oversize" of "pads in" did not workcorrectly for MM data.
) c- }% @9 _ ?0 T666214 CONCEPT_HDL OTHER Option to increase Line thicknessin publishpdf utility
% ~+ e: d/ x" O2 S. E! g$ [9 X) `738482 ALLEGRO_EDITOR GRAPHICS Export image creates black image with Nvidia GeForce 8400M GS Graphicscard, W8 O6 A4 f1 q( ], _) }4 s
982950 CONCEPT_HDL OTHER change the mouse button for thestroke to have same function with in pcb editor
Y+ i& I( I: t$ @$ N1020886 SIP_LAYOUT LEFDEF_IF a quicker way to promote die pins (byimporting macro_pin list)
+ a! L( w* Q5 H* Q2 b3 d7 M# J1032678 CIS VIEW_DATABASE_PA View Database Partgives incorrect result in complex design with variants. l" r% h6 D, K2 N# j9 i
1033864 ALLEGRO_EDITOR PADS_IN pads_in doesnot translates teardropspresent in design: ?/ I5 U: K2 L' s
1054862 CONCEPT_HDL OTHER Option to increase Linethickness in publishpdf utility; p; p# [4 F0 Q1 R+ s3 A3 M1 S# c
1055252 FSP PROCESS Add a synthesis option to target agroup to contiguous or consecutive banks. V9 a; x5 N S `
1100772 CONSTRAINT_MGR OTHER In Constraint Manager > DRC >Spacing the Show Element DRC totals are wrong.2 W: W0 z; J, \" \$ U7 i1 v! `
1135020 CIS DESIGN_VARIANT Variant list is showing wrong results forhierarchical designs- k- P% K+ N( {" B4 ~5 z/ p0 O* V' i
1138951 SIP_LAYOUT DIE_ABSTRACT_IF Fix die abstract r/w to properly supportpinnumbers on ports
9 O6 [; ]& Q' n; N1140042 CONSTRAINT_MGR OTHER Diff_Pair lengths and analysis arelost after closing and opening Constraint Manager.
- |/ O# x7 |4 q+ ]1143662 ALLEGRO_EDITOR INTERACTIV Enhancement Request for RMB - Snap Pickto options increased to include Pin edge/ W( _4 H% H0 H
1147961 PSPICE SIMULATOR Simulation produces no output data+ C; n, E( c8 A/ \3 n
1150874 ALLEGRO_EDITOR PADS_IN Dimensions in PADS are not translatedcorrectly during pads_in translation
Z9 e' O4 L) O1154184 CONSTRAINT_MGR CONCEPT_HDL Difference in the way topology isextracted in 16.3 versus 16.6
9 G. D1 ?8 u7 f+ b1154770 CAPTURE PROPERTY_EDITOR Variant Name property doesn't show value inVariant View mode
5 n; Y. M' s! n1158350 CONCEPT_HDL CORE Need a warning Message whileimporting a 16.3 sub-design in a 16.6 Design
! g+ N8 A# \, J4 x& m: q1162347 ALLEGRO_EDITOR EDIT_ETCH Enh- Allow new option in Move commandsuch that it allows stretching etch using only 45/90 degree segments directly
7 x; T) s, B/ z1165553 ALLEGRO_EDITOR INTERACTIV Subclass list invoked from the statuswindow does not represent correct colors.
s, h$ I& I* O# l! Y( ^6 n% h& Z1168079 FSP MODEL_EDITOR Clicking OK or Save As in rules editorallows user to overwrite the master with no warning* s7 J* l7 d# H: ^8 [
1172043 SCM OTHER : in pin name causes SCM to crash
( e& y! z. d7 p2 ]0 s x! s' g1172207 CAPTURE STABILITY Capture crash while adding new partfrom Spreadsheet
! R) t, A0 [. @9 M( M+ x1172743 ADW TDA Allowed character set for thecheck-in comments is too limited
) ?5 z; v0 \- A7 l. Q# z6 X1174099 SIP_LAYOUT WIREBOND Option to reconnect wire based on 縫in name� in the Wire Bond Replace4 V# A6 C5 j6 i, T
1177672 APD IMPORT_DATA Netlist-in wizard didn縯 provide detail information about whatcolumns have been ignored by import process& I1 W- h6 o4 N
1177714 CONCEPT_HDL RF_LAYOUT_DRIVEN RF component's LOCATIONproperty can not be set to invisible. t8 S$ C4 n" Z0 l* y( e: Z
1177820 CONSTRAINT_MGR INTERACTIV Done the Allegro command when attemptingto launch CM! t. x6 d7 b& J. z2 I) ]8 N0 W! y
1178586 ALLEGRO_EDITOR EDIT_SHAPE Number of digits displayed after thedecimal point of Shape Creation function does not match the Accuracy of BRD, H. q4 ?( q! {9 r9 Y8 A9 S
1179688 PSPICE STABILITY pspice crash for particular HOMEvariable vlaue3 \* v3 l' Z2 i* l7 i% O: B% g6 X
1179827 SIP_LAYOUT OTHER SiP Layout - Spreadsheet to Symbolexport - enable field to add Keywords for data fields to excell cells
( a- B0 M1 N, ~ C. j1179879 SIP_LAYOUT STREAM_IF Data file corrupt when exporting Streamdata from SiP database.
3 E* x! I: `7 X- x2 E1180164 F2B BOM BOM csv data format converts toexcel formats
, {( K# Y% M! Z4 y4 k/ L8 Q! T6 s6 L: g1180477 ALLEGRO_EDITOR INTERFACES IPC-356 output is listing a duplicatelocation in the comment section
1 g7 b# s# c. e' X8 z# p9 J1180932 SIP_LAYOUT OTHER SiP Layout - Symbol to Spreadsheetadd option for writing to existing spreadsheet3 p5 A+ T7 Q$ z$ W q
1181377 ALLEGRO_EDITOR INTERACTIV Pick Releative does not work correctlywith RMB-Move Vertex V7 _8 y' N( G9 R$ w
1181516 ALLEGRO_EDITOR DRC_CONSTR Getting a "Thru Pin to RouteKeepout Spacing" when there should not be one.
4 h8 K9 G$ x8 [2 |# J; h7 Q8 ?1181739 GRE CORE Running Plan > Spatial crashesGRE4 c- |4 S" N- _4 S$ v. |& A
1181935 ALLEGRO_EDITOR DATABASE Enh. Property that allows internal C-CDRC errors' w/ K! h8 b6 Y1 E; W [
1182185 SIP_LAYOUT OTHER SiP Layout - Import symbolspreadsheet - suppress Family for the font in the XML spreadsheet$ a! g7 R, L" S6 w, X: O! z
1182566 SIP_LAYOUT OTHER SiP Layout - Spreadsheet to symbol- Enhance ability of spreadsheet exchange to allow for a portion of a full pinmap. O8 x2 M0 O: }5 Q8 I
1182599 CONSTRAINT_MGR DATABASE CM Prop Delay Actuals do not updateafter Z Axis option is turned ON or OFF and Analyze is run.' x9 W/ r' [! A0 @
1182892 CAPTURE SCHEMATIC_EDITOR Pspice marker rotationbefore placement
9 t. f" _ Q& ]1 D9 {2 z1183682 ALLEGRO_EDITOR DRC_CONSTR Implement Nodrc_Sym_Pin_Soldermask &Nodrc_Sym_Pin_Pastemask to symbol level1 h: J3 n# f f
1185445 SIP_LAYOUT DIE_ABSTRACT_IF Die abstract export needs to be able toselect xda file type when browsing+ y4 m% t+ M* l8 \" g
1185932 ALLEGRO_EDITOR SHAPE Soldermask in solder mask void DRC
$ A# V1 v* ?0 V4 O1185946 CONCEPT_HDL CORE Ericsson perfomance testing report5 sept 2013: I9 d( `3 Q0 g
1187213 FLOWS PROJMGR Unable to lock the directive:backannotate_forward
2 s$ K, @6 G8 Y8 i1187444 ALLEGRO_EDITOR DRC_CONSTR With this design Database check promptserror "SPMHGE-47: Error in call to batch DRC"
( b7 g) H9 x- P1187597 ALLEGRO_EDITOR DRC_CONSTR No Package to Package Spacing DRC error,when symbol overlap sideways at 45 degree./ e: L% G! K$ x
1187723 FSP PROCESS Synthesis can fail depending on componentplacement( r# t; z! y4 q% t' T
1188164 SIP_LAYOUT OTHER SiP Layout - Spreadsheet interfacesImport Export and Add Component - include Keyword for NET_GROUP# `, i9 U" T* H: K; y
1188245 CONCEPT_HDL CORE INFO(SPCOCN-2055): You cannot runthe CHANGE command in a read only schematic0 C( L+ t( n1 C. }
1190927 CONCEPT_HDL CORE Check sheet does not reportshorted signal/power nets if power symbol is connected to a pin; R# O5 _) n4 o# @( c2 K+ Q1 S. M
1191497 ALLEGRO_EDITOR INTERACTIV ENH: Adding names to the text blockparameters numbers
' q9 ^7 M; S+ R m1192005 SIP_LAYOUT IMPORT_DATA Import SPD2 is missing 1 smart metalshape from file
+ t' |+ T t; U9 w& A' g2 {2 J1192204 ALLEGRO_EDITOR EXTRACT Need ability to extract vias that arelabeled as microvia
0 ]4 l4 j* f5 r. c1193063 ALLEGRO_EDITOR MANUFACT TestPrep log displays "Pin is notaccessible from bottom". The component is through hole.% F8 H$ H7 R, a% o0 N
1193418 ALLEGRO_EDITOR GRAPHICS 3D Viewer can`t export image in both SPB166S015 and SPB165S047
# ~$ o, X) C% K! [/ k3 f# g1194305 SIP_LAYOUT EXPORT_DATA export package overlay creates file withno package info; W" A3 O! i& d" q) n8 K
1194418 APD IMPORT_DATA issue when doFile->import->netlist-in wizard
1 J' H) U/ P7 L) ^8 `3 ~# y1195279 F2B PACKAGERXL Ptf files are not being read whenpackaging with Cache) x1 n0 w5 T5 t" e
1195374 ALLEGRO_EDITOR INTERACTIV Modules are not showing up in Tools >Module reports, e9 H& h! z; ^- B4 f2 n9 c6 b
1196603 SIP_LAYOUT EXPORT_DATA Change form for "Write PackageOverlay..." to better support longer lists of routing layers
: a t* H2 s& ?7 i8 b( d/ `1197302 CONSTRAINT_MGR UI_FORMS Inconsistancy in selection of objectfor Spacing Constraint Worksheet
4 L5 H9 k% L$ M3 V3 _+ s1197399 CAPTURE OTHER Draw toolbar disappears when usingPrint Preview; w+ h) @) ` K! g5 Z
1197543 ADW TDA TDO does not correctly showdeleted pages1 q9 j; {% S- `4 i% J8 m
1198033 CONCEPT_HDL CORE Signals do not get highlightedwhen Show Physical Net Name is option enabled
# K. k- k8 E U$ J, J9 V% M1198468 ALLEGRO_EDITOR GRAPHICS 3D_step model does not show thecorrect view in 3D_Viewer when symbols have multiple place_bounds.
% a f" ^' t; O' Q3 A1198617 CIS GEN_BOM Mech parts are showing with Partreference in CIS BOM$ i, q( l% x% Q7 i7 e0 R
1199764 ALLEGRO_EDITOR SHAPE Allegro crashes when trying todelete small island on POWER layer.. ?9 s9 w {4 u1 l4 }( ]
1200232 ALLEGRO_EDITOR INTERACTIV Moving all items including board outlinewhich is made of lines does not move the board outline in General Edit Mode.# s1 k& P- j# R4 N/ Z
1200748 ALLEGRO_EDITOR INTERACTIV Additional pin edge vertex object tosnap pick
5 F9 U3 ^1 l: ^1201056 ALLEGRO_EDITOR DATABASE Unsupported functionality strip designcreates a .SAV file3 i1 }9 u5 I4 F: y
1201638 CIS PART_MANAGER Part retains previous linking inside thesubgroup
% Z' x+ l! W- E: X1201834 ALLEGRO_EDITOR PLOTTING Bug: Import Logo command changesresulting imported object
], v- I* I/ r; K: f1202406 SIP_LAYOUT OTHER enable the dynamic display of componentpin names for co-design dies in Sip Layout2 e5 ]2 _% E% C4 E+ \
1202431 CONCEPT_HDL PDF The publishpdf -variant optionshould have a "no graphics" option
- a5 f- \1 C1 e4 I' o1202717 ALLEGRO_EDITOR DATABASE About Warning(SPMHA1-108):Illegal linesegment ... end points.
5 ^, t: n% ~" B1203459 CONSTRAINT_MGR INTERACTIV Object Report has no mechanism to outputinformation for a specific design.
( }; i7 M7 E3 t' l1204544 F2B DESIGNVARI Variant Editor does not warn on save ifno write permissions are on the file* g( ?* r" l7 y' O8 `
1205500 FSP CONSTRAINTS MAPP FSP FPGA port mapping VHDLsyntax r! c+ h5 g6 O+ p( w( K/ a
1205952 ALLEGRO_EDITOR GRAPHICS Step Model for Mechanical Part isvisible in 3D viewer only when Etch Top Subclass is enabled
# p3 K( k* k. \! o* C! V1206103 SIP_LAYOUT IC_IO_EDITING add port name property to pins, and addSkill access I/O driver cell data
# y* N) [/ J7 \0 x4 c1206546 CAPTURE ANNOTATE User assigned refdes are resettingwhen 緼nnotation type� is set to 縇eft-Right� or 縏op-Bottom�+ x p5 H2 ~1 E$ v* O* b
1206561 ALLEGRO_EDITOR GRAPHICS Not all mechanical symbols made with Stepfiles are displayed in the 3D View
' b4 U. F4 ^6 f0 I) i% t1207125 SIG_INTEGRITY ASSIGN_TOPOLOGY ECSet mapping wrong for 2 bit in a 4bit bus
: M% E* C% I. I& s+ e) v" w1207386 CAPTURE GENERATE_PART Altera pin file not generating the partproperly
& ^& K; B) V+ ?3 `: `1207629 CAPTURE TCL_INTERFACE Bug: GetMACAddresses tcl command notworking
( r$ a: t# c1 |6 w1207994 CAPTURE TCL_INTERFACE TCL pdf export in 16.6 fills DOT type pinswith black color/ J* p: S* r, @: ?
1208017 F2B DESIGNVARI sch name is not same when updatingSchematic View while backannotating Variant
{/ W% Y# m5 s1209363 ALLEGRO_EDITOR INTERFACES When placing pins using the polarcommand the tool returns 4500.00 for 45 degrees.
0 P+ \1 V L4 h( j! P1209769 CONCEPT_HDL CORE Top DCF gate information missing
; J B# k6 g7 k/ `1210194 CONCEPT_HDL CONSTRAINT_MGR HDL crashes with Edit Via List dialog box
* b, p6 V& v: g1210442 CONCEPT_HDL INFRA Save design givesERROR(SPCOCN-1995): Non synchronized constraint property found in schematicpage% L0 T3 }# {; r& o0 T) r) Y
1210685 ASI_PI GUI User can't edit padstack inPowerDC-lite4 X+ {$ d: `! o! G' y+ U2 g
1210744 SIG_INTEGRITY SIGWAVE SigWave: FFT Mode Display unit seemsnot to be correct0 `* N6 H0 y) h8 W" k5 J
1210829 CAPTURE NETLIST_VERILOG Shorted port is missing from verilog file
" j# _! F2 l$ ^5 J2 ~1210850 CONCEPT_HDL CORE DE-HDL backannotation crashingafter instantiating specific cell from Ericsson BPc Library: |) R+ s5 ~# b! j- @- Y
1211620 ADW COMPONENT_BROWSE Component BrowserPerformance% W0 ], w g0 E! f) e& Z9 O
1212102 ALLEGRO_EDITOR INTERACTIV Shape edit boundary adds arc mirrored tothe highlighted preview.# J: ]. j- ?* `1 D' ~
1213294 CONCEPT_HDL SECTION DE-HDL windows mode multiple section fails tosection first contactor pin from column of individual pins
; P2 |% E9 l" i' P! i1213402 APD DATABASE The old "ix 0 0" fix is now causing the features to lose netsentirely.# b, Z- e( B+ ]
1213694 ALLEGRO_EDITOR PARTITION Via connected to Dummy Net pin in Partitiongets connected to shape on the board after importing partition( S& g9 `8 E* x3 |* |
1214247 CONSTRAINT_MGR UI_FORMS Selecting the "All" folderin Spacing Constraints in CM does not automatically select the first column forediting
3 ~( J7 p, e8 K8 G1214320 SIG_INTEGRITY SIGNOISE signoise command with -L and -k option+ `. A& g. s( _+ T. U
1214433 CONCEPT_HDL CORE Genview does not update sym_1 withports added to the schematic
9 {# R9 N0 I0 G! i5 S4 z; X# N1214909 ALLEGRO_EDITOR NC NC Drill Legend show extra rowsfor drills
; m# W* b7 q3 x* _1 l: O# A; s3 d" ^# @) r1214916 SIP_LAYOUT OTHER package design integrity check forvia-pin alignment with fix enabled hangs& G% o0 X/ V6 d9 \! u
1215954 SIG_INTEGRITY SIMULATION Cycle.msm does not exist error whensimulating extracted net/ c, N8 C; `3 m1 ?( N6 p# T. v
1216328 CAPTURE STABILITY Capture crash0 }5 k2 Z9 `: Y' i y
1216993 ALLEGRO_EDITOR DRC_TIMING_CHK Allegro crash on SPB16.50.049
1 W; [8 {6 O" I% k5 O* S6 }1217450 F2B BOM ERROR 233: Output file path doesnot exist) ]7 a! f7 [4 l/ s$ ~9 n X$ W
1217612 ALLEGRO_EDITOR INTERACTIV Replace padstack will not replacepadstacks that have multiple alphabetic characters in the pin name - AB21-AB37
) V2 u3 Z5 }0 {7 X$ _; A1217823 ALLEGRO_EDITOR INTERACTIV Compose shape fails with SPMHIS-4733 O1 H; |3 s4 c+ m/ W A0 O
1217887 ALLEGRO_EDITOR INTERFACES An undo option to be made available inthe STEP Package Mapping window
+ z0 o$ x* l0 u* p, a1218665 ALLEGRO_EDITOR INTERFACES In step viewer, the bottom side partsare placed above the pcb board surface
# _. E: t, m& D& v, v1219053 PSPICE PROBE PSpice crash with the attachedDesign, q$ K, u% b# r+ U, {2 M1 c
1219067 ALLEGRO_EDITOR EDIT_ETCH dynamic fillets behavior is unstable
* z5 r! I) t' f/ v% V1219095 ALLEGRO_EDITOR MANUFACT Design Cross section chart is taperedfor two layer board8 V8 G) N! Z3 U4 N( m# V' ?8 w
1219126 ALLEGRO_EDITOR SKILL Skill issue with axlRefreshSymbol(), B# M1 Q- [/ ^ a2 s
1220701 ALLEGRO_EDITOR INTERACTIV View > Windows > Worldview(showhide view command) fails with command not found
$ e' Y5 ^, C1 N: v9 u6 T1221057 ALLEGRO_EDITOR REPORTS Units in Cross section report forspacing is not synced with the design$ O9 C8 s/ _/ H3 v& g4 p. \
1221139 ALLEGRO_EDITOR EDIT_ETCH Delay tune is not tuning differentialpair
7 a" J! u8 H. ^/ p4 k1221157 SIP_LAYOUT IMPORT_DATA import spd2/na2 file is not importingdata correctly into sip
* c" M+ z* Q9 a* Q8 E; ~+ v1221163 SIG_INTEGRITY GEOMETRY_EXTRACT Simulation aborts withsevere convergence issue when coupled vias is enabled.( v# K& y7 Q: K
1221416 ALLEGRO_EDITOR DATABASE strip design for function type6 M1 k& c* T, O& s6 |
1221931 ALLEGRO_EDITOR DATABASE Fatal software error when embeddingcomponent
/ [* Z1 p) A& @1 k# x# u; c1222105 CONCEPT_HDL CORE Moving Pins around the edge of aBlock causes the text of the pin to change its text size.
& w& B7 X' }: l3 m, ?! p* S7 V1222124 APD DATABASE Same Net DRC's exhibiting inconsistentbehavior.
7 w% W' U) J, T7 x; H3 P4 k1222272 SIG_EXPLORER EXTRACTTOP Cannot extract net or open SigXplorerafter selecting a netgroup
% N( n: _$ w4 O7 R! D: }1222329 ALLEGRO_EDITOR SHAPE STEP-Model Symbol which has place bound bottom is on Top
# V7 Y; W% j8 C0 t$ @1223183 SIP_LAYOUT BGA_GENERATOR Getting an incorrect error message whenusing the BGA generator with a long BGA name.
0 ^3 J* x, i/ j0 W) Y2 I0 _$ ^1223662 ALLEGRO_EDITOR REFRESH Allegro crashes when trying torefresh symbol" P0 X. N% B3 ?7 Y( N6 f
1223932 CONCEPT_HDL CORE DEHDL block desend does not find1st page if its not page1
7 t8 C5 w$ p, E0 H/ @4 R" m1223940 CONSTRAINT_MGR UI_FORMS Unable to change CLOCK name inSetup/Hold Worksheet under Timing in CM.; E/ L2 [2 t1 f3 d
1224127 SIG_INTEGRITY IRDROP Is the old static IRDrop in 16.6officially supported?
+ Z4 J7 y" G, g4 _* {* D S1225492 PCB_LIBRARIAN CORE PDV expand vector pins resizessymbol outline to maximum height again
1 v7 E1 @& K" \6 C/ r; z: D5 k- h1225546 CONSTRAINT_MGR ECS_APPLY nets where the referenced ECS mapscorrectly in constraints manager for front end but not in back end
2 @/ K; E, l( V5 D9 b( Z; R3 R1226405 ALLEGRO_EDITOR INTERFACES File > Export > IDF ask for filterconfig file eventhough it is created in same session and stored in parent folder
0 N& O6 Z) i+ J$ }3 `1 v. i; k1226448 PDN_ANALYSIS PCB_STATICIRDROP License failure about PDNAnalysis with XL and GXL
9 o. p( g9 W8 a1228721 SIP_LAYOUT OTHER File Export Netlist Spreadsheetenhance sort to be a natural method per Jedec according to customer |
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发表于 2014-2-10 15:09
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