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You have module Clock_Generator.v 3 t1 V3 T ~! O% P. t
with port input [31:0] key_value# c/ T- j, Y1 a
and you set a instance of * C: v/ E K+ N# b- U4 v, P* z
key_scan_jitter key_scan_jitter_inst
" I: U& \3 l; Q1 O% t (
; u# i- N. o2 U5 e8 S; [: N .clk(clk),7 h2 w e" ~" z( _
.rst_n(rst_n),
3 O2 \( T7 i5 o( Q2 _+ p8 m! Y& v .key_data(key_data),$ H$ G& ^" l8 L4 J$ G0 ?4 M- t
.key_flag(key_flag),
( L' k- I: F |% \( i! { W9 O .key_value(key_value)5 E' |2 U. S+ w9 i5 @) {/ {; W
);8 T) o- `7 O& K y$ k: A0 k
In module key_scan_jitter.v8 z I4 D% H$ ^: h! Q' @
you have output[31:0] key_value
. [5 q7 _/ u' Y3 F* K
% _: R/ }: @' H1 H& O3 H+ L4 tSo module have to source of key_value:
: a' c: A6 r% R5 @1. From input port (may be 32 pins of chip)8 z {, ~8 w/ \5 {
2. From internal instance key_scan_jitter
, [: Y2 v" O6 C* ~7 w6 y
0 L- u( E6 g$ h" |% RAltera can-t to do short circuit in your module.& G1 Y2 g8 l5 @$ @
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