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换了nandflash后和加焊DDR后有两种状态,但是板子都没有启动成功,串口有打印。/ O% G& i3 Z7 H% s
以下是状态1的log:
$ _% j0 y# s$ M4 f* V4 M* ~SoC preloader 1.0.0.r1422.lzma (Wed Nov 13 14:32:57 CST 2013)
3 b+ V" n+ P+ z3 i7 B3 DII: Stack @ 0x9fc1fd18 (parameter 736B)+ s- f$ g8 H, f7 t0 w* F- ?
II: Console... OK/ F5 W! C$ H: i# \$ B
Setting DTR% p* k0 O" O/ V( g
II: DRAM is set by software calibration... PASSED# l, }" {- |% Y8 {6 l+ ]
, m( D6 `. I+ v( V* x+ {) k
DDRKODL(0xb800021c):0x00000410. l0 s5 V2 ^" i0 x6 g
MCR (0xb8001000):0x22041de0, 0x21220000, 0x54433830, 0x0404030f
8 p) L2 Z& D! H7 u9 q' gDTR2(0xb8001010):0x0630d000
/ O' c/ m6 ~* y+ EPHY Registers(0xb8001500):' }7 Y, O, ^' j T- b) B3 `6 d
0xb8001500:0x80000010, 0x0000007f, 0xa1a00000, 0xfdffffff; N# e6 B' |' o
0xb8001510:0x00140a00, 0x00180c00, 0x00140a00, 0x00180c00
+ ^' i% k' F% p% ?$ r0xb8001520:0x001a0d00, 0x00140a00, 0x00160b00, 0x00120900- S) ]! L( z! B
0xb8001530:0x001c0e00, 0x001e0f00, 0x001c0e00, 0x001e0f00
, V8 b5 d% l' V9 [ C8 @( E0xb8001540:0x001e0f00, 0x001a0d00, 0x001c0e00, 0x001a0d00
- q: V h$ R* U5 |9 C5 H0xb8001550:0x00100800, 0x00140a00, 0x00100800, 0x00140a00
, |3 ~# Y' ]! o$ g0xb8001560:0x00160b00, 0x00120900, 0x00140a00, 0x00100800
. {4 \# V: Z a& _$ ]$ [0xb8001570:0x001a0d00, 0x001a0d00, 0x00180c00, 0x001c0e00 Y) y+ W. v+ n2 h9 a t
0xb8001580:0x001c0e00, 0x00180c00, 0x001a0d00, 0x00180c00
, g/ F" F5 @' [0xb8001590:0x00000000, 0x5110dbd9, 0xa9a95656, 0x5352b5b5
6 T4 q; c q4 G2 B! k4 E0xb80015a0:0x4145dcdc, 0x00000000, 0x00000000, 0x00000000
! V) r% V& y% U* M& O; OII: PLL is set by SW... OK! G& N [& W: u
II: Flash... OK
' _& w% q& {7 o' N- d$ w/ QII: Stack @ 0x801ffff8' S9 ~, c- N7 I/ H* J& g
II: Starting U-Boot...
- b2 v( a% }! v& h0 C; U$ e7 Y; pII: Inflating U-Boot (0x80000040 -> 0x87c00000)...
. ]) ? _4 ~/ P0 z4 u# W9 uEE: decompress failed: 1
2 F8 x; H+ E# U) _6 Q以下是状态2板了log:
; \# P2 B. u& {) \SoC preloader 1.0.0.r1422.lzma (Wed Nov 13 14:32:57 CST 2013)' d9 |' X2 N* {4 I$ T2 C
II: Stack @ 0x9fc1fd18 (parameter 736B)
, c n2 G, N0 U; K8 jII: Console... OK
. B" R+ ~) I; f% {& S& a: V ISetting DTR6 P; F# q" k% o6 z3 u
II: DRAM is set by software calibration... PASSED& u% E2 j# H% I/ `$ B/ q2 I
2 g3 `4 e: p1 e# LDDRKODL(0xb800021c):0x00000410+ B+ [3 j) x! f5 G8 N# u, Y& T, t
MCR (0xb8001000):0x22041de0, 0x21220000, 0x54433830, 0x0404030f
4 i Z1 o2 C4 y+ E0 o4 dDTR2(0xb8001010):0x0630d000' D: Z: Q( ], {! z
PHY Registers(0xb8001500):5 ~( {4 Q, e" A! f9 A0 ?, a
0xb8001500:0x80000010, 0x0000007f, 0xa1a00000, 0xffffffff( x# o O9 n( B6 A# q7 ^
0xb8001510:0x00120900, 0x00140a00, 0x00120900, 0x00160b00. V* S) H+ u! R8 j6 H& N1 b! i# i
0xb8001520:0x00140a00, 0x00120900, 0x00140a00, 0x001008009 T0 Z& [' n% P! v, ^
0xb8001530:0x00180c00, 0x001a0d00, 0x00180c00, 0x001a0d00- a9 J) Q! n) r- @# ~/ J& s
0xb8001540:0x001a0d00, 0x00180c00, 0x001a0d00, 0x00180c009 F: @4 s) L) t7 X- J4 M$ U. o
0xb8001550:0x00120900, 0x00160b00, 0x00120900, 0x00140a00
2 [1 n7 z+ M9 \4 ^, O) m+ U& ~0xb8001560:0x00140a00, 0x00140a00, 0x00120900, 0x00100800
: M1 m* D2 w7 y" u0xb8001570:0x001c0e00, 0x001c0e00, 0x00180c00, 0x001c0e005 e4 ?, [! u. F9 [2 o
0xb8001580:0x001a0d00, 0x00180c00, 0x001a0d00, 0x00180c00
; C6 p! G3 {8 ^( h0xb8001590:0x00000000, 0x5adad2d2, 0x24207574, 0x5a5adada
$ i3 F. P2 } m' w+ s$ z0xb80015a0:0x8d0da7a5, 0x00000000, 0x00000000, 0x00000000, ]2 V, n% b* @. I; L: C; V$ S- n
II: PLL is set by SW... OK* I- p9 l0 G8 b$ @; I8 B
II: Flash... OK0 Q/ X+ Z$ I/ y- w+ V# u$ z Y
II: Stack @ 0x801ffff87 O, j, v3 ~) ^8 @$ t- J
II: Starting U-Boot...
; F7 @* d) h# ?% l; SII: Inflating U-Boot (0x80000040 -> 0x87c00000)... OK
! Q. K" o4 Q3 w- U+ T ^# q4 j; NII: Starting U-Boot... $ N/ f: |% O! t; Q& t
( ]# l, H2 f0 h, A! g6 w
- _$ l0 e! [- L
U-Boot 2011.12.NA (Nov 13 2013 - 14:33:03)3 h# } H3 r. R
: h0 e! v* W9 @" L! P2 UBoard: LUNA
3 j& V2 m3 c# RCPU: RLX5281 600.00 MHz, DSP: RLX5181 500.00 MHz, , DDR3 300MHz, LX:200.00 MHz : G$ H2 E5 ]* {5 d9 S- n8 K
DRAM: 128 MB1 Y4 s, L2 S; I' E: [! ? K: c' Q
enter nand_init
# G& T9 P! V( D5 y# @9 y# o& s7 Lboard_nand_init()
# o O- U- n1 [; O3 `& u! lparameters at 0x00001212
" c! Y" f! O" p7 c$ k3 Dparameters.read at 0x9fc00550
8 m4 x [: q% Sparameters.write at 0x9fc03308- E+ A( h! N) v7 d
parameters.bbt at 0x9fc1feac% \. m% Y0 B2 r# r6 N( m
uboot- read nand flash info from SRAM) g1 p3 _8 C \- ^: Z8 W
flash_info list
* P3 }; W$ k6 U( }flash_info.num_block : 1024
" \4 a" c' [% b {flash_info.num_page_per_block : 64
0 ?* J( o2 ~# w6 eflash_info.page_per_chunk : 1
# {" _$ M$ _# b9 qflash_info.bbi_dma_offset : 2000- }/ O2 D9 d5 O9 e/ Q6 O# z$ m
flash_info.bbi_raw_offset : 20489 X2 s! O( [6 Y/ B: N% t" q. K
flash_info.bbi_swap_offset : 23
+ b- e% ~. K7 {+ v d1 w _flash_info.page_size : 2048. C9 x4 `5 h# n9 o
chunk size : 2048. r; z! S1 K* H# I+ `% u: s4 {
flash_info.addr_cycles : 4 r) u& H6 P# I6 T/ P
pblr_start_block : 1
' b `$ z7 @8 \0 Dnum_pblr_block : 37 [6 @9 o; `5 I+ [8 e
parameters.curr_ver is a
) ]. H0 C: ?* n, B# J8 C! d& Tparameters.plr_num_chunk is 29
6 O1 \: C, \( i/ uparameters.blr_num_chunk is 45
' z4 x( R f' H2 r7 Q' y1 Tparameters.end_pblr_block is 4
0 |9 f$ |/ i' H* @rtk_nand_read_id id_chain is 9580f192* f1 h- _% E S
nand: Manufacture ID=0x92, Chip ID=0xf1, 3thID=0x80, 4thID=0x95, 5thID=0x40, 6thID=0xc0
$ h3 k' J- [# R/ Bthis->pagemask is 655350 U5 m3 e% X7 k5 F
this->chip_shift is 27
& J* D3 `* H% B; ?2 ?+ nparameters.bbt_valid is 1
4 E' S; ^) |4 v4 Dcreate_logical_skip_bbt5 D0 p$ y* C, t+ n1 x" [5 j* e
last skip_block 1024; N3 d6 F6 ~" Z6 }
nand.c nand_init_chip mtd size is 877bfeac
! K7 @( A0 ~. X0 v1 G* `128 MiB( }2 k3 c& z0 q7 m
Loading 131072B env. variables from offset 0xc00001 z1 ~2 J! @/ d, Q* `% h1 M! X
Unknown command 'sf' - try 'help'
3 f7 V# {# y9 L* }" A( Y, _Net: LUNA GMAC 5 Z& S0 B* d: S3 Y' t
Warning: eth device name has a space!0 ?& T9 t9 o( X& F8 E" v' k% H _
+ V8 ~" y+ K! z6 O0 Z" A
Hit space key to stop autoboot: 0
1 [: Y! X& r6 c2 F' i6 L7 C% E# b l) {; S, `( {% s* \( S
3 m! g" o5 ~- U4 B3 S$ i+ S
ACTIVE IMAGE 0 (tryactive=2 sw_commit=0)
" D7 ]: i6 q5 G' R; @
Z% D& ^! V' jreset pcie0
* e" s# H) i: e D* k$ ^reset pcie17 i3 ] f {# ~
- n/ Z. G( X b) K1 B. oNAND read: device 0 offset 0x100000, size 0x380000
& R5 \, u2 L. e1 H" j 3670016 bytes read: OK
4 t+ J- `: Q; s0 C## Booting kernel from Legacy Image at 82000000 ...2 j& X& `6 V7 }' Q2 ?% V2 | ]- e
Image Name: Linux-2.6.30/ [9 `+ i0 ~/ i: K+ a5 p9 E
Created: 2013-11-14 2:56:37 UTC( e4 M5 ^: F# N( U8 k& c( y7 a
Image Type: MIPS Linux Kernel Image (lzma compressed)
* x' t8 R6 ~: R9 v2 h8 V& L Data Size: 1791872 Bytes = 1.7 MB
7 P. Y6 r4 o0 e Load Address: 80000000
. n, s9 g& g7 s& t* x Entry Point: 80000000
7 y0 t- x1 v7 ~6 i1 Z Verifying Checksum ... Bad Data CRC" k; u! H. I% r& p: X
ERROR: can't get kernel image!6 z, y" {4 l6 h1 @7 S* M
5VT-2510# , B g( [8 J# o5 L
请问大家这是什么问题呢? |
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