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换了nandflash后和加焊DDR后有两种状态，但是板子都没有启动成功，串口有打印。1 e, P3 a5 E D$ b) I! ?& {; A# f
以下是状态1的log:
O: M/ u, U B. j# y, zSoC preloader 1.0.0.r1422.lzma (Wed Nov 13 14:32:57 CST 2013)/ n8 L- }& |# @/ u3 l1 C
II: Stack @ 0x9fc1fd18 (parameter 736B)
' \$ s" o& }! K) j, e: ?/ v" ]& gII: Console... OK
: r4 f, L2 N( T# CSetting DTR
% l: ~7 f/ q. D5 H5 q2 gII: DRAM is set by software calibration... PASSED3 v0 [0 C$ ?, l: U. |4 w
0 g/ g& k C3 F4 @3 ?DDRKODL(0xb800021c):0x00000410" _; l b0 \5 R* a( `' T
MCR (0xb8001000):0x22041de0, 0x21220000, 0x54433830, 0x0404030f
2 ?- a" H/ ?' V4 xDTR2(0xb8001010):0x0630d000
8 J' I0 f* a4 n2 _. l( Q nPHY Registers(0xb8001500):) @8 _7 r; B* `' J3 n Y0 A; D7 e
0xb8001500:0x80000010, 0x0000007f, 0xa1a00000, 0xfdffffff; R! }4 t9 Y7 z2 J! k. V
0xb8001510:0x00140a00, 0x00180c00, 0x00140a00, 0x00180c00/ S1 p2 y0 l7 y3 U
0xb8001520:0x001a0d00, 0x00140a00, 0x00160b00, 0x00120900
, ]! I4 a" z& N6 Q1 t0xb8001530:0x001c0e00, 0x001e0f00, 0x001c0e00, 0x001e0f00
/ O. O1 B' w( _3 }0 Q, _0 J6 \; u0xb8001540:0x001e0f00, 0x001a0d00, 0x001c0e00, 0x001a0d00
0 `: Q5 V& ]" x6 V0xb8001550:0x00100800, 0x00140a00, 0x00100800, 0x00140a00# i3 y# E1 {+ Q" n' I0 B
0xb8001560:0x00160b00, 0x00120900, 0x00140a00, 0x00100800
2 N. j3 C! D: {0xb8001570:0x001a0d00, 0x001a0d00, 0x00180c00, 0x001c0e00
( m8 ^% g: ^- h! S( X( T! Z1 ~. G0xb8001580:0x001c0e00, 0x00180c00, 0x001a0d00, 0x00180c003 |. Y& [; y+ X5 r L9 g) Y
0xb8001590:0x00000000, 0x5110dbd9, 0xa9a95656, 0x5352b5b5+ k- {5 x% R9 J* ]
0xb80015a0:0x4145dcdc, 0x00000000, 0x00000000, 0x00000000$ c' c' c1 E* F9 r+ ]
II: PLL is set by SW... OK" d% ~, @# p+ b& c: `: c
II: Flash... OK
. l; i8 x8 K3 r! F. w- F8 KII: Stack @ 0x801ffff8
3 ~+ B1 K9 f3 a" zII: Starting U-Boot...# V" V! t s3 ` k0 {: i
II: Inflating U-Boot (0x80000040 -> 0x87c00000)...
4 X0 O9 v2 F, g, I8 MEE: decompress failed: 1/ K' ^! ~5 c) s. E
以下是状态2板了log:
; `9 I' t0 R/ R8 p; ]" z8 RSoC preloader 1.0.0.r1422.lzma (Wed Nov 13 14:32:57 CST 2013)# m; `; u+ w w" }% B8 d/ @: S
II: Stack @ 0x9fc1fd18 (parameter 736B)
& ?) G% Z8 j2 @9 { ?3 m- EII: Console... OK0 {, ~$ u4 {9 `2 Y# J; n9 ~
Setting DTR) l+ u2 d% ^2 }
II: DRAM is set by software calibration... PASSED, q, j7 Z# @( o, h+ d
4 w5 e; l% \5 G6 z$ m% n
DDRKODL(0xb800021c):0x00000410
! c2 S$ d4 _/ h& y3 Y: B: rMCR (0xb8001000):0x22041de0, 0x21220000, 0x54433830, 0x0404030f
6 ]2 y( L- a! y+ S% w' d) t# ADTR2(0xb8001010):0x0630d000
7 a; ]. I- M5 j, W0 Z" z" z2 GPHY Registers(0xb8001500):
+ y: G# I2 C& ^0xb8001500:0x80000010, 0x0000007f, 0xa1a00000, 0xffffffff
2 v7 R9 L8 K5 [) |; p$ @0xb8001510:0x00120900, 0x00140a00, 0x00120900, 0x00160b00
4 b0 W3 \! F, i; {9 K& T7 F0xb8001520:0x00140a00, 0x00120900, 0x00140a00, 0x00100800$ K9 K- i7 P q+ g i: P
0xb8001530:0x00180c00, 0x001a0d00, 0x00180c00, 0x001a0d00: L3 ?5 J; G6 `; m! B6 C' j, O
0xb8001540:0x001a0d00, 0x00180c00, 0x001a0d00, 0x00180c000 a" o2 C8 ?$ H6 u/ j( k1 ~
0xb8001550:0x00120900, 0x00160b00, 0x00120900, 0x00140a00
) B7 J# S) M! z2 H- p. r0xb8001560:0x00140a00, 0x00140a00, 0x00120900, 0x00100800. L. ~! t3 M( Q3 |0 [1 D$ k
0xb8001570:0x001c0e00, 0x001c0e00, 0x00180c00, 0x001c0e00
5 ?9 a2 ~" F% |8 R1 G0xb8001580:0x001a0d00, 0x00180c00, 0x001a0d00, 0x00180c00
% v4 ]8 g$ ?: R0xb8001590:0x00000000, 0x5adad2d2, 0x24207574, 0x5a5adada8 E% R: q3 {3 Y0 `" Y& r5 u' t2 |
0xb80015a0:0x8d0da7a5, 0x00000000, 0x00000000, 0x00000000# a7 h3 F. ~7 x, Q% m
II: PLL is set by SW... OK# Z; \( S, L& d
II: Flash... OK" y: C; o/ Y# w) |
II: Stack @ 0x801ffff86 T. R8 A* G4 i4 W! X. A
II: Starting U-Boot...
# B+ N+ L, _5 ~II: Inflating U-Boot (0x80000040 -> 0x87c00000)... OK
5 V8 c, T6 `: e4 g! RII: Starting U-Boot... : I5 F) ~6 Z, L1 x$ [" A) m
% H/ l( a% @5 B: O2 E6 Y
' v. V5 U, T3 ?- x9 Q1 u3 a PU-Boot 2011.12.NA (Nov 13 2013 - 14:33:03)$ }' M+ r5 @9 ]
" ~" Q5 V" a: m* ZBoard: LUNA
5 `& [! A" [ oCPU: RLX5281 600.00 MHz, DSP: RLX5181 500.00 MHz, , DDR3 300MHz, LX:200.00 MHz + z, g0 [4 y/ P+ ]+ s
DRAM: 128 MB5 w! [& } I5 S8 d: p* l# p
enter nand_init
+ C; B6 k& ], I4 x9 nboard_nand_init() }( t7 o! j' o
parameters at 0x00001212" j u) l. {. [! J! g5 i( {/ n
parameters.read at 0x9fc00550
) E6 \4 i5 `. V2 D' [2 nparameters.write at 0x9fc033085 X: H4 P; a; U7 Z$ p5 \
parameters.bbt at 0x9fc1feac" E6 N+ C4 o! \/ b( c
uboot- read nand flash info from SRAM" E( Q: q# M! I! z$ ^
flash_info list
M- Y8 w* w& H! Xflash_info.num_block : 1024
0 ~! P9 a. ]6 b# z n& P& @flash_info.num_page_per_block : 64% B/ q4 ]2 H7 f& Z( V$ }, C4 ?
flash_info.page_per_chunk : 1% h! V, Q1 R/ P8 q; i9 r) U: ?
flash_info.bbi_dma_offset : 2000
3 v: p7 Y" `' J0 k( [" S$ ~$ Wflash_info.bbi_raw_offset : 2048
9 W5 j$ `7 h& P- c3 ?flash_info.bbi_swap_offset : 23
! J- }5 v& v3 c) ~# O. }flash_info.page_size : 2048
4 C. n5 k( X4 D& rchunk size : 2048' r: x6 a9 C+ h$ R5 C! l
flash_info.addr_cycles : 48 |! ]# Z" |; j4 v; j% s
pblr_start_block : 1
# U+ V0 c# A. H: r" R: v& R# qnum_pblr_block : 38 I- q: @5 {4 M0 m( y+ B
parameters.curr_ver is a
0 C% V# f& H9 aparameters.plr_num_chunk is 29
6 Z G8 W% Q& m' wparameters.blr_num_chunk is 45
7 n4 ?6 D, r# o% `6 H% N" e: v( P6 \7 Jparameters.end_pblr_block is 4' D/ e3 H, d! J
rtk_nand_read_id id_chain is 9580f1927 P. o. t. K- i+ T- }
nand: Manufacture ID=0x92, Chip ID=0xf1, 3thID=0x80, 4thID=0x95, 5thID=0x40, 6thID=0xc0
! b2 z8 @+ ^/ ^1 Zthis->pagemask is 65535) A/ N% _) x/ p, }: y
this->chip_shift is 272 f; t+ D* l0 Z3 J
parameters.bbt_valid is 1
7 `$ U L% d# f& _5 q' n- J6 icreate_logical_skip_bbt
, s2 e! @) S7 N7 x$ E) xlast skip_block 1024
# m! D+ y5 p. Enand.c nand_init_chip mtd size is 877bfeac3 ?. K! d8 [+ R4 M. L& D" y
128 MiB
. b% d0 a, h8 @5 J. F0 `1 ^Loading 131072B env. variables from offset 0xc0000( Z6 W0 C: b9 J/ ^6 N3 G
Unknown command 'sf' - try 'help'
+ \8 u6 \/ A$ y4 u+ n/ @Net: LUNA GMAC
* t$ w0 d1 x: [9 z8 ]6 h8 aWarning: eth device name has a space!, V/ x9 P4 g5 S. W, E0 P# [
$ D; s6 |9 y9 C- H2 W, X2 D# K2 ^* W
Hit space key to stop autoboot: 0 8 [( V5 I6 L8 Q4 d* z
R U' X- ~- c# @( `& M2 v' s$ p2 R5 C) ]' z. s! L. ~( `- X: G
ACTIVE IMAGE 0 (tryactive=2 sw_commit=0)
# t% ] z4 a- v8 E! s- i
( ~4 k9 |& Y" u$ n$ areset pcie04 E3 V, c1 S2 A% y' ?
reset pcie1& i8 h/ w; {. M: }9 f
3 ^& m7 }% ^! t1 a$ W @% h5 hNAND read: device 0 offset 0x100000, size 0x380000* g' h7 x, x& z0 O$ I6 \8 B
3670016 bytes read: OK
* @3 U- f* o* z+ d% s- v: O) `) f## Booting kernel from Legacy Image at 82000000 ...
- a# v! _1 b0 h1 z% ]2 h* Z Image Name: Linux-2.6.30
& O3 e" V% F& V2 i+ E- Z$ J Created: 2013-11-14 2:56:37 UTC- [# ^& V, ?. E0 z, P7 P6 l
Image Type: MIPS Linux Kernel Image (lzma compressed)
! j, m, [. Q( @ \/ j Data Size: 1791872 Bytes = 1.7 MB
7 S; W- P' `6 n* @! B Load Address: 80000000
- h# C6 a) H3 l$ L& k: c Entry Point: 80000000
# @8 u+ K* Z$ L2 w3 e Verifying Checksum ... Bad Data CRC: E: | _. O2 F% @, U
ERROR: can't get kernel image!5 o$ }7 `. G1 C* q( F. G0 z3 c4 q
5VT-2510# ; k3 O2 z% [/ P) t2 Z. T
请问大家这是什么问题呢？ |
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发表于 2013-11-28 17:40
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