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reg state;
* w4 F* [# M, u+ cassign sram_cs = 1'b0;/ O0 D0 _4 }3 Q
assign sram_data =we?8'hz:wirte_data;: i: C" w# b1 p8 A( L
always @(posedge clk or negedge rst)& p- ]# |. B, _& E
if(!rst)
/ c7 y& L |: ] N& s$ l clk <= 1'b1;
; g8 z; F( Z: s7 l& helse7 {7 {& v( U; e$ k
state <= ~state;
3 V: v$ E C4 I% y4 Z# i8 S" S: ~& K% e3 s
always @(posedge clk or negedge rst)) x$ A" u. X/ s. c: _! y/ ?
if(!rst)9 @% K/ s) q/ U* X. o, F
begin
% E: [; H6 e3 H0 R; r# h2 R end( O5 h7 V2 T; N+ Q
else
$ q7 r p% Z# r' F begin6 C2 x, ]# M ]/ ~4 D! K
if(state ) //读,
. n$ ]# d# N$ x9 l6 b3 Y5 E+ { begin: n2 ^* m6 O) F$ r) ]7 ~
sram_addr <= read_addr;
7 J1 R. g2 J8 ?' c; H sram_we <= 1'b1;
* G: f$ @! h6 k$ H) ^. `5 t$ I sram_oe <= 1'b1;/ o5 z4 l9 g4 E5 Y
end6 ^2 d: o. y8 V! `5 q' n S
else
3 m" `; ^# O, m5 m# C' s begin //写+ p% o, y% P' U- U8 z! ]. j) g* `: w
read_data <=sram_data
9 K4 d9 s# c! O2 j& J: @ sram_addr <= write_addr;0 X8 \2 R$ w. O( @- g( f+ n
write_data <= video_data;
* W. p6 o& ^. D2 R# q- N. m sram_we <= 1'b0;
+ n* w- b5 ^9 ` sram_oe <= 1'b0; H+ ^7 Z4 H6 S
end! m( i4 D( V9 Q
end
# b$ U8 W% i% h- x: b! f; h
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5 }) T3 e9 |0 J" v* N6 n: K9 j
. y$ c( @4 m7 [ _
endmodule |
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