|
|
EDA365欢迎您登录！
您需要 登录 才可以下载或查看，没有帐号？注册
x
http://www.orcad.nl/patches/Hotfix_SPB16.50.049_wint_1of1.exe! g$ Q+ H) F0 E
, G/ k$ b L" \: v5 s3 |
4 y9 C* c% l1 C' b
4 E! }7 t& K, U$ F# K- W+ bDATE: 10-31-2013 HOTFIX VERSION: 049' ?6 N& F* Z0 E6 b1 ?, P7 b
/ M8 A0 o- O+ C1 o. d) f
=================================================================================================================================== {9 r' p$ ^8 r( |
: o( C+ E3 P+ C8 C) [' w
CCRID PRODUCT PRODUCTLEVEL2 TITLE0 u0 g* F8 R3 O6 D
6 m8 \' A9 U; p; R+ b===================================================================================================================================7 p; _2 I( j* X. h4 c
$ k% \( g) c- p6 @/ z$ r5 L1 K
1188193 concept_HDL CHECKPLUS CheckPlus not recognizing PIN as a base object.( N. b, z; r* f) L
$ z8 N% [ K/ ?1190210 F2B BOM The bomhdl.exe fails - MFC Application has Stopped Working
7 i8 _3 ]9 ^8 E0 F
$ f Z- V5 o" t: @; c: O$ Y1190782 FSP FPGA_SUPPORT Support for Altera > 5SGXEA9N2F45 device.7 Y9 C% E+ M7 K8 v6 y! r0 {: @- G
8 X+ i& k6 m3 b' `
1192916 allegro_EDITOR EDIT_ETCH Wrong static phase values are shown in the dynamic timing meter for certain Diff pairs compared to CM.
+ D! [/ |6 v2 D/ H" t
( j6 x3 `8 l8 a1195309 GRE CORE GRE crashing during Plan Spatial.
) ^7 g, C3 x8 a. A+ t( u
) J/ i* y# j% o2 z/ E' y1195744 APD EDIT_ETCH Diff_Pair routing fails on certain Uvias in the pair.4 Q4 [# T- N# |+ O. g
" t& ~1 S% w& a. j
1198521 CONCEPT_HDL OTHER cadence DEHDL issue - Note for Hotfix_SPB16.60.016_wint_1of11 |# ]- d" e( O* }9 ^0 {: t& ]+ |
! i" A) V" F5 z+ \( G
|
|
/1 
发表于 2013-11-18 09:21
收藏
淘帖
支持！
反对！
楼主
