|
|
2#

楼主 |
发表于 2013-10-29 17:11
|
只看该作者
2 d! C. D: m* v( iDATE: 10-25-2013 HOTFIX VERSION: 018
X3 ?, t0 S8 r* a. m===================================================================================================================================
* U1 v! f$ Q1 B! U4 ?CCRID PRODUCT PRODUCTLEVEL2 TITLE
. ^$ \/ d+ n/ Q3 \; j1 ~===================================================================================================================================
+ `6 w5 L! z1 b1118303 CONCEPT_HDL CONSTRAINT_MGR can not prdefinedefault units in HDL1 L. p" d- P' k" {8 ]/ A; c
1174901 ALLEGRO_EDITOR GRAPHICS Spurious odd lines are shown in shapesand text that are not part of the design with opengl
" V2 x: E0 ~6 R* F; y3 G1176990 CONCEPT_HDL OTHER DEHDL BOM tooldoesn縯 see similar names.
2 D( M6 s: H6 k1179665 GRE CORE Plan TopologicalCrashes after around 8 hours of routing.
2 @. |* C4 S" _9 d! T' n1188193 CONCEPT_HDL CHECKPLUS CheckPlus notrecognizing PIN as a base object.
' P! N9 ~0 @8 H# a1189100 SCM OTHER Replace part inSCM using ADW as library fails' {' Q* b+ T+ D7 k$ t$ [
1189507 SCM SCHGEN ERROR(SPCOCN-2009): Package error after second schgen run with Preservemode.; k, Z) w2 _9 q; r: L! T3 I& n
1192391 CONSTRAINT_MGR CONCEPT_HDL Restore from definition deletes localobjects in other blocks) i2 g4 |. p& q. q
1194597 FSP OTHER Pin definitionproblem
$ T% ^& Q# J, [2 V1195202 SIP_LAYOUT LEFDEF_IF Cannot add .leffiles in IC Library Manager. Getting warning message WARNING(SPMHLD-52)
( \" }9 h! N/ C' [# u: y1195309 GRE CORE GRE crashingduring Plan Spatial.
; @, h' [. @0 j4 Y0 ], Y0 }1197262 ALLEGRO_EDITOR MANUFACT Angular Dimension created in symbol isplaced w.r.t. board origin and angle is blank
8 M: |. m" w( s8 l1 K, m# }$ k1198521 CONCEPT_HDL OTHER Cadence DEHDLissue - Note for Hotfix_SPB16.60.016_wint_1of1
. b# `! p( a4 D1199219 ALLEGRO_EDITOR INTERFACES Question on STEP Model export which usesPLACE_BOUND layer for any symbols that do not have STEP model mapped
- K/ x; k" M# j) d8 V0 |0 Y1 P1199235 ALLEGRO_EDITOR SCHEM_FTB capture's behavior is redundant whilecreating pcb editor netlist- U. d: s5 A5 H% U
1199323 GRE IFP_INTERACTIVE Crash whenimporting logic! |/ _4 t! z1 G0 P
1199368 SIP_LAYOUT DIE_EDITOR Refresh of dieabstract in die editor with this design takes over two hours
, x, {1 G( Y7 r$ E p* p! N1199760 ALLEGRO_EDITOR DATABASE Allegr won't display Soldermask Toplayer |
|