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本帖最后由 pzt648485640 于 2013-10-16 22:11 编辑
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下载地址：http://pan.baidu.com/s/1kmHkL5 m7 V4 {& l0 p4 t4 E# z/ z# N
5 O9 P3 r& ?1 [百度网盘 在hotfix附录里. i5 v( b- F" t4 d4 p! M! Z
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2 c5 F1 ]. o/ C* kDATE: 10-10-2013 HOTFIX VERSION: 017
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( I* s1 `0 Y0 p l. g===================================================================================================================================( _# g V0 p) D8 q) u& u7 a$ c8 X& J2 z
1 W+ v: g7 h+ B% S3 hCCRID PRODUCT PRODUCTLEVEL2 TITLE( j5 l7 Y3 X2 ]( T
6 E! R4 X3 u" e$ S4 Y5 k/ u$ Y8 I===================================================================================================================================0 {+ G) m, ]6 T+ r# t& [7 @3 m
: U7 w& g! e0 D735992 ADW LIB_FLOW Create Test Schematic does not use the correct package type+ `! j; }* j: T7 W# r; m& K* M
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1121403 FSP PROCESS "Assign to Pin" not getting obeyed by Synthesis.
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1141844 RF_PCB DISCRETE_LIBX_2A ADS Lib Translation Pin Soldermask/Pastemask missing5 i% h7 ^! Y5 T5 D" V$ H, k) F
9 y9 L1 B3 l# U4 E1 W1169269 allegro_EDITOR DRAFTING Dimension placed on package symbol moves to different place when it is placed on brd file.: Q c4 J, g( `0 Z8 N
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1170488 ALLEGRO_EDITOR MANUFACT Dimension text(on .psm) move to different position, when it is placed on .brd.
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7 q* T6 H+ Q: a2 u* B1173345 CIS CRYSTAL_REPORTS Crystal Report - Display Parameter dialog for export option& P) s4 J; t6 f4 h) N
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1181759 SCM LVS SCM Crash when doing update all that executing import physical command.% G5 s4 [; x3 v" j
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1182499 ALLEGRO_EDITOR OTHER Step export to include through hole padstacks (all pins and via) drill.
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$ O1 j9 v: m# G* ~3 E' l1184682 concept_HDL CONSTRAINT_MGR Net Constraint not transferring to layout from schematic9 C3 G1 s0 H$ W4 ~6 T3 \
$ Z2 m+ ^5 R2 }; h, G& v! m v1185524 F2B PACKAGERXL Enhancement User would like notification of pack_short in pxl.log
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1185902 ALLEGRO_EDITOR SHAPE Update shapes dont clear some diffpairs in HF152 _1 a/ `- z5 y0 |2 A
8 }2 H1 O& l. Y5 U; Q0 [1186152 ADW LRM Part Status for Deleted Part in LRM is distinguished with other part status4 g: r Z, g; Q, s" W' q6 {' v
2 [( ?: q6 o; `! U5 C T' C- ^+ N# G1186387 ALLEGRO_EDITOR OTHER DXF cannot catch offset value in s047 hotfix.% h( Y2 L+ P2 d
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1186805 ALLEGRO_EDITOR OTHER Exported STEP file missing multiple components placed on board
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& d9 [! P& |' e$ M1186818 ALLEGRO_EDITOR COLOR Custom color not retained during dehilight6 C9 I4 ~- }0 X/ i% m3 D- r" i- |; {
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1187196 CONCEPT_HDL CORE TOC not populating (page 1)8 U4 M6 K# V9 F
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1187667 F2B PACKAGERXL Existing hard LOCATION property in drawing was left unchanged8 E+ C# o- ?; ]- t& k
/ a) e. d8 I# D% h3 n ?4 f1188264 ALLEGRO_EDITOR MODULES Some fillets not regenerated in module created from a board file.
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1190144 ALLEGRO_EDITOR OTHER Fillet shape is not genrated around cline
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+ M% g; L" H) }1190210 F2B BOM The bomhdl.exe fails - MFC Application has Stopped Working
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9 T Z, i# J; F9 m4 _0 [6 `% k1190618 ALLEGRO_EDITOR GRAPHICS Enhancement for Visible grid
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1 c! T2 G; e( c* k% G0 p" b2 D1190813 ALLEGRO_EDITOR INTERFACES 3rd party netlist file in TEL format fails syntax check but imports successfully
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1190895 ALLEGRO_EDITOR EDIT_ETCH Route delay meter displays violation when sliding diff pair1 {" C7 i. j, Z b! u: p) h
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1190908 F2B OTHER DE-HDL aborts if dummy net is being cross-probed from PCB Editor0 n4 A; P( b, A7 s) N2 \
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1190990 CONCEPT_HDL CORE Mismatch in .csa and .csb files3 A5 E- t2 p2 o' V6 B
4 k( B1 G) O- J1191008 CONCEPT_HDL CORE Remove Binary File feature doesn't work4 n% q* h- \4 d$ Q' n w
( g! G% {( ^/ n, }* O: ^1191514 SCM PACKAGER Packaging error PKG-100) o: I! B" S" d* P& D' \* I* [
2 J) }+ x7 e/ z/ `. Q# r0 N1191517 ALLEGRO_EDITOR DRAFTING Metric +tolerance when using dual dimensions is not displayed correctly* b: K# A7 w# s/ W- V
# F6 ?4 `# O' u" M1192561 ALLEGRO_EDITOR GRAPHICS Padstack with offset is not showing correctly in the 3D Viewer.
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1192916 ALLEGRO_EDITOR EDIT_ETCH Wrong static phase values are shown in the dynamic timing meter for certain Diff pairs compared to CM.
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$ F9 H; d+ w' m$ f1194197 ALLEGRO_EDITOR OTHER Step export to include through hole padstacks., a5 E( u8 Q7 q( E' J. [1 e0 H0 S
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1194239 Pspice DEHDL Associate Model does not launch from DE-HDL8 _" Y/ g) X2 C7 C8 z6 ^
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1194736 PSPICE SIMULATOR Design causes RPC failure when run consectively. G9 \( t3 i, P: [5 ]* J6 M0 D. Q
) Z# n4 ]6 b1 t# W0 Q1195139 ALLEGRO_EDITOR PLACEMENT Components disappears from board file once they moved6 E1 j1 Q) l2 C. W2 Y
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发表于 2013-10-15 10:33
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