|
|
EDA365欢迎您登录！
您需要 登录 才可以下载或查看，没有帐号？注册
x
本帖最后由 pzt648485640 于 2013-10-16 22:11 编辑
5 C* j3 \4 A& w F
" V; |- J+ n6 r, d5 d& s6 x下载地址：http://pan.baidu.com/s/1kmHkL
# u/ F6 g9 E( i, Y2 |& f& c$ S$ @9 n6 j' ^0 c8 X+ n; o4 P
百度网盘 在hotfix附录里: Q) I9 V( C7 m+ T5 D8 D9 @
1 w, B& d: J( U2 f% J4 T
$ ]3 [ N" e% X& U
: Y/ S" S0 G9 q9 KDATE: 10-10-2013 HOTFIX VERSION: 017$ p/ [' |6 D( {$ W
/ p7 W. ^' c1 W% b8 q" Z
===================================================================================================================================
: [. ]- {; @) `" O3 N2 i: Q0 G2 f' a& h. G# f: H/ m8 u- h7 y& B' [; v
CCRID PRODUCT PRODUCTLEVEL2 TITLE. b. v0 |9 t# g- p9 B
7 F# n( Y5 H0 E" |9 y0 C% B9 ^1 f===================================================================================================================================, j* Y7 O% Q/ M7 k# I
; \' _, F$ }' @) X7 [6 K
735992 ADW LIB_FLOW Create Test Schematic does not use the correct package type
: g8 i/ O6 |- @& a- R' X2 ?9 q- [
0 e# M% J- [3 y& ?: n1121403 FSP PROCESS "Assign to Pin" not getting obeyed by Synthesis.
' L1 T" e3 ~ Q; c4 @ d) e
0 _" @1 K( T% I1141844 RF_PCB DISCRETE_LIBX_2A ADS Lib Translation Pin Soldermask/Pastemask missing( H0 \" P$ Q* ~, N! M5 \
" ?# P4 R9 g$ }; M7 ? g5 I" T1169269 allegro_EDITOR DRAFTING Dimension placed on package symbol moves to different place when it is placed on brd file., h2 N. l+ U$ ~- l6 w0 V I
7 O7 e# L$ h' ~+ {1170488 ALLEGRO_EDITOR MANUFACT Dimension text(on .psm) move to different position, when it is placed on .brd.0 I% b- p! q2 X; Z" J' r2 u
3 [3 Z' `8 d+ @ Z4 y1173345 CIS CRYSTAL_REPORTS Crystal Report - Display Parameter dialog for export option
% V; p& k' w: ]% q9 l3 i- c, C5 |# W# R3 `6 E& u& `. O
1181759 SCM LVS SCM Crash when doing update all that executing import physical command.
3 `1 D' S- \7 E
5 w# C0 S" c, e H' [# t* }1182499 ALLEGRO_EDITOR OTHER Step export to include through hole padstacks (all pins and via) drill.9 {$ Q8 [7 E: C3 F
& ?+ a, v, @; y* R
1184682 concept_HDL CONSTRAINT_MGR Net Constraint not transferring to layout from schematic2 u) _$ D4 o- n/ }# t
: F$ v% y: Z! P' T2 ?
1185524 F2B PACKAGERXL Enhancement User would like notification of pack_short in pxl.log$ e; l! F B b' O6 ^- u
3 _# E1 a) Y% e* i {, ~ ?0 y' h/ n
1185902 ALLEGRO_EDITOR SHAPE Update shapes dont clear some diffpairs in HF15
) M9 z3 {- ~/ L9 w; k' T1 b) R. o: _6 R% f ^/ k: u0 O% F
1186152 ADW LRM Part Status for Deleted Part in LRM is distinguished with other part status# A/ D( n6 M' M1 h) o) r- Y/ `' F
$ F: }& m5 s$ g7 C1186387 ALLEGRO_EDITOR OTHER DXF cannot catch offset value in s047 hotfix.
! ?! e! j9 O3 I9 ?3 `
$ h/ C. R1 X! p6 h* H2 U1186805 ALLEGRO_EDITOR OTHER Exported STEP file missing multiple components placed on board
' L& A) W1 }/ P" K3 i* n
4 ~/ n" \2 c- Y3 P, J7 p, y9 V' K# E1186818 ALLEGRO_EDITOR COLOR Custom color not retained during dehilight2 @- c! O; E$ h( p' H
5 z8 R1 D9 T6 c$ C
1187196 CONCEPT_HDL CORE TOC not populating (page 1)- T3 C3 `+ \$ Q: W7 O1 ^8 g* p
& \/ m* B' F! ~7 M+ E; c( W1 M" ?+ T1187667 F2B PACKAGERXL Existing hard LOCATION property in drawing was left unchanged
; h. g* s0 W; s5 S1 |3 q' b& q4 n" C. @8 y
1188264 ALLEGRO_EDITOR MODULES Some fillets not regenerated in module created from a board file.$ Z4 h7 H3 X) S2 {
9 T. M6 c- D9 H! }9 U* `1190144 ALLEGRO_EDITOR OTHER Fillet shape is not genrated around cline& @( Q% \ O' z4 K
8 B$ n' W9 K; U1 g8 R9 B
1190210 F2B BOM The bomhdl.exe fails - MFC Application has Stopped Working
Y {+ F7 y( r. M% A# i& M1 M2 U! k$ H: v
1190618 ALLEGRO_EDITOR GRAPHICS Enhancement for Visible grid' w! t5 z8 X, D$ M6 O
) @( ^3 q& n( o4 q8 K
1190813 ALLEGRO_EDITOR INTERFACES 3rd party netlist file in TEL format fails syntax check but imports successfully( E# N4 [+ t7 |6 g
* k& V& n4 w- ^# V# A( i8 H
1190895 ALLEGRO_EDITOR EDIT_ETCH Route delay meter displays violation when sliding diff pair
7 f# p% |! p$ X/ }) A6 M B" a; u7 ~. H& `! G. e- w
1190908 F2B OTHER DE-HDL aborts if dummy net is being cross-probed from PCB Editor
0 c/ H N4 s9 |/ p, n# [6 b1 m- F/ j" R
1190990 CONCEPT_HDL CORE Mismatch in .csa and .csb files
$ c1 N1 g' @3 x* u9 d$ }- R4 Q8 c1 a C7 I
1191008 CONCEPT_HDL CORE Remove Binary File feature doesn't work
8 D+ t2 T/ c- _- K( C0 i$ h6 ^' l1 J* g, j- y, a
1191514 SCM PACKAGER Packaging error PKG-100
- h4 u+ |! V) }! r
: N, r. K6 A) D) G1191517 ALLEGRO_EDITOR DRAFTING Metric +tolerance when using dual dimensions is not displayed correctly- L* _; y) w* q/ d4 J% ^# g
9 b1 B( Y( B6 P2 q4 p2 e1192561 ALLEGRO_EDITOR GRAPHICS Padstack with offset is not showing correctly in the 3D Viewer.
3 w- F7 f( m4 ?# |" e$ j0 Z7 b+ _# E& z
1192916 ALLEGRO_EDITOR EDIT_ETCH Wrong static phase values are shown in the dynamic timing meter for certain Diff pairs compared to CM.
+ M7 W& X1 b9 |* W( d3 O2 @
/ b0 d4 X# Z K; j) A! q" S( \! q1194197 ALLEGRO_EDITOR OTHER Step export to include through hole padstacks.8 Y" q3 k2 l. i0 m, A
& N/ Z8 S/ p9 W0 y5 n% }7 o
1194239 Pspice DEHDL Associate Model does not launch from DE-HDL" i" f. |/ ^. p2 U
7 c5 T4 `3 }1 |# x8 Y
1194736 PSPICE SIMULATOR Design causes RPC failure when run consectively
" e6 I5 _# m4 t% t! _2 H$ W4 V' b) `$ A" U/ X
1195139 ALLEGRO_EDITOR PLACEMENT Components disappears from board file once they moved3 @" a9 h5 Y& l+ ^$ q9 Q; `
|
|
/1 
发表于 2013-10-15 10:33
收藏
淘帖
支持！
反对！
