Cadence SPB OrCAD 16.60.016 Hotfix

suiwinder

cadence SPB orcad 16.60.016 Hotfix | 853 mb
DATE: 09-27-2013   HOTFIX VERSION: 016

===================================================================================================================================
& `* u  R( h# l2 E4 C
& N) p+ N7 @$ I/ N% y+ @5 w* a/ wCCRID   PRODUCT        PRODUCTLEVEL2   TITLE

; c, O2 `; b0 i$ ~5 ?* n6 e===================================================================================================================================

+ R5 H  L0 \; [" [, l7 N548538  CAPTURE        NETLIST_allegro  Enhancement:Include mechanical parts in Allegro netlist
4 S" L  k! }- a6 W* L- G
1076579 CAPTURE        GENERAL          Display value only if value exists

% C7 u  e/ _* E( M6 ~8 [1083904 FSP            GUI              Need Filter in Change FPGA dialog to select desire FPGA from the long list.

0 I7 L  i, S1 h+ f1089313 ALLEGRO_EDITOR INTERFACES       Allegro Export PDF requires similar setup options as DE-HDL Export PDF for layer visibility

1095728 ALLEGRO_EDITOR EDIT_ETCH        Slide to grab adjacent elements when extend selection is enabled

* Y9 L6 S( z8 U# ~# d1102698 SIG_INTEGRITY  ASSIGN_TOPOLOGY  ECset will map on single ended nets but fails when the two nets are define as a diff pair.
& t" J' Q+ t1 [; f* }  a7 |
1104071 SIG_INTEGRITY  REPORTS          Shape Parasitic value changes for bottom shape for changes in top shape
) c/ K# C7 h+ I, U0 a, U& T
1117731 FSP            POWER_MAPPING    Ability to sort in Power Regulator forms
) x8 C! f$ w" s0 C
/ r5 _+ Z3 f$ ^1 j# X$ _/ @! Y6 x1121539 FSP            CONFIG_SETTINGS  Cannot configure special FPGA pins (temperature diodes)

: Y- l1 h3 l) f( }* l: n1122721 FSP            MODEL_EDITOR     Partial copy-paste overwrites the complete cell in XML Editor
4 Z$ D) N" {# @. F
1123238 FSP            TERMINATIONS     Report functionality for terminations defined in the complete design.

1123364 FSP            GUI              Clicking on column header should sort the column.
! @5 I% e( _$ o  k3 U
* r; T. Z5 s0 _1 Q% ?! Q1123403 FSP            EXTERNAL_PORTS   Improper checkbox selection for 緿o Not Connect?or 縀xternal Port?column
1 ?7 l2 \7 i1 Z# N5 }1 A( B
1125611 concept_HDL    OTHER            display unconnected pin in schematic pdf.

1129871 ALLEGRO_EDITOR INTERACTIV       Wire Profile Editor can't read mcmmat.dat in working directory.
5 a2 R2 m9 X6 }- a
1133688 ALLEGRO_EDITOR GRAPHICS         Enhancement request to enable 3D Viewer to show STEP model from .dra file.
! a* }( a. P  ?/ G
1141747 ALLEGRO_EDITOR GRAPHICS         3D view dooesnot displays height if step_unsupported_prototype variable set
6 K+ D5 c4 P: }
1142215 SIG_INTEGRITY  SIMULATION       PULSE_PARAM set on DiffPair wasn't used for designlink simulation.
# U; v5 o9 h8 B4 G, j% ]0 L& g
5 q+ |+ J/ C$ w: k' C1 ~( x1142798 ALLEGRO_EDITOR INTERFACES       Step file output is incorrect in step viewer when composed of arcs and line.
, N7 _8 s, Y6 o2 j
1142894 FSP            GUI              Ability to RMB on a header and select `Hide Column?
4 Y( D2 k+ E9 a5 _; \# w1142940 FSP            EXTERNAL_PORTS   Issue with checking/unchecking "Do not connect" and "External port" cells
7 [, S/ q+ q, k6 r+ D0 ^
1142949 CONCEPT_HDL    skill            Usage of "Preferences > License Settings?in FSP

; ~$ k- p8 ]! k- _7 f& C2 R1143091 SIP_LAYOUT     SYMB_EDIT_APPMOD symed:  When AddPins is used to add pins to a co-design die, those pins are not output as bumps in the die abstract

$ a* A7 J& q( W/ _6 U) f1144371 CONCEPT_HDL    COMP_BROWSER     Component Browser search results are inaccurate
& S; o2 y# p% V7 N5 ~0 c; X
1145033 ALLEGRO_EDITOR PLACEMENT        When aligning components with options in Placement mode displays no busy indicator
) h. f$ D6 h9 n$ E: p
1145286 CONCEPT_HDL    CORE             Directive required for switching off the console
" }. I6 G" y% L% \3 X  C$ E
& Z# P/ g% v! E. b6 K* a) H) Q1145800 ALLEGRO_EDITOR GRAPHICS         Spurious odd lines are shown in shapes and text that are not part of the design with opengl.

1147899 ALLEGRO_EDITOR SHAPE            Autovoid two overlapping shapes that share the same net

1149996 ALLEGRO_EDITOR EDIT_ETCH        Routing does not follow the ratsnest 'pin to pin'.

- V1 ^' V1 e1 T6 U1150847 ALLEGRO_EDITOR INTERFACE_DESIGN Rename of DiffPair was not retained.
$ `$ m4 ^% ]$ F! m, j
, B: B& d1 N1 m& x1152577 ALLEGRO_EDITOR DATABASE         slide removes cline seg

1152751 CONCEPT_HDL    CORE             Option to double-click and copy the Netname

1153220 ALLEGRO_EDITOR INTERFACES       ENH: option to supress header/footer during PDF Export
" r1 |) B* G* Q+ w
1153625 ALLEGRO_EDITOR INTERFACES       If Symbol has place bound bottom, the step model shows incorrect placement.

1153813 CONCEPT_HDL    CORE             Spaces should not be allowed in the signal name entry form
- R# g) z, V/ W& n! f4 T
0 {4 _& g5 S1 L( H: P! c1153857 CONCEPT_HDL    CORE             Changing different power symbol should maintain the schematic level properties.

) g( V6 |5 ], Y  g. g! U/ u& C  K1155161 CONCEPT_HDL    CORE             Add Signal name: Suggestion box overlaps with the typed signal name that is typed
! Z1 z6 S- Z& s2 ]9 B
1155922 CONCEPT_HDL    OTHER            How can I use the batch mode for PDF Publisher and print a variant overlay?

" i5 E9 _5 d2 g6 {$ D2 T1156858 ALLEGRO_EDITOR pads_IN          PADS Translator: Missing drill on square PTH padstack

1157362 APD            3D_VIEWER        Need a way to color multiple nets in 3D viewer from APD/SiP.
1 i  ~# L, k+ c. m
1158130 CONSTRAINT_MGR ANALYSIS         Constraint Manager do not display the Cumulative Result in Reflection Simulation

: d7 N1 t* ]3 Z( i4 M; O( d0 D1158210 ALLEGRO_EDITOR SHAPE            SIP Layout happens crash while users move the shape with route keep-out
$ s7 Q8 R3 \; C5 i6 D% u0 N
$ z( z7 R5 C1 u1158452 SIG_INTEGRITY  GEOMETRY_EXTRACT CPW differential traces are not extracted as coupled when they are routed at an angle
! w6 {7 _  d" u( i: \. m) w
! p# `; b! u. l2 {1158827 ALLEGRO_EDITOR EDIT_ETCH        Slide a via in pad automatically add cline back to via to pin.

1158871 PCB_LIBRARIAN  IMPORT_CSV       PIN TEXT is not automatically added when importing the .csv file
3 O/ m' D8 V& G! _
" b; f5 I3 I0 \  x; q& b: L1159738 ALLEGRO_EDITOR INTERACTIV       Selecting the Cancel button in the Text Edit command does not cancel the text.

1159878 SIG_EXPLORER   OTHER            Ecset mapping dont follow topology template

& d5 t9 S2 f$ \! e0 N1159971 ALLEGRO_EDITOR MANUFACT         Allegro PDF Publisher requires ability to control film record sequence when generating the combined PDF file
: g- q: @% X1 F5 h7 X
! ?6 Y# X( E* b6 m6 Q1160017 SIP_LAYOUT     DIE_ABSTRACT_IF  Add text to clarify shrink operation
+ }+ |) L# p) R" q! ~
* {  k) ~1 I) n# n# r2 U/ S1160507 APD            EDIT_ETCH        Script not playing back what was recorded when sliding lines
; }# E$ m* r: \/ Z/ W, D" c
1161261 ADW            TDO-SHAREPOINT   Schema for TDO-SP fails on Japanese OS
9 D/ E7 E: i0 |+ i7 o" F/ Z
) B# w" J9 F) v. ^: t( }- @  j1161538 CONCEPT_HDL    CORE             Espice model value edited in DE HDL  & then netlisting done, but it doesnt changes the earlier assigned model in Allegro

1161636 ALLEGRO_EDITOR DRAFTING         need new function for PDFout : hatching shape
% s7 X1 P' B  X
$ k( {3 ^1 G2 T0 l0 N& m! ~1161777 ALLEGRO_EDITOR OTHER            default line width for PDF output
1 v  @8 ~9 h  B0 W4 @2 g
: r  L4 Z2 i  {2 j1162383 CONCEPT_HDL    CHECKPLUS        Checkplus not using $CDS_SITE/custom_help and $CDS_SITE/custom_rules_include directories.

1162562 CAPTURE        STABILITY        Capture crash on second attempt of Pspice netlist creation in 16.6

  d8 @4 O8 {' Y) W9 Y1162629 FSP            PROCESS          "Load Process Option" under Run does not work properly
$ x) e" O. M$ J0 @/ z3 z
1162686 CONCEPT_HDL    CORE             Changing NET_SPACING_TYPE to display both shows up with $NET_SPACING_TYPE
' L! d$ o* o$ Q' |
" j" `& P7 Q$ f7 o4 i1 Y1163149 ALLEGRO_EDITOR DATABASE         Autosilk creates Illegal arc to corrupt database
- F0 e: u9 R) Y
2 j* |; I1 _( _9 h% X1163439 ALLEGRO_EDITOR COLOR            Duplicate Views Listed in Visibility Tab.

; |- T; ~8 i3 G7 k1163521 CONCEPT_HDL    COMP_BROWSER     System Architect crahes on replace
, \  t& Q6 w. |3 ?
1163709 CONCEPT_HDL    CONSTRAINT_MGR   Loosing Diffpairs when reimport block or restore from definitioin
' b% L# C8 g$ Q# C3 z, V; W
1 U2 R1 N6 B0 T  I7 U0 a0 D1163902 APD            EXPORT_DATA      Q- In APD > File - Export - Board Level Component, check otion of delay reports is not working, is it ?
7 |: g5 p  X1 f4 o) Z( t) Z8 {
4 O5 q6 ^' j, _& ?: b" i1164337 CONCEPT_HDL    CORE             Cannot delete attribute filter value in PDF > General > Attribute Filter list
& Q! y4 A0 U# q$ i  M9 `3 C& S( X9 p
( m% v8 O1 I7 f& a3 ^1164365 ALLEGRO_EDITOR INTERACTIV       Symbol not selected for Move because Symbol Pin number selected in options tab not available on symbol

/ f& m2 c, f7 ?8 q- H1164769 APD            VIA_STRUCTURE    The replace via structure command does not accept a single canvas pick.

1165026 ASI_SI         GUI              EMS3D exist in Via Model Setup of SI base.

: d: b7 M1 M. ?* j" p1165561 CAPTURE        DRC              File > Check and Save clears waived DRCs
5 L$ I) y+ I! F& I# _. a
+ Q" E9 ^% p) ?1165631 CAPTURE        STABILITY        Capture crash in the hierarchy tab of Project Manager window

1165836 SIG_INTEGRITY  GEOMETRY_EXTRACT Some nets has no result at Bus Simulation and Comprehensive simulation.(update)

1165911 FSP            PROCESS          Editing group name in protocol causes incorrect Process option checked
' V# \' N5 S9 W3 b( e& u9 N
1166026 ALLEGRO_EDITOR DATABASE         Running DB Doctor removes net name from vias
6 a  r5 B4 x) u5 i& L1 f" c  U
1166034 SIP_LAYOUT     OTHER            SiP - Cline Change Width command enhanced to have selection by polygon not just rectangle
6 Y4 R' H; M2 G3 a& l/ Y- ?. \
1166074 GRE            CORE             GRE crashes during planning phases
& z6 j. l& N  p: u" N0 O: ]3 f
8 K, A9 \2 }) b% F0 u1166319 ALLEGRO_EDITOR PLACEMENT        Swap not succeed
& m% T9 P7 D  a4 `" D/ E8 a# [
1166484 SIP_LAYOUT     WIREBOND         Bondfinger "Align With Wire" problem during move
& j' i/ O! S) z* I
1166530 ALLEGRO_EDITOR INTERACTIV       Bug: Mirror in Placement Edit resets the options tab for Edit > Move
' L# u2 j$ i; C" i
) N7 L- I2 d7 D/ \7 R  a0 M1166819 CONCEPT_HDL    CORE             Cadence DEHDL Text Size Issue
$ p2 I4 U5 t; l: b' d( F5 G2 X* J3 b
2 }* ]& w2 X9 K( B* L# h1167847 CAPTURE        PROPERTY_EDITOR  Implementation name length greater than 31 character causes capture crash

1167887 F2B            OTHER            Improve message on symbol to schematic generation
4 r: F' z  U( L' [6 h4 Y
+ j3 J5 d- Z/ J' S& j$ C% f$ Z! k1168369 F2B            DESIGNVARI       Variant don縯 appear in increasing order while Annotate.
& ]+ `9 \1 K: a2 F* `% R5 w4 q2 `
' L0 K/ @! o" q5 y# s" D% F" O1168629 APD            OTHER            Do we have Skill command which is equivilant to Change Characteristics operation of a Wire Bond in APD

1168678 ALLEGRO_EDITOR NC               Drill Figure will be changed wrong layer when some subclass was deleted in SPB165S045.
* K$ H- w) o2 |3 {5 b
0 m# H* h) p5 r( J4 I& h1168798 ALLEGRO_EDITOR INTERACTIV       Enh - Allow user the ability to set the visibiity layer of refdes while moving the symbol rather than fixing it to silk

, o) @5 P6 G9 W" z: s1168830 ALLEGRO_EDITOR DRC_CONSTR       missing DRC-marker for package to package check

. @8 M  d! a, n. b; X9 ~6 w% x% l! n1168864 ALLEGRO_EDITOR CREATE_SYM       Saving the dra after Shape Expand/Contract throws warning 'Sector Table is not empty

4 V2 ?  O* d$ n5 ]4 s2 M1169213 PSPICE         SIMULATOR        Parametric sweep is giving incorrect reuslts

1169436 FSP            FPGA_SUPPORT     Add support for Cyclone V CSX and CST parts

1170108 ALLEGRO_EDITOR INTERACTIV       Enhancement to preserve Rat T location for Topology assigned schedule

1170313 SIP_LAYOUT     LOGIC            scm adding additional pin names and unassigned property to codesign die chips file

9 f/ u2 c0 m5 w3 y0 j: |1171136 CONCEPT_HDL    CORE             Page Number should also be displayed in Import Design Window.

; f, F. D- H- S7 B& ~1171747 ALLEGRO_EDITOR PLACEMENT        Allegro crashes when doing a gate swap between components

1172183 ALLEGRO_EDITOR INTERACTIV       Alignment modules fails on equal spacing

0 w8 I. s% b" _1 k8 V1173183 ALLEGRO_EDITOR DRC_CONSTR       Undesired Same net DRC for overlapping Pin and Via
+ E$ f& ?2 M( u# }
1 q/ Q3 f1 W" b# J2 Q# f$ @1174067 ALLEGRO_EDITOR DRC_CONSTR       Soldermask to shape drc does not show if the layer is a PLANE.

1174338 ALLEGRO_EDITOR PLACEMENT        preview has rotated pads
" n* k. v; e, V0 m
: x6 |! L4 W! l  {- ^5 D# x) |1175307 CONSTRAINT_MGR ANALYSIS         CMGR fails to report RPD DRC for accuracy 4 - mm

  i1 Z" @$ p% p( p1175537 ALLEGRO_EDITOR REPORTS          net loop report crashes Allegro. Design specific

* r- O/ _; \0 Q% e8 U1176126 ALLEGRO_EDITOR INTERFACES       3D viewer doesnot change models units dynamically

: w, N- u& q% m$ p7 u$ [6 S1176281 CONCEPT_HDL    CORE             Option to Auto-hide excluded modules

/ v- J$ C5 o7 a4 }: X8 o1176413 ALLEGRO_EDITOR MANUFACT         Q - testprep parameter settings is not retained, what could be the cause..
% p% O3 S2 S! T
1176791 ALLEGRO_EDITOR GRAPHICS         Spurious odd lines are shown in shapes and text that are not part of the design with opengl
7 u4 {7 w8 e- x
) P1 E1 U$ R0 p2 U* N; u9 c6 N, B3 y1178052 ALLEGRO_EDITOR SHAPE            SIP crashes during shape degassing.
7 x) k! y; t/ j8 r% d
0 M! n4 }8 C( z1 z2 t1178158 ALLEGRO_EDITOR INTERFACES       Export step file creates step file of same height

8 N# }, H/ u& L- |1178201 ALLEGRO_EDITOR GRAPHICS         Large oval pads rendered as oblong hexagons in the 3D viewer

2 s0 |. M  ~( U5 w2 f1178671 ALLEGRO_EDITOR GRAPHICS         3D Viewer in package symbol editor not displaying correct place bound shapes.
2 s% L1 L) T+ `" {" t) G
  a* r2 @' c7 ^/ g( U8 S- Q# e1178725 ALLEGRO_EDITOR OTHER            With fillets present, rat lines do not point to the closest endpoint.
, y1 s) C# W+ L3 h& L7 ^9 y
6 b/ q0 o. u! X2 M) Y" R1178972 CONSTRAINT_MGR ANALYSIS         The Cross-Section's parameters was not applied immediately after importing a DCF on the Constraint Manager.

1179093 ALLEGRO_EDITOR SHAPE            Dynamic Shape for GROUND net on TOP Layer is corrupted and is not voiding correctly in certain areas.
7 k, o) P) J  V8 e
1179109 ALLEGRO_EDITOR OTHER            DXF importing makes figure shift in 16.5&16.6 version it is ok in 16.3 version

1179571 ALLEGRO_EDITOR ARTWORK          Artwork crash and artwork log report Aparture missing
. ~2 z3 p1 a; L( t3 |, M- Z6 ]
) Q3 ~6 e' R. z# V1179636 SPECCTRA       ROUTE            Route Automatic will not start if NET_SHORT are attached to a mec-pin

1179659 SIP_LAYOUT     DIE_EDITOR       die edit on co-design die losing c4 bumps
& b$ I- e& X% h' ]2 ^/ P* A8 `
; d1 Z" x; \0 P1180306 ALLEGRO_EDITOR ARTWORK          When trying to create Artwork the tool crashes with no error messages just a little X box
: O( ^# F' T2 N
1180573 ALLEGRO_EDITOR ARTWORK          If one layer has warning, all artwork films are "created with warning".
" Z5 o9 t. h! y' |! h' f
6 J. q7 j" B  M% J& [1180960 SIP_LAYOUT     PLACEMENT        swap function is not swapping logical paths in sip layout!

1182534 ALLEGRO_EDITOR SKILL            axlLayerPrioritySet() not working with v166 s013 and up

1 F' C& Z  n9 {! r. U1182560 ALLEGRO_EDITOR PLOTTING         Creating plot 2nd time casues Allegro to crash
, v4 ]! U8 a" @/ h/ ]& K" ^
1182616 ALLEGRO_EDITOR PLACEMENT        Application crashes when attempting to place a high pin count BGA
3 y( {3 k9 p5 H( i" }+ p
1183752 CONCEPT_HDL    CORE             Unable to modify location properties within a read-only hierarchical block

6 ?( H$ I% J2 D. T1183774 SIP_LAYOUT     DIE_EDITOR       Die Refresh hangs

1184178 CONCEPT_HDL    CONSTRAINT_MGR   Ecset xnet members lost from electrical class when restore from definition of  subblocks

0 Y  @$ s  q5 W* K/ V8 Q1184787 ALLEGRO_EDITOR EDIT_ETCH        Allegro SPB166 s 015 crashes during normal add connect function.
8 u. S- T" |: }* K

Cadence SPB OrCAD 16.60.016 Hotfix

Download uploaded
http://uploaded.net/file/lo9hy18c/ceenS1660016fi.rar

9 h+ S- i' j" z8 JDownload filefactory
http://www.filefactory.com/file/6t9yiqdubs8t/n/ceenS1660016fi.rar
1 w; k1 K- n- o" \8 i0 F* Y2 M8 K
Download 城通网盘
http://www.400gb.com/file/31016333
/ l1 g2 p: A5 q: T) o9 h  w% q0 {# G
5 O8 ~6 M9 ]; @% }; o% X: DDownload 百度云
1 f% Q: b$ e& ]% j! {http://pan.baidu.com/s/1n9yPG

molin

谢谢，请问下有没有打补丁 的方法？？

pxgood

长假回来就给力了 谢谢了！！！

inspiron1501

前几个补丁跳过了，这次看bug fix，修正了很多，也增强了很多功能，特别是step方面，测试一下，多谢分享！

allanwang

谢谢楼主分享！！！

wxmcumtb

顶。。。。。。。。。。

lgl2466