Cadence SPB OrCAD 16.60.016 Hotfix

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cadence SPB orcad 16.60.016 Hotfix | 853 mb
4 Y7 P+ [  K2 i% J! [( r( ` DATE: 09-27-2013   HOTFIX VERSION: 016
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: @) a, y) R5 e; j6 Y- q; F: O===================================================================================================================================
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6 s# F$ g, k( b8 m& wCCRID   PRODUCT        PRODUCTLEVEL2   TITLE
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===================================================================================================================================
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548538  CAPTURE        NETLIST_allegro  Enhancement:Include mechanical parts in Allegro netlist

% Z' F& W, n0 _% l( \4 F: }' m1076579 CAPTURE        GENERAL          Display value only if value exists

; f7 O. K! Y) g5 ?5 K# y1083904 FSP            GUI              Need Filter in Change FPGA dialog to select desire FPGA from the long list.

1089313 ALLEGRO_EDITOR INTERFACES       Allegro Export PDF requires similar setup options as DE-HDL Export PDF for layer visibility

) T/ u0 W# B. ], k1095728 ALLEGRO_EDITOR EDIT_ETCH        Slide to grab adjacent elements when extend selection is enabled

4 K9 y9 g, o0 w- y: J6 J1102698 SIG_INTEGRITY  ASSIGN_TOPOLOGY  ECset will map on single ended nets but fails when the two nets are define as a diff pair.
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8 w  ?3 z/ r4 Y4 Y' X  ^1104071 SIG_INTEGRITY  REPORTS          Shape Parasitic value changes for bottom shape for changes in top shape
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) ]$ F6 {- a3 F& }1117731 FSP            POWER_MAPPING    Ability to sort in Power Regulator forms

+ j" |& v0 t5 Z7 J; r/ I% b, M- i1121539 FSP            CONFIG_SETTINGS  Cannot configure special FPGA pins (temperature diodes)

! M) x; ?# a" g0 k, g4 W. i1122721 FSP            MODEL_EDITOR     Partial copy-paste overwrites the complete cell in XML Editor
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9 A- }/ M' _% M% W1123238 FSP            TERMINATIONS     Report functionality for terminations defined in the complete design.

1123364 FSP            GUI              Clicking on column header should sort the column.

4 R4 _6 a# Z* Z$ v. F7 ]1123403 FSP            EXTERNAL_PORTS   Improper checkbox selection for 緿o Not Connect?or 縀xternal Port?column
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1125611 concept_HDL    OTHER            display unconnected pin in schematic pdf.
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% \  p0 @' o5 `- E5 ~) M1129871 ALLEGRO_EDITOR INTERACTIV       Wire Profile Editor can't read mcmmat.dat in working directory.

1133688 ALLEGRO_EDITOR GRAPHICS         Enhancement request to enable 3D Viewer to show STEP model from .dra file.

1141747 ALLEGRO_EDITOR GRAPHICS         3D view dooesnot displays height if step_unsupported_prototype variable set
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5 c: F" o. c' y0 w  k8 g1142215 SIG_INTEGRITY  SIMULATION       PULSE_PARAM set on DiffPair wasn't used for designlink simulation.

6 t& x; v2 B' `4 E$ A/ s- Q5 R1142798 ALLEGRO_EDITOR INTERFACES       Step file output is incorrect in step viewer when composed of arcs and line.
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1142894 FSP            GUI              Ability to RMB on a header and select `Hide Column?
1142940 FSP            EXTERNAL_PORTS   Issue with checking/unchecking "Do not connect" and "External port" cells

4 l% `0 O! y3 r& i. `+ @- h1142949 CONCEPT_HDL    skill            Usage of "Preferences > License Settings?in FSP

5 E$ Q1 Q1 I1 ^. t1143091 SIP_LAYOUT     SYMB_EDIT_APPMOD symed:  When AddPins is used to add pins to a co-design die, those pins are not output as bumps in the die abstract

1144371 CONCEPT_HDL    COMP_BROWSER     Component Browser search results are inaccurate
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1145033 ALLEGRO_EDITOR PLACEMENT        When aligning components with options in Placement mode displays no busy indicator
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1145286 CONCEPT_HDL    CORE             Directive required for switching off the console
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/ o8 n& Q; c' ~6 p6 c2 G1145800 ALLEGRO_EDITOR GRAPHICS         Spurious odd lines are shown in shapes and text that are not part of the design with opengl.
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1147899 ALLEGRO_EDITOR SHAPE            Autovoid two overlapping shapes that share the same net

( w9 G% ^$ M& K4 J" b7 @1149996 ALLEGRO_EDITOR EDIT_ETCH        Routing does not follow the ratsnest 'pin to pin'.

6 B" _0 t2 A) u/ i" j+ s# O1150847 ALLEGRO_EDITOR INTERFACE_DESIGN Rename of DiffPair was not retained.
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1152577 ALLEGRO_EDITOR DATABASE         slide removes cline seg
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1152751 CONCEPT_HDL    CORE             Option to double-click and copy the Netname
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% a' s' ?' `$ d& q3 q, q1153220 ALLEGRO_EDITOR INTERFACES       ENH: option to supress header/footer during PDF Export

1153625 ALLEGRO_EDITOR INTERFACES       If Symbol has place bound bottom, the step model shows incorrect placement.
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; h) R4 _7 x" i/ q1153813 CONCEPT_HDL    CORE             Spaces should not be allowed in the signal name entry form

1153857 CONCEPT_HDL    CORE             Changing different power symbol should maintain the schematic level properties.
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1155161 CONCEPT_HDL    CORE             Add Signal name: Suggestion box overlaps with the typed signal name that is typed

- A3 F( [$ D4 u9 u7 S1155922 CONCEPT_HDL    OTHER            How can I use the batch mode for PDF Publisher and print a variant overlay?
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1156858 ALLEGRO_EDITOR pads_IN          PADS Translator: Missing drill on square PTH padstack
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1157362 APD            3D_VIEWER        Need a way to color multiple nets in 3D viewer from APD/SiP.
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; [* w* Q7 g" f) I- j: K1158130 CONSTRAINT_MGR ANALYSIS         Constraint Manager do not display the Cumulative Result in Reflection Simulation

1158210 ALLEGRO_EDITOR SHAPE            SIP Layout happens crash while users move the shape with route keep-out

9 l, M- a$ J1 J1158452 SIG_INTEGRITY  GEOMETRY_EXTRACT CPW differential traces are not extracted as coupled when they are routed at an angle
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  s- D8 z, t7 S1158827 ALLEGRO_EDITOR EDIT_ETCH        Slide a via in pad automatically add cline back to via to pin.

1158871 PCB_LIBRARIAN  IMPORT_CSV       PIN TEXT is not automatically added when importing the .csv file
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1159738 ALLEGRO_EDITOR INTERACTIV       Selecting the Cancel button in the Text Edit command does not cancel the text.

1159878 SIG_EXPLORER   OTHER            Ecset mapping dont follow topology template
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1159971 ALLEGRO_EDITOR MANUFACT         Allegro PDF Publisher requires ability to control film record sequence when generating the combined PDF file
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1160017 SIP_LAYOUT     DIE_ABSTRACT_IF  Add text to clarify shrink operation
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1160507 APD            EDIT_ETCH        Script not playing back what was recorded when sliding lines
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1161261 ADW            TDO-SHAREPOINT   Schema for TDO-SP fails on Japanese OS

1161538 CONCEPT_HDL    CORE             Espice model value edited in DE HDL  & then netlisting done, but it doesnt changes the earlier assigned model in Allegro
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. o* m% w! B& u, f) c" P1161636 ALLEGRO_EDITOR DRAFTING         need new function for PDFout : hatching shape

1161777 ALLEGRO_EDITOR OTHER            default line width for PDF output
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  J3 ^! t1 w! [4 U0 r7 A6 q1162383 CONCEPT_HDL    CHECKPLUS        Checkplus not using $CDS_SITE/custom_help and $CDS_SITE/custom_rules_include directories.

1162562 CAPTURE        STABILITY        Capture crash on second attempt of Pspice netlist creation in 16.6

. k! {1 b. C7 C; J6 d- v1162629 FSP            PROCESS          "Load Process Option" under Run does not work properly

1162686 CONCEPT_HDL    CORE             Changing NET_SPACING_TYPE to display both shows up with $NET_SPACING_TYPE
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1 y: _/ Z4 |- x. |$ k1163149 ALLEGRO_EDITOR DATABASE         Autosilk creates Illegal arc to corrupt database
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6 v( E+ o8 M% n/ z! E" _6 S4 h) v1163439 ALLEGRO_EDITOR COLOR            Duplicate Views Listed in Visibility Tab.
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1163521 CONCEPT_HDL    COMP_BROWSER     System Architect crahes on replace
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1163709 CONCEPT_HDL    CONSTRAINT_MGR   Loosing Diffpairs when reimport block or restore from definitioin

1163902 APD            EXPORT_DATA      Q- In APD > File - Export - Board Level Component, check otion of delay reports is not working, is it ?
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' \' [8 v7 J+ T! @+ L, T4 B# W' _1164337 CONCEPT_HDL    CORE             Cannot delete attribute filter value in PDF > General > Attribute Filter list

5 b+ a9 v& I4 n1164365 ALLEGRO_EDITOR INTERACTIV       Symbol not selected for Move because Symbol Pin number selected in options tab not available on symbol
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1164769 APD            VIA_STRUCTURE    The replace via structure command does not accept a single canvas pick.

. \1 G/ d0 c% c5 G! a2 I1165026 ASI_SI         GUI              EMS3D exist in Via Model Setup of SI base.
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, j# v! w2 j% O  ?0 s0 k& l1165561 CAPTURE        DRC              File > Check and Save clears waived DRCs

5 C) Q) Z( V# g8 y2 L1165631 CAPTURE        STABILITY        Capture crash in the hierarchy tab of Project Manager window

2 k0 A  G  y- t5 ~+ a1165836 SIG_INTEGRITY  GEOMETRY_EXTRACT Some nets has no result at Bus Simulation and Comprehensive simulation.(update)
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( _# W+ ], T: ~' t  B% V1165911 FSP            PROCESS          Editing group name in protocol causes incorrect Process option checked
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1166026 ALLEGRO_EDITOR DATABASE         Running DB Doctor removes net name from vias
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9 I% z+ ^* J3 [9 P1166034 SIP_LAYOUT     OTHER            SiP - Cline Change Width command enhanced to have selection by polygon not just rectangle

1166074 GRE            CORE             GRE crashes during planning phases
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) _6 `; W. |* I! g9 Q, Y1166319 ALLEGRO_EDITOR PLACEMENT        Swap not succeed

1166484 SIP_LAYOUT     WIREBOND         Bondfinger "Align With Wire" problem during move

1166530 ALLEGRO_EDITOR INTERACTIV       Bug: Mirror in Placement Edit resets the options tab for Edit > Move
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1166819 CONCEPT_HDL    CORE             Cadence DEHDL Text Size Issue

6 S/ M. y+ |) ~$ p3 R5 H1167847 CAPTURE        PROPERTY_EDITOR  Implementation name length greater than 31 character causes capture crash
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4 H8 q# m9 c* G, G0 C2 }1167887 F2B            OTHER            Improve message on symbol to schematic generation

5 d; [3 w; w1 d$ G# N( z1168369 F2B            DESIGNVARI       Variant don縯 appear in increasing order while Annotate.

1168629 APD            OTHER            Do we have Skill command which is equivilant to Change Characteristics operation of a Wire Bond in APD
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1168678 ALLEGRO_EDITOR NC               Drill Figure will be changed wrong layer when some subclass was deleted in SPB165S045.

1168798 ALLEGRO_EDITOR INTERACTIV       Enh - Allow user the ability to set the visibiity layer of refdes while moving the symbol rather than fixing it to silk

1168830 ALLEGRO_EDITOR DRC_CONSTR       missing DRC-marker for package to package check

& h! h, P3 h4 k% y1168864 ALLEGRO_EDITOR CREATE_SYM       Saving the dra after Shape Expand/Contract throws warning 'Sector Table is not empty
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1169213 PSPICE         SIMULATOR        Parametric sweep is giving incorrect reuslts

1169436 FSP            FPGA_SUPPORT     Add support for Cyclone V CSX and CST parts

" y- c4 m+ c1 i& o; f7 ~1170108 ALLEGRO_EDITOR INTERACTIV       Enhancement to preserve Rat T location for Topology assigned schedule
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1170313 SIP_LAYOUT     LOGIC            scm adding additional pin names and unassigned property to codesign die chips file

% A1 }5 j  @; p) K0 `3 H1171136 CONCEPT_HDL    CORE             Page Number should also be displayed in Import Design Window.
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3 j0 F+ e4 y& k, L7 l1171747 ALLEGRO_EDITOR PLACEMENT        Allegro crashes when doing a gate swap between components
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; k6 o5 ^# S+ G& p) O. A1172183 ALLEGRO_EDITOR INTERACTIV       Alignment modules fails on equal spacing
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1173183 ALLEGRO_EDITOR DRC_CONSTR       Undesired Same net DRC for overlapping Pin and Via

4 ]2 R4 s4 o) e1 e" O/ o  ^1174067 ALLEGRO_EDITOR DRC_CONSTR       Soldermask to shape drc does not show if the layer is a PLANE.

1174338 ALLEGRO_EDITOR PLACEMENT        preview has rotated pads
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1175307 CONSTRAINT_MGR ANALYSIS         CMGR fails to report RPD DRC for accuracy 4 - mm
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1175537 ALLEGRO_EDITOR REPORTS          net loop report crashes Allegro. Design specific

/ c2 g# r3 T' o! ^. \) }1176126 ALLEGRO_EDITOR INTERFACES       3D viewer doesnot change models units dynamically
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% v1 j2 e2 y2 P0 V1176281 CONCEPT_HDL    CORE             Option to Auto-hide excluded modules
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: B+ y+ L9 L6 |' n- ~: y1176413 ALLEGRO_EDITOR MANUFACT         Q - testprep parameter settings is not retained, what could be the cause..
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1176791 ALLEGRO_EDITOR GRAPHICS         Spurious odd lines are shown in shapes and text that are not part of the design with opengl
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1178052 ALLEGRO_EDITOR SHAPE            SIP crashes during shape degassing.

1178158 ALLEGRO_EDITOR INTERFACES       Export step file creates step file of same height

" D6 {2 |4 p7 j' B- a9 r1178201 ALLEGRO_EDITOR GRAPHICS         Large oval pads rendered as oblong hexagons in the 3D viewer
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1178671 ALLEGRO_EDITOR GRAPHICS         3D Viewer in package symbol editor not displaying correct place bound shapes.

% t$ \+ M6 l0 K5 v8 v# M: {% c* ^6 t1178725 ALLEGRO_EDITOR OTHER            With fillets present, rat lines do not point to the closest endpoint.

1178972 CONSTRAINT_MGR ANALYSIS         The Cross-Section's parameters was not applied immediately after importing a DCF on the Constraint Manager.

; W1 v# T* c. |9 B+ d4 x  B/ Q% {1179093 ALLEGRO_EDITOR SHAPE            Dynamic Shape for GROUND net on TOP Layer is corrupted and is not voiding correctly in certain areas.
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3 V& I9 ?4 E2 E0 h. w  Z( ~8 Q1179109 ALLEGRO_EDITOR OTHER            DXF importing makes figure shift in 16.5&16.6 version it is ok in 16.3 version
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6 W" c8 t) u/ r' y; \' P- e& `1179571 ALLEGRO_EDITOR ARTWORK          Artwork crash and artwork log report Aparture missing
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3 I5 \" R$ }! `" j; r; {  w1179636 SPECCTRA       ROUTE            Route Automatic will not start if NET_SHORT are attached to a mec-pin
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  _. X/ y; r7 N. {4 \0 \1179659 SIP_LAYOUT     DIE_EDITOR       die edit on co-design die losing c4 bumps
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1180306 ALLEGRO_EDITOR ARTWORK          When trying to create Artwork the tool crashes with no error messages just a little X box

1180573 ALLEGRO_EDITOR ARTWORK          If one layer has warning, all artwork films are "created with warning".

8 E9 U$ k5 S. A7 s. Z1180960 SIP_LAYOUT     PLACEMENT        swap function is not swapping logical paths in sip layout!
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1182534 ALLEGRO_EDITOR SKILL            axlLayerPrioritySet() not working with v166 s013 and up
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& |9 n3 B! i' i6 S  w% ]% ?1182560 ALLEGRO_EDITOR PLOTTING         Creating plot 2nd time casues Allegro to crash
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0 O7 F- a3 z- \) b& S1182616 ALLEGRO_EDITOR PLACEMENT        Application crashes when attempting to place a high pin count BGA
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1183752 CONCEPT_HDL    CORE             Unable to modify location properties within a read-only hierarchical block
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) q9 [# F: s  u: ]2 ~. A: g1183774 SIP_LAYOUT     DIE_EDITOR       Die Refresh hangs

8 b; W: q) O4 |8 u( I$ i1184178 CONCEPT_HDL    CONSTRAINT_MGR   Ecset xnet members lost from electrical class when restore from definition of  subblocks

: q( _- I9 {/ h1 N5 e1184787 ALLEGRO_EDITOR EDIT_ETCH        Allegro SPB166 s 015 crashes during normal add connect function.
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9 j9 q1 U$ R6 @7 a0 _Cadence SPB OrCAD 16.60.016 Hotfix
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6 h6 E# J! j, Q* {: \" o5 lDownload uploaded
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molin

谢谢，请问下有没有打补丁 的方法？？

pxgood

长假回来就给力了 谢谢了！！！

inspiron1501

前几个补丁跳过了，这次看bug fix，修正了很多，也增强了很多功能，特别是step方面，测试一下，多谢分享！

allanwang

谢谢楼主分享！！！

wxmcumtb

顶。。。。。。。。。。

lgl2466