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cadence SPB orcad 16.60.016 Hotfix | 853 mb
0 \. {3 l3 X, R6 f# ^/ ? DATE: 09-27-2013 HOTFIX VERSION: 016! F$ N- B2 t2 w& C! m9 |
+ H3 ~+ d; I& y$ ^===================================================================================================================================. k J+ G7 m4 n: H# ?
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CCRID PRODUCT PRODUCTLEVEL2 TITLE
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===================================================================================================================================& i2 b& n) s( s8 r% \, M; a& `8 W* R
& p3 c( G: B: j: M7 |. O' g H) e2 ?548538 CAPTURE NETLIST_allegro Enhancement:Include mechanical parts in Allegro netlist( G4 i5 r0 I% J! j( D
7 F. K! }% U0 ~/ c" W1076579 CAPTURE GENERAL Display value only if value exists4 X" h& H4 \/ U$ |! c4 H; Y. ]
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1083904 FSP GUI Need Filter in Change FPGA dialog to select desire FPGA from the long list.
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8 J9 m4 `! k) a# c1089313 ALLEGRO_EDITOR INTERFACES Allegro Export PDF requires similar setup options as DE-HDL Export PDF for layer visibility; K* ^! [2 u' ~( J# I$ b" Z: v, R& n4 P
) h0 v; P1 d+ y; p) c. ^5 O1095728 ALLEGRO_EDITOR EDIT_ETCH Slide to grab adjacent elements when extend selection is enabled
! X4 [( \* A1 f4 ]: P, ]5 I7 @8 M7 D, j9 I' v: z; b+ R
1102698 SIG_INTEGRITY ASSIGN_TOPOLOGY ECset will map on single ended nets but fails when the two nets are define as a diff pair.) c5 g4 u7 e$ R' @8 i4 D
( v% J( U5 J" |+ d% {9 D1104071 SIG_INTEGRITY REPORTS Shape Parasitic value changes for bottom shape for changes in top shape
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1117731 FSP POWER_MAPPING Ability to sort in Power Regulator forms4 |+ v }3 l9 G* h3 P
% a# I( y3 \. x5 `% ]# R0 I1 a1121539 FSP CONFIG_SETTINGS Cannot configure special FPGA pins (temperature diodes)! d6 m# g$ b8 W3 a- {
5 h" g8 s/ z( E; v
1122721 FSP MODEL_EDITOR Partial copy-paste overwrites the complete cell in XML Editor
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1123238 FSP TERMINATIONS Report functionality for terminations defined in the complete design.& }+ p3 q) E# k
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1123364 FSP GUI Clicking on column header should sort the column.- O0 |% E! U/ ~& o$ ^) C0 r
3 R" t' Y9 }4 a! B3 p2 e' n4 a1123403 FSP EXTERNAL_PORTS Improper checkbox selection for 緿o Not Connect?or 縀xternal Port?column
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1125611 concept_HDL OTHER display unconnected pin in schematic pdf.
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( O( S6 m2 O. z$ x9 G" g/ ]% s k1129871 ALLEGRO_EDITOR INTERACTIV Wire Profile Editor can't read mcmmat.dat in working directory.5 Y6 m6 W3 E1 \, a- a
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1133688 ALLEGRO_EDITOR GRAPHICS Enhancement request to enable 3D Viewer to show STEP model from .dra file.
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1141747 ALLEGRO_EDITOR GRAPHICS 3D view dooesnot displays height if step_unsupported_prototype variable set
9 i! Z3 {; Y- I5 ?3 R( q" e6 y h- v* q# J7 d
1142215 SIG_INTEGRITY SIMULATION PULSE_PARAM set on DiffPair wasn't used for designlink simulation." d3 k4 U% Y& L; Z
9 Q- y1 X2 C4 m Y7 c
1142798 ALLEGRO_EDITOR INTERFACES Step file output is incorrect in step viewer when composed of arcs and line.5 z# E+ y6 { f6 r' W+ ]4 g0 \! ^
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1142894 FSP GUI Ability to RMB on a header and select `Hide Column?$ \9 ?) B! P; @: P1 k0 F
1142940 FSP EXTERNAL_PORTS Issue with checking/unchecking "Do not connect" and "External port" cells/ v! |3 j" E8 T2 r
# y6 Q% b" ?5 ]$ i
1142949 CONCEPT_HDL skill Usage of "Preferences > License Settings?in FSP8 d! n7 l! B+ l, w3 Y( T% Z
1 G1 ? {3 ^4 N) G2 _/ E+ m i1143091 SIP_LAYOUT SYMB_EDIT_APPMOD symed: When AddPins is used to add pins to a co-design die, those pins are not output as bumps in the die abstract
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1144371 CONCEPT_HDL COMP_BROWSER Component Browser search results are inaccurate
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1145033 ALLEGRO_EDITOR PLACEMENT When aligning components with options in Placement mode displays no busy indicator
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1145286 CONCEPT_HDL CORE Directive required for switching off the console
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" P( V4 N* Q. A+ F0 q( C1145800 ALLEGRO_EDITOR GRAPHICS Spurious odd lines are shown in shapes and text that are not part of the design with opengl.
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1147899 ALLEGRO_EDITOR SHAPE Autovoid two overlapping shapes that share the same net3 e3 _- o, w* A
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1149996 ALLEGRO_EDITOR EDIT_ETCH Routing does not follow the ratsnest 'pin to pin'.& g, c9 Z9 Y7 I
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1150847 ALLEGRO_EDITOR INTERFACE_DESIGN Rename of DiffPair was not retained.+ d, N- P4 }) o) u& u
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1152577 ALLEGRO_EDITOR DATABASE slide removes cline seg
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1152751 CONCEPT_HDL CORE Option to double-click and copy the Netname
: e2 p! |+ I1 n k: r, L) |3 K7 w0 E% T5 c* V; {$ Y/ Q8 }# x' S
1153220 ALLEGRO_EDITOR INTERFACES ENH: option to supress header/footer during PDF Export! a1 \; k! p) E+ M3 z
h( Q+ r6 v8 b' }- q
1153625 ALLEGRO_EDITOR INTERFACES If Symbol has place bound bottom, the step model shows incorrect placement.
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1153813 CONCEPT_HDL CORE Spaces should not be allowed in the signal name entry form# ], \( \, W# P0 ^4 @1 |9 x' w) e
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1153857 CONCEPT_HDL CORE Changing different power symbol should maintain the schematic level properties.. e# y- k2 e3 I( M
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1155161 CONCEPT_HDL CORE Add Signal name: Suggestion box overlaps with the typed signal name that is typed
0 k: P( b7 N1 Q m5 ^1 J) y
9 Y+ ~+ b5 ^8 r3 c7 r2 ^- ~5 A1155922 CONCEPT_HDL OTHER How can I use the batch mode for PDF Publisher and print a variant overlay?5 L' g2 S" G0 R7 K5 j* d$ i1 B
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1156858 ALLEGRO_EDITOR pads_IN PADS Translator: Missing drill on square PTH padstack- k5 }5 n7 Z" Y) b
8 j& `* I: a/ g: L4 t1157362 APD 3D_VIEWER Need a way to color multiple nets in 3D viewer from APD/SiP.
9 V6 E# }/ S- N; O! I2 o8 ~; U
1158130 CONSTRAINT_MGR ANALYSIS Constraint Manager do not display the Cumulative Result in Reflection Simulation+ S9 f4 o2 c9 { F6 K
4 ]- f2 |8 A6 f( U4 z- Y% G1 }7 G1158210 ALLEGRO_EDITOR SHAPE SIP Layout happens crash while users move the shape with route keep-out% q2 E+ w$ ~* z ]/ @2 ^1 H- _
l7 r# \ L& W1158452 SIG_INTEGRITY GEOMETRY_EXTRACT CPW differential traces are not extracted as coupled when they are routed at an angle
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1158827 ALLEGRO_EDITOR EDIT_ETCH Slide a via in pad automatically add cline back to via to pin.
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1158871 PCB_LIBRARIAN IMPORT_CSV PIN TEXT is not automatically added when importing the .csv file, ]- c4 W' g0 x2 W; u$ z- S; g/ m
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1159738 ALLEGRO_EDITOR INTERACTIV Selecting the Cancel button in the Text Edit command does not cancel the text.- c! _- f% z3 x) u8 r
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1159878 SIG_EXPLORER OTHER Ecset mapping dont follow topology template
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1159971 ALLEGRO_EDITOR MANUFACT Allegro PDF Publisher requires ability to control film record sequence when generating the combined PDF file. v" p7 w0 f/ R
+ k9 z! r3 B3 m1160017 SIP_LAYOUT DIE_ABSTRACT_IF Add text to clarify shrink operation
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" y( V8 d3 B7 r, p4 f7 I' q1160507 APD EDIT_ETCH Script not playing back what was recorded when sliding lines) A) C: i9 Z2 C0 O: ?
/ r h9 G& R; l& I1161261 ADW TDO-SHAREPOINT Schema for TDO-SP fails on Japanese OS6 \. j9 y* F, `4 \
% f }" J" P8 e7 S2 v% o% x& U1161538 CONCEPT_HDL CORE Espice model value edited in DE HDL & then netlisting done, but it doesnt changes the earlier assigned model in Allegro
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O, h& f$ C5 J1161636 ALLEGRO_EDITOR DRAFTING need new function for PDFout : hatching shape
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1161777 ALLEGRO_EDITOR OTHER default line width for PDF output
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' a3 a m4 P0 V; W9 w) [, y3 a1162383 CONCEPT_HDL CHECKPLUS Checkplus not using $CDS_SITE/custom_help and $CDS_SITE/custom_rules_include directories.( L1 {, ^0 p4 r8 Y1 R
7 y9 [# t! j1 V V8 r8 k3 U9 L
1162562 CAPTURE STABILITY Capture crash on second attempt of Pspice netlist creation in 16.69 D- K u, `( ?: h$ ?3 ^
8 ]; f8 w! z+ x( Z4 g2 e7 W b0 J
1162629 FSP PROCESS "Load Process Option" under Run does not work properly
6 r8 V0 D K6 t+ ?1 U
6 b& m) {2 Y! D6 W1162686 CONCEPT_HDL CORE Changing NET_SPACING_TYPE to display both shows up with $NET_SPACING_TYPE- ?# l' ~: D3 {1 J9 I1 f% h- }
# w9 C6 ?6 v5 e1163149 ALLEGRO_EDITOR DATABASE Autosilk creates Illegal arc to corrupt database
7 H' ]" d" j% J1 |% \: E: L& [! G g$ a3 c) Q0 O6 _8 b
1163439 ALLEGRO_EDITOR COLOR Duplicate Views Listed in Visibility Tab.
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1163521 CONCEPT_HDL COMP_BROWSER System Architect crahes on replace
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1163709 CONCEPT_HDL CONSTRAINT_MGR Loosing Diffpairs when reimport block or restore from definitioin
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7 w' M& \& n5 C# K0 Y% `, v1163902 APD EXPORT_DATA Q- In APD > File - Export - Board Level Component, check otion of delay reports is not working, is it ?: Y. H/ {0 h& ^8 ]$ x) A1 V
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1164337 CONCEPT_HDL CORE Cannot delete attribute filter value in PDF > General > Attribute Filter list( S! K9 U9 V" b" u
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1164365 ALLEGRO_EDITOR INTERACTIV Symbol not selected for Move because Symbol Pin number selected in options tab not available on symbol
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6 d2 b) a5 X/ k, F. }5 i1164769 APD VIA_STRUCTURE The replace via structure command does not accept a single canvas pick.) i5 s8 I$ z1 j4 w, w8 G7 }
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1165026 ASI_SI GUI EMS3D exist in Via Model Setup of SI base./ g0 T3 T, z& l) P/ D4 S8 o1 g
8 E4 Z7 ?# U$ j# a/ _
1165561 CAPTURE DRC File > Check and Save clears waived DRCs1 T5 s% j9 ~+ V; X* q
/ P ^3 Z: Z3 M X& G# P0 ?( m1165631 CAPTURE STABILITY Capture crash in the hierarchy tab of Project Manager window
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1 ~: E" C; j7 c% R1165836 SIG_INTEGRITY GEOMETRY_EXTRACT Some nets has no result at Bus Simulation and Comprehensive simulation.(update)
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1165911 FSP PROCESS Editing group name in protocol causes incorrect Process option checked
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1 ?2 T( `2 x u2 _' L1166026 ALLEGRO_EDITOR DATABASE Running DB Doctor removes net name from vias
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1166034 SIP_LAYOUT OTHER SiP - Cline Change Width command enhanced to have selection by polygon not just rectangle# s8 W# i4 z K; N7 y* g
5 |3 r* _5 R# b; T; o2 U- N' ~
1166074 GRE CORE GRE crashes during planning phases1 v6 ^8 S$ v% A, R
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1166319 ALLEGRO_EDITOR PLACEMENT Swap not succeed
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* i, Z/ m; y# m, ~ B1166484 SIP_LAYOUT WIREBOND Bondfinger "Align With Wire" problem during move
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3 L/ r+ y4 t! h+ G1166530 ALLEGRO_EDITOR INTERACTIV Bug: Mirror in Placement Edit resets the options tab for Edit > Move
# P9 Y/ E* ^0 [3 F& ]3 H
- G2 M% U* b& ]1 D, G7 f* p6 v* Q1166819 CONCEPT_HDL CORE Cadence DEHDL Text Size Issue" P/ s* j, `3 j, }6 {0 N" j
" Z) }! {/ ^ ~1167847 CAPTURE PROPERTY_EDITOR Implementation name length greater than 31 character causes capture crash8 l' T: N7 |; j7 F Y6 U
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1167887 F2B OTHER Improve message on symbol to schematic generation4 Y+ T+ ^( S$ p- q- ^
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1168369 F2B DESIGNVARI Variant don縯 appear in increasing order while Annotate.! V& ?; X) n" q
2 j& l/ ~+ f2 q5 d
1168629 APD OTHER Do we have Skill command which is equivilant to Change Characteristics operation of a Wire Bond in APD/ Q% L6 e6 ^3 D4 e5 b# [ @
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1168678 ALLEGRO_EDITOR NC Drill Figure will be changed wrong layer when some subclass was deleted in SPB165S045.
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1168798 ALLEGRO_EDITOR INTERACTIV Enh - Allow user the ability to set the visibiity layer of refdes while moving the symbol rather than fixing it to silk; M1 D, ]% {. S9 L0 R. @5 Q- s' a$ [
+ b. s* I: g, D4 Z' B% w
1168830 ALLEGRO_EDITOR DRC_CONSTR missing DRC-marker for package to package check; P: h Z0 z3 S2 d
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1168864 ALLEGRO_EDITOR CREATE_SYM Saving the dra after Shape Expand/Contract throws warning 'Sector Table is not empty
3 n6 d1 G/ A. H3 G8 V' P [9 d, N3 T. s. H$ ]) P, B0 H* V1 ?- K
1169213 PSPICE SIMULATOR Parametric sweep is giving incorrect reuslts
9 @- l t% ^9 f3 j/ |% F$ e
- t9 E5 k; [0 ~2 h1169436 FSP FPGA_SUPPORT Add support for Cyclone V CSX and CST parts5 f+ \8 T% q9 C' l1 y
7 D- ^& h% U+ X* T2 {2 {5 G" i1170108 ALLEGRO_EDITOR INTERACTIV Enhancement to preserve Rat T location for Topology assigned schedule# Q2 N1 i. x3 }) X) ], U
1 n' l/ O( R2 s8 i9 ?1170313 SIP_LAYOUT LOGIC scm adding additional pin names and unassigned property to codesign die chips file
5 G5 y: r, M! Q/ J1 O# l$ J* E, E' |2 G; y: ]& n, L+ x
1171136 CONCEPT_HDL CORE Page Number should also be displayed in Import Design Window.5 ~0 ?# c; s- @
$ n7 G+ W! B! f7 I. Z1171747 ALLEGRO_EDITOR PLACEMENT Allegro crashes when doing a gate swap between components2 {( a7 R9 |9 E; c0 ]! M4 R
* x/ w" | @$ y- V1 L! f2 Z( s1172183 ALLEGRO_EDITOR INTERACTIV Alignment modules fails on equal spacing
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1173183 ALLEGRO_EDITOR DRC_CONSTR Undesired Same net DRC for overlapping Pin and Via
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$ N5 U M+ ?* u$ N( U5 U3 c$ ~1174067 ALLEGRO_EDITOR DRC_CONSTR Soldermask to shape drc does not show if the layer is a PLANE.
2 {8 v* j" l# q3 ^: z _8 s
/ D. [( d7 [6 R+ `3 O$ s1 m1174338 ALLEGRO_EDITOR PLACEMENT preview has rotated pads
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1175307 CONSTRAINT_MGR ANALYSIS CMGR fails to report RPD DRC for accuracy 4 - mm: Q3 b: J& U2 v- s7 k0 \
! t+ ?5 ~0 _" P- A1175537 ALLEGRO_EDITOR REPORTS net loop report crashes Allegro. Design specific
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+ T6 V1 s+ P8 i1176126 ALLEGRO_EDITOR INTERFACES 3D viewer doesnot change models units dynamically6 Q: _6 q0 Q2 E' z: b; s5 t# f1 I/ D. }
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1176281 CONCEPT_HDL CORE Option to Auto-hide excluded modules
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2 F( E1 k6 s" o) T* x1176413 ALLEGRO_EDITOR MANUFACT Q - testprep parameter settings is not retained, what could be the cause..
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2 ~9 {! y3 u4 U3 U2 P6 o1176791 ALLEGRO_EDITOR GRAPHICS Spurious odd lines are shown in shapes and text that are not part of the design with opengl
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1178052 ALLEGRO_EDITOR SHAPE SIP crashes during shape degassing.
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1178158 ALLEGRO_EDITOR INTERFACES Export step file creates step file of same height8 Z& i3 U. M$ ?0 V$ B8 g- f4 H
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1178201 ALLEGRO_EDITOR GRAPHICS Large oval pads rendered as oblong hexagons in the 3D viewer
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1178671 ALLEGRO_EDITOR GRAPHICS 3D Viewer in package symbol editor not displaying correct place bound shapes.4 ?3 U, k, d) a- t
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1178725 ALLEGRO_EDITOR OTHER With fillets present, rat lines do not point to the closest endpoint.' r% T6 z. q# f% r5 _
( s% C( S7 l/ E- o1178972 CONSTRAINT_MGR ANALYSIS The Cross-Section's parameters was not applied immediately after importing a DCF on the Constraint Manager.
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1179093 ALLEGRO_EDITOR SHAPE Dynamic Shape for GROUND net on TOP Layer is corrupted and is not voiding correctly in certain areas.
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1179109 ALLEGRO_EDITOR OTHER DXF importing makes figure shift in 16.5&16.6 version it is ok in 16.3 version
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- F7 v5 m: P0 b0 D- W- i# Q; }* n+ I1179571 ALLEGRO_EDITOR ARTWORK Artwork crash and artwork log report Aparture missing$ P- K$ t# ]8 S9 J
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1179636 SPECCTRA ROUTE Route Automatic will not start if NET_SHORT are attached to a mec-pin
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3 C0 G$ }3 R( j- x' i u9 ?1179659 SIP_LAYOUT DIE_EDITOR die edit on co-design die losing c4 bumps6 w1 f& ~+ R2 f* t/ g& h+ }9 B
q9 u+ u; I0 X9 M% k6 @1180306 ALLEGRO_EDITOR ARTWORK When trying to create Artwork the tool crashes with no error messages just a little X box
4 x9 Z9 A+ y( m4 @/ _3 N' V( R% V! \
5 V, ^2 K5 a# M8 V" E1180573 ALLEGRO_EDITOR ARTWORK If one layer has warning, all artwork films are "created with warning".
4 y, ?2 E3 n/ E8 }6 N5 \6 I) j' A. }. ~5 m- @3 K7 i
1180960 SIP_LAYOUT PLACEMENT swap function is not swapping logical paths in sip layout!
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) v5 D* s/ W$ E# @1182534 ALLEGRO_EDITOR SKILL axlLayerPrioritySet() not working with v166 s013 and up
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1182560 ALLEGRO_EDITOR PLOTTING Creating plot 2nd time casues Allegro to crash
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6 }" x9 {4 U9 m! ~) o/ U+ A: S5 ?1182616 ALLEGRO_EDITOR PLACEMENT Application crashes when attempting to place a high pin count BGA
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( |3 H/ x2 M0 Y, u0 K+ ~- H$ I1183752 CONCEPT_HDL CORE Unable to modify location properties within a read-only hierarchical block: z& D ?& \8 M! `
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1183774 SIP_LAYOUT DIE_EDITOR Die Refresh hangs
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; j! K+ e# ?% f* p$ A1184178 CONCEPT_HDL CONSTRAINT_MGR Ecset xnet members lost from electrical class when restore from definition of subblocks- a2 e6 b P$ b& m4 |8 E
! [; n9 `8 C4 @9 ^5 O# K! l1184787 ALLEGRO_EDITOR EDIT_ETCH Allegro SPB166 s 015 crashes during normal add connect function.
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" S* y; f! w! L; tCadence SPB OrCAD 16.60.016 Hotfix
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Download uploaded0 J# D) s2 B& F* a) r9 r
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. F. I% U1 L$ ~5 `0 f0 }Download filefactory8 j$ y' R. B G2 f+ r/ j
http://www.filefactory.com/file/6t9yiqdubs8t/n/ceenS1660016fi.rar4 ]# r0 Q! N8 A: U
9 B( q( k- |. d3 ^
Download 城通网盘% Z1 @1 P6 E: Q. G; \. U
http://www.400gb.com/file/310163337 B* _" I U) K9 n
3 V6 Y5 g. I- k% }6 j# Q# C
Download 百度云 S4 P1 j0 w& X9 E
http://pan.baidu.com/s/1n9yPG& f9 P! z$ m. _$ l" b( b. {! w
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发表于 2013-10-5 20:59
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