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本帖最后由 紫菁 于 2017-9-14 14:13 编辑
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/ F& L( n! o& ucadence SPB orcad 16.5 最新的升级补丁，版本号16.50.47，修正内容如下：
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DATE: 09-6-2013 HOTFIX VERSION: 0473 l4 v9 }% m0 X2 a/ y" `. A7 B: l
CCRID PRODUCT PRODUCTLEVEL2 TITLE
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1095533 concept_HDL CORE changing visibility for $PNN results in crash in windows mode
6 c0 v* u6 T( K1153813 CONCEPT_HDL CORE Spaces should not be allowed in the signal name entry form
5 T6 J( O1 B$ |4 p1156102 PCB_LIBRARIAN CORE PDV severe peRFormance degradation on Linux platform makes PDV counter productive after some time
- ]4 U9 G) {. g$ h1161781 CONSTRAINT_MGR CONCEPT_HDL SigXp crash when selecting ECset in design
, m* T) H# F+ N8 `! g% U0 |5 r/ a1163709 CONCEPT_HDL CONSTRAINT_MGR Loosing Diffpairs when reimport block or restore from definitioin
7 t7 _" l! v6 u4 U1167887 F2B OTHER Improve message on symbol to schematic generation
( m, X3 T- X, K1168496 allegro_EDITOR SCHEM_FTB Export Physical Crashes when netreving the board
* e- m+ X$ s' m5 t+ ~1168830 ALLEGRO_EDITOR DRC_CONSTR missing DRC-marker for package to package check
1 q# n$ q" }, m* T/ Y: }1169593 CONCEPT_HDL PDF Published PDF file\'s hyperlinks do not work fine when user click 1D10 or 2A10.9 R' C [6 q4 u; L( G
1169984 F2B PACKAGERXL Error Mapping cset when packaging but not in CM Audit) Q5 X8 D% x# M) S7 i& d1 j
1171136 CONCEPT_HDL CORE Page Number should also be displayed in Import Design Window.
: ^# V3 R) R$ E9 `$ S \9 o1172597 ALLEGRO_EDITOR DATABASE Board cannot be unlocked using Password used while locking
) `2 j* w3 j* w1 \ I8 m4 S1172938 ALLEGRO_EDITOR PLOTTING Export IPF probrem, z) {" L n8 v0 k
1173183 ALLEGRO_EDITOR DRC_CONSTR Undesired Same net DRC for overlapping Pin and Via+ w: P0 A8 g& u8 k
1173829 ALLEGRO_EDITOR MANUFACT Backdrill completes even though a stub exceeds the MAX_PTH_STUB value( t$ L- M3 M" U2 B, O {: c: [9 s. r
1178972 CONSTRAINT_MGR ANALYSIS The Cross-Section\'s parameters was not applied immediately after importing a DCF on the Constraint Manager.
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发表于 2013-9-11 09:53
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发表于 2017-11-15 10:52
