i/o 的tri-state 和可控制状态区别？

thinkzero

Altera FPGA中DEV_OE管脚功能描述为控制全局I/O为三态或可控制状态，不明白三态和可控制状态的区别？

超級狗

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. l6 Q0 A6 ~* bDevice Output-Enable Pin
The MAX II device has a chip-wide output-enable pin (DEV_OE) to control the output enable for all output pins in your design. This allows bus-sharing in your system where you can disable the MAX II output so that other devices can drive the bus. If you use this option, all outputs on the chip operate normally when DEV_OE is asserted. When the pin is deasserted, all outputs are tri-stated. The DEV_OE pin functions as a normal user I/O pin if the option is not used.
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zgq800712

复用管脚，你要在quartus里面开启这个才能用。不开启就是个普通IO,开启就是DEV_OE功能。
开启后可能是输入0所有输出IO就变成三态口，相当于不让输出了。输入1就又变回输出IO了。
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timerc

那怎么开启这个管脚呢，怎么设置？