Cadence SPB16.6下载(Hotfix013已发布更新)

hzqydq

cadence SPB16.6下载(Hotfix013已发布)
6 C2 b  T/ p8 E1 ]" R$ L, i. {
  ]/ K5 g% h: g, P+ ]$ n! ~Cadence SPB16.6已经推出，需要的朋友可以点击下面的链接下载：
http://dl.vmall.com/c0ych9k8m3
3 B. K* `9 H4 W! f( \% w, ~
DATE: 07-26-2013  HOTFIX VERSION: 013
===================================================================================================================================
# ?! R0 n7 c2 p3 x# pCCRID   PRODUCT        PRODUCTLEVEL2   TITLE
===================================================================================================================================
3 B* _% I: D8 ^' i" W% {111368 CAPTURE        CORRUPT_DESIGN   Capture - will not produce allegro netlistwith 10.0
134439 PD-COMPILE     USERDATA         caCell terminals should be top-levelterminals
9 T9 f$ `9 B6 }% S: a186074  CIS            EXPLORER         refresh symbols from lib requires youto close CIS
- b2 R2 X9 Y6 M8 C5 X9 G4 V0 S583221 CAPTURE        SCHEMATIC_EDITOROption to have the Schematic Page Name as a Property in the Titleblock
591140 concept_HDL    OTHER            Scale overall output size inPublishPDF from command line
$ S2 w# T$ ^7 ~+ X+ N: o; I' L801901 CONCEPT_HDL    CORE             Concept Menus use the same key"R" for the Wire and RF-PCB menus
813614  APD            DRC_CONSTRAINTS  With Fillets present the "cline toshape" spacing is wrong.
881796 ALLEGRO_EDITOR GRAPHICS        Enhancement request for Panning with Middle Mouse Button
2 D7 y% {- v9 ]1 e# y' ?8 t( i- a887191 CONCEPT_HDL    CORE             Cannot add/edit the locked property
9 O$ m$ H$ F! L/ ~' y0 C; [, a$ o911292 CONCEPT_HDL    CORE             Property command on editing symbolattaches property to ORIGIN immediately
987766  APD            SHAPE            Void all command gets result as novoids being generated on specific env.
; p& _  c4 E- b! e; O2 \3 G1001395 SIP_LAYOUT    ASSY_RULE_CHECK  Shape Minimumvoid check reports lots of DRCs which are not necessary to check out.
9 O+ B1 t( o  [/ D/ P( s" H$ {1030696 ALLEGRO_EDITOR INTERACTIV       Enh - Allow another behavior of PANmovement using middle mouse in Allegro
1043856 ADW           TDA              Diff between TDOand DE-HDL Hierarchy Viewer is confusing to the user
8 w+ s8 y& c8 X  K8 N1046440 ADW           PCBCACHE         ADW: ImportSheetis not caching libraries under flatlib/model_sym when the source design is notan ADW project
1077552 F2B           PACKAGERXL       Diff Pairs get removed when packing withbackannotation turned on
, D3 r9 c: k1 T1079538 F2B           PACKAGERXL       Ability to blockall 縮ingle noded nets� to the board while packaging.
1086362 ALLEGRO_EDITOR SHAPE            Enhancement request to autovoid a viaif shape cannot cover the center of the via.
1087958 Pspice        MODELEDITOR      Is there anylimitation for pin name definition?
1087967 CIS           UPDATE_PART_STAT Update part status window shows incorrect differences
- L, v6 g3 j/ S- J# {1090693 ADW           LRM              LRMauto_load_instances does not gray out Load instances Button
1097246 CONCEPT_HDL   CORE             ConceptHDL -assign hotkeys to alpha-numerical keys
$ O2 o. d/ H$ F: ^% N' X, g5 I1099773 CONCEPT_HDL   CORE             DE HDL goes intorecursive loop if a custom text locked at site level is deleted from Tools >Option
0 Z: \0 Z- h) T9 d2 q1100945 SCM           SCHGEN           SCM generatedDE-HDL has $PN placement issue
1100951 PSPICE        SIMULATOR        Increasing theresolution of fourier transform results in out file
1103117 RF_PCB        FE_IFF_IMPORT    Enh- Allow theAllegro_Discrete_Library_to_ADS_Library_Translator to output in its originalunit
1 T" x1 Z2 K1 Z+ Z' Z6 O1105473 PSPICE        PROBE            Getting errormessages while running bias point analysis.
2 R2 G/ @% k  u: o! R1106116 FLOWS         PROJMGR          view_pcb settingchange was cleared by switching Flows in projmgr.
1106298 ALLEGRO_EDITOR INTERACTIV       Copy Shape uses last menu pick locationas origin and not the Symbol Origin as specified in Options.
1106626 CONCEPT_HDL   CORE             Concept HDL crashes when saving pages
1107086 ALLEGRO_EDITOR INTERACTIV       manual void with arc's goes in wrongdirection during arc creation
) K' T0 E& V  T9 W' |+ A- g1107172 CONCEPT_HDL   OTHER            Project ManagerPackager does not report errors on missing symbol
/ h! P, \* V7 v, L' V1108193 CONCEPT_HDL   CORE             Using theleft/right keys do not move the cursor within the text you're editing
1108603 PCB_LIBRARIAN VERIFICATION     PDV ToolsVerification > View Verification (CheckPlus) leaves<project>.cpm_tmp.cpm
* g/ I6 o5 `: U1109024 CIS            OTHER            orcad performance issue from Asus.
, {0 f" t" T8 G& _1109109 CAPTURE       NETLIST_ALLEGRO  B1: Netlistmissing pins when Pack_short property pins connected
- Y/ ?1 h* ^! h0 v" I1 ^3 _  [1109466 ALLEGRO_EDITOR ARTWORK          Artwork create some strange gerberlines for fillet.
& o1 E( O6 Z1 i1109647 SIP_LAYOUT    DEGASSING        Shape degassingcommand enhancement - control over what layers are counted in even/odd layersets.
" H+ }# z6 M' Q, _8 `7 m0 v: v1109926 CONCEPT_HDL   CORE             viewing a designdisables console window
1110194 SIP_LAYOUT    WIREBOND         If OpenGL settings for display ofdynamic net names is enabled, should be visible while push/shove wirebonds.
! v6 D9 l& Q/ a9 I( l( J' r$ |1112357 SIP_LAYOUT    WIREBOND         wirebond commandcrashes the application
1112395 CONCEPT_HDL   CORE             縗BASE\G� for global signal is not obeyedafter upreving the design to 1650.
1112658 CAPTURE       PROPERTY_EDITOR  Changing Part 縂raphic� value from property EditorChanges Occ refdes values to instance
1112662 CAPTURE       PROJECT_MANAGER  Capture crashesafter moving the library file and then doing Edit> Cut
1113177 PCB_LIBRARIAN CORE             Pin Shapes arenot getting imported properly
1113380 ALLEGRO_EDITOR INTERACTIV       Change layer to - option for packagetype .dra is not available in 16.6 release
% K# e4 m1 U6 J- }* f1113656 SIP_LAYOUT    WIREBOND         Enable Changecharacteristic to work without unfixing its Tack point.
1113838 SIP_LAYOUT    DIE_ABSTRACT_IF  probe pinsdefined in XDA die abstract file are added with wrong location
1113991 CAPTURE       GENERAL          Save Project Asis not working if destination is a linux machine
$ @( B6 l( O; o. c4 K: T+ w6 W  p1114073 APD           DRC_CONSTRAINTS  Shape voidingdifferently if there are Fillets present in the design.
1114241 CAPTURE       SCHEMATIC_EDITOR Port not retaining assigned color, when moved on theschematic
1114442 PSPICE        PROBE            Getting Internalerror - Overflow Convert with marching waveform on
1114630 CONCEPT_HDL   ARCHIVER         Archcore failsbecause the project directory on Linux has a space in the name
1 j* ~3 M, v4 {% t, l% B" |8 F# g3 v1114689 CONCEPT_HDL   CORE             Unknown projectdirective : text_editor
1114928 F2B           PACKAGERXL       縀rror (SPCODD - 5) while Export Physical even afterchange pin from A<0> to A
: X0 L" W$ ~" b+ ?" c4 C1116886 CONCEPT_HDL   CORE             Crefer hyperlinksdo not work fine when user use double digits partitions for page Border.
1118088 ALLEGRO_EDITOR EDIT_ETCH        Should Plan accurate and Optimize beremoved in 16.6?
  x# k3 n. m; ]* E3 C( a+ x. m1 P1118734 APD           EDIT_ETCH        Multiline routingwith Clines on Null Net cannot route in downward direction
. ~! @! f# D3 B% x) o  y! W5 Q1118756 ALLEGRO_EDITOR SHAPE            Shape clearance parameter oversizevalues getting applied to Keepouts
1119606 CONCEPT_HDL   MARKERS          Filtering two ormore words in Filter dialog box
2 y; X$ x4 y2 a$ L& S  l1119707 CONCEPT_HDL   CORE             Genview does not use site colors when gen schfrom block symbol
1119711 F2B           DESIGNSYNC       DesignDifferences show Net Differences wrongly
( h$ J) G! _) n1120659 CAPTURE       PROJECT_MANAGER  "Saveproject as" does not support some of Nordic characters.
+ i; ~7 O$ [* x+ C1120660 CONCEPT_HDL   CORE             Save hierarchysaves pages for deleted blocks.
1120817 SIP_LAYOUT    SYMB_EDIT_APPMOD Rotate pads commands not working while in the SymbolEdit App. mode
1120985 PSPICE        MODELEDITOR      Unable to importattached IBIS model
1121171 CONCEPT_HDL   CREFER           PNN and correctproperty values not annotated on the Cref flat schematic
1121353 ALLEGRO_EDITOR INTERACTIV       Local env setting will change aftersaving and reopening.
1121382 ALLEGRO_EDITOR INTERACTIV       Undo command is limited to two for thisdesign
1121540 F2B           PACKAGERXL       pxl.chg keepsdeleting and adding changes on subsequent packager runs
, c* K! \- r' M( J1121558 ALLEGRO_EDITOR MODULES          Unrouted net and unrouted connectionwhen module is placed of completely routed board file.
% p" e, Z- v; Y3 }- F1121585 ALLEGRO_EDITOR OTHER            Drill Hole to Shape Same NetSpacing with Dynamic Shapes shows wrong result.
1121651 CAPTURE       SCHEMATIC_EDITOR "PCB editor select" menu option is missing
1122136 SIP_LAYOUT    PLACEMENT        Moving acomponent results in the components outline going to bottom side of the design.
1122340 CAPTURE       NETLIST_ALLEGRO  Cross probe ofnet within a bus makes Capture to hang.
1122489 CONCEPT_HDL   OTHER            Save _Hierarchycausing baseline to brd files
1122781 CONCEPT_HDL   CORE             cfg_package isgenerated for component cell automatically
; u+ x( s6 p) P. u1 g1122909 CONCEPT_HDL   CORE             changing versionreplicates data of first TOC on 2nd one
1123150 CONCEPT_HDL   CORE             property on yaxis in symbol view was moved by visibility change to None.
! t; h; z- v- R0 O6 R1123176 ALLEGRO_EDITOR UI_FORMS         Negative values for pop-up location isnot retained with multiple monitors (more than 2)
1123815 ALLEGRO_EDITOR GRAPHICS         Embedded netname changes to a differentnetname
1124369 ALLEGRO_EDITOR INTERACTIV       Sliding a shape using iy coordinate doesnot work indepedent of grid.
1124544 CONCEPT_HDL   CORE             About SearchHistory of find with SPB16.5
9 d7 R5 h0 D, y1 }2 K' ?1124570 APD           IMPORT_DATA      When importingStream adding the option to change the point
/ D% F6 S$ c# G9 C0 g1125201 CONCEPT_HDL   CORE             Connectivityedits in NEW block not saved( lost) if block is created using block add
1125314 ALLEGRO_EDITOR INTERACTIV       Enved crash during setting of library paths inuser preference
3 m" u. M$ o  S9 Z; ?  s1125366 CONCEPT_HDL   CORE             DE-HDL crachESDuring Import Physical if CM is open on Linux
5 Y7 p+ Z  v  t4 K' `& D" e1125628 CONCEPT_HDL   CORE             Crash on doingsave hierarchy
1130555 APD           WIREBOND         Wirebond Import should connect to pinsof the die specified on the UI.
1131030 PSPICE        ENVIRONMENT      Unregistered iconof Simulation setting in taskbar
7 G0 V0 u0 H* K' Q  l$ V1131083 ALLEGRO_EDITOR INTERACTIV       Bug: 16.6 crash in changing the mode inFind filter window
1131226 ALLEGRO_EDITOR PLACEMENT        When Angle is set in design parameterswhile placement component is rotated but outline is not.
; U2 ~/ q* l3 t- P9 Q) J& w) u2 ~1131567 CONCEPT_HDL   OTHER            Lower case valuesfor VHDL_MODE make genview use pin location to determen direction.
. I! C7 ~4 G1 H. N" t1 k6 i8 ?1131699 PSPICE        PROBE            Probe windowcrash on trying to view simulation message
1132457 CONCEPT_HDL   CORE             The schematicnever fully invokes and has connectivity errors.
$ }. ]- \2 N" W" b+ D$ A: T3 q0 E/ r1132575 CONCEPT_HDL   CORE             2 pin_name weredisplayed and overlapped by spin command.
1132698 ALLEGRO_EDITOR EDIT_ETCH        Slide Via with Segment option with newSlide command
1132964 ALLEGRO_EDITOR SHAPE            Same net "B&B via toshape" errors created when adding shape
1133677 CONCEPT_HDL   CORE             Cant delete norreset LOCATION prop in context of top
8 D- e, y$ h2 E6 `" @1133791 CONCEPT_HDL   CORE             Cant do textjustification on a single selected NOTE in Windows mode.
1134761 CONCEPT_HDL   CORE             Why does MousePointer/Tooltip display LOCATION instead of $LOCATION property
4 j+ i) w% o, j% T1 T" f1135118 ALLEGRO_EDITOR INTERACTIV       Mirror and other editing commands aremissing for testpoint label text in general edit mode.
1136420 CAPTURE       GENERAL          Registrationissue when CDSROOT has a space in its path
1136808 PSPICE        STABILITY        Pspice crashmarker server has quite unexpectedly
( x% k0 P. f. B! F1136840 CAPTURE       SCHEMATICS       Enh: Alignment oftext placed on schematic page
1138586 ADW           MIGRATION        design migrationdoes not create complete ptf file for hierarchical designs
* u  a0 t# i# ?4 T1139376 CONCEPT_HDL   CORE             setting wirecolor to default creates new wire with higher thickness
1140819 APD           GRAPHICS         Bbvia does notretain temp highlight color on all layers when selected.
) ?+ V# F; J( T3 h1141300 CONCEPT_HDL   CORE             DE HDL hier_writesave hierarchy log reports summarizes Successfully saved block x while blockwas skipped
; V: J( y1 J6 x) q# b1141723 ADW           PURGE            purge commandcrashes with an MFC application failure message
# N" [- t- c& }6 O) ~7 N' M1143448 CAPTURE       GENERAL          About copy &paste to Powerpoint from CIS
1143670 SIP_LAYOUT    OTHER            Cross Probingbetween SiP and DEHDL not working in 16.6 release
; G. y! J; c+ Z, W( a1143902 ALLEGRO_EDITOR DATABASE         when the shape is rotated 45 degreesthe void is moved.
1144990 PCB_LIBRARIAN CORE             PDV expand &collapse vector pins resizes symbol outline to maximum height
1145112 CONCEPT_HDL   CORE             Warning message:Connectivity MIGHT have changed
1145253 CONCEPT_HDL   CORE             Component Browseradds properties in upper case
7 j6 Q" v: |7 J0 Z2 r, _1146386 ALLEGRO_EDITOR INTERACTIV       Place Replicate Create add Static shapewith Fillet shape
7 S! {! r5 C" w) C3 A# ~, c1 n8 F1146728 F2B           PACKAGERXL       DCF with upperand lower case values on parts causes pxl to fail
# e& [) o, |( E' H! s+ V1146783 ALLEGRO_EDITOR INTERFACES       Highlighted component is missing fromexported IPF file.
1147326 CONCEPT_HDL   CORE             HDL crashes whentrying to reimport a block
1148337 CAPTURE       ANNOTATE         Checking "refdes control" isnot giving the proper annotation result
1148633 SIP_LAYOUT    INTERACTIVE      Add "%"to the optical shrink option in the co-design die and compose symbol placementforms
/ L6 H; M7 m9 B6 e" V6 K1149778 CAPTURE       SCHEMATICS       Rotation of pspice marker before placementis not appropriate
+ M3 k; F1 I) z1149987 PCB_LIBRARIAN PTF_EDITOR       Save As pushingthe part name suffix into vendor_part_number value
1151748 ALLEGRO_EDITOR OTHER            If the pad and cline are the samewidth don't report a missing Dynamic Fillet.
1152206 CONCEPT_HDL   CORE             ROOM Propertyvalue changes when saving another Page
3 ~+ a  ~6 K* T1152755 CONCEPT_HDL   COPY_PROJECT     Copy projecthangs if library or design name has an underscore
1152769 PSPICE        ENCRYPTION       Unable to simulate Encrypted Models in16.6
1153308 ALLEGRO_EDITOR DRC_CONSTR       Creating Artwork Getting Warning"DRC is out of Date" even when DRC is up to date
" _! C% H6 L1 y: {" N; s, b% \1153893 F2B           DESIGNVARI       16.6 VariantEditor not supporting - in name
) ?: O! @! [- ]2 o( {1154185 SIG_INTEGRITY SIGNOISE         Signoise didn'tdo the Rise edge time adjustment.
( T  W% F( ]) o2 a1154860 ALLEGRO_EDITOR MANUFACT         Double digit drill character overlapswith figures triangle, hexagon and octagon in NC drill legend
1155167 ALLEGRO_EDITOR EDIT_ETCH        Via structure placed in Create Fanouthas incorrect rotation.
0 }/ Y6 Z$ y& l& N, d" O/ F1155728 CONCEPT_HDL   CORE             Unable to uprevpackaged 16.3 design in 16.5 due to memory
1155855 SCM           SCHGEN           A newlyuser-defined net property is not transferred from SCM to DEHDL in PreservedMode
1156274 ALLEGRO_EDITOR INTERFACES       Exported Step file from Allegro is wrong
1156316 CONSTRAINT_MGR OTHER            Break in functionality whilecreation of pin-pairs under Xnet in Constraint Manager
3 g4 u6 Y" S1 Q+ [+ ^1156351 CONCEPT_HDL   CONSTRAINT_MGR   Loose members inPhysical Net Class between DEHDL and Allegro
1156547 ALLEGRO_EDITOR DRC_CONSTR       Etch Turn under SMD pin rule checkthrough pin Etch makes confused.
6 t& t  R/ E" C8 L: \, ~1156779 CONSTRAINT_MGR OTHER            Electrical Cset References in CM notworking correctly
8 P, q6 a- J  F+ n0 X+ {1 h" B$ t" r1157167 ALLEGRO_EDITOR skill            axlPolyFromDB with ?line2poly isbroken
1158042 ALLEGRO_EDITOR DFA              DFA_DLG writes the dra file namein uppercase.
* j& ~  o1 j" w8 {/ r( \% ^1158718 CONCEPT_HDL   CHECKPLUS        Customer couldnot get $PN property values on logical rule of CheckPlus16.6.
1158970 ALLEGRO_EDITOR SCHEM_FTB        Changing LOCATION to $LOCATION in DEHDLdoes not update the .brd file
' M  J4 D  d" f) I1158989 ALLEGRO_EDITOR INTERFACES       pdf_out -l creates a PDF
1 D0 U  ^! L% A% D# m0 n1159285 APD           DXF_IF           DXF_OUT fails;some figures are not exported
' n8 d  {: Q1 q) C0 b1159432 ALLEGRO_EDITOR SHOW_ELEM        http:// in the Show Element in 166 donot have HTML link to open the Website
1159483 PCB_LIBRARIAN SETUP            part developercrashing with
  l/ u$ E! d0 ^* d0 h1159516 ALLEGRO_EDITOR EDIT_ETCH        Unable to slide cline segment with newslide.
1159959 ALLEGRO_EDITOR GRAPHICS         3D viewer displays clines arcsincorrectly
1160004 SCM           UI               The RMB->Pastedoes not insert signal names.
1160410 ALLEGRO_EDITOR DATABASE         Lock databse with View Lock option ismisleading
$ M2 g2 d# @% L' Z  X: `6 B1160529 SCM           SCHGEN           Schematicgeneration stopped because the tool was unable to create an appropriateinternal symbol structure
1160537 SPIF          OTHER            Cannot start PCBRouter
2 |) W  \% i2 s1161363 ALLEGRO_EDITOR SYMBOL           Getting error SPMHGE-73 when tryingto mirror symbol
' ]: e- K( \" ^1161781 CONSTRAINT_MGR CONCEPT_HDL      SigXp crash when selecting ECset indesign
3 m1 ^3 _* I3 A6 R- u2 Q* ~; M1161896 ALLEGRO_EDITOR DRAFTING         Tolerance value added for Dimensionsis not working correctly (HF11-12)
1162193 SIP_LAYOUT    DIE_ABSTRACT_IF  shapes in diafile not linked to the die after edit co-design die
/ |4 ?2 X- N3 G2 Z( R6 k( t1162754 APD           VIA_STRUCTURE    Replace Via Structurecommand selecting dummy nets.

txqtomton

楼主辛苦了！ 谢谢
% I3 o6 n1 t' I* ?/ }6 X' }

2000

楼主辛苦了！ 谢谢

q343408315

怎么屏蔽了

陈志军

好

每一天都不同

感谢分享