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我的还是不行呢,好多的帖子都试过了,一直出现
1 E4 [$ K: q) wTranslating E:/SPB16.3/Allegro/temp/project/S713OBX_SUBFPC/11.asc.
7 S- Y. }: V. u7 WUsing translator version @(#)$CDS: pads_in.exe v16-3-85D 11/3/2009 Copyr 2009 CADENCE DESIGN SYSTEMS.; U, V: D) ]. v8 ?2 i* {9 U
Reading PADS ASCII file header.
2 c1 P" L1 A/ F3 E i8 V Version = PowerPCB4.0
4 {( r0 @7 `* P6 p2 |6 { Route Layers = 2
8 i! N/ B0 _. |& _; w+ k" K Units = METRIC1 C+ W; h% {8 h5 _1 E
Hatch mode = Vertical / Horizontal) |, l. Y T, y5 J! X9 b' H
Hatch grid = 0.100000, angle = 0.000000, anti-pad spacing = 0.000008" m; z: O+ P7 P% x# G+ N
Initializing new database.$ `; h% g5 b* `- N8 R
Creating layers./ J' x7 u" {: N5 m' ]! U& r5 R2 z
Reading PADS ASCII file body.% C8 {3 J- V2 K' C: y$ [% ^
*MISC*
+ T% T! `9 k' h *MISC*
$ B1 N+ ?) Q/ z$ ]9 aInformation: CSet 1_5_6 renamed to DEFAULT
8 W& j E: s5 `3 Y
: x1 K0 [0 }8 ?9 \* V2 }Warning: Allegro doesn't support default electrical CSets.
- K8 ]- P4 f, y( E/ l. V *MISC*6 W K7 e1 h2 B8 W1 X' a
*MISC*' c! H+ I' D% Y1 ~2 q+ i
*MISC*
1 I K+ R" }7 ?; {7 M9 Z) b7 nLZ帮忙看一下什么问题呢? |
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