|
|
EDA365欢迎您登录!
您需要 登录 才可以下载或查看,没有帐号?注册
x
本帖最后由 dsws 于 2013-7-1 20:32 编辑 ' O) F. s( T8 O( O5 r& a3 Q
# \) f' G/ g( G
DATE: HOTFIX VERSION: 012
9 s8 g' V* h# F! P5 M2 n===================================================================================================================================
3 j0 m' \" o' F8 g% C8 C) sCCRID PRODUCT PRODUCTLEVEL2 TITLE8 j, R x2 E. A! I( j
===================================================================================================================================
% p& v5 ^# b: l( ?" G914562 allegro_EDITOR GRAPHICS 3D viewer, PCB Symbol view in DRA needs to be same as in BRD
& }3 [7 t! V9 g1 i1120397 concept_HDL CREFER CreferHDL attempts to create missing vlog004u.sir files* P% H2 @. y1 s( ]
1136449 ALLEGRO_EDITOR GRAPHICS about previous shape fill display
8 I8 f L3 T9 u! l1145635 ALLEGRO_EDITOR SHAPE Auto Voding on the same net shapes with other parameter.* t) G8 s/ I1 Y1 ~1 o
1150334 ALLEGRO_EDITOR EDIT_ETCH AiDT deletes the clines and turns it back to PLAN line! U. ]$ G" G7 o) n; h
1151100 APD VIA_STRUCTURE Net filter not working in replace via structure command.
9 l+ L: r% J+ H. ?, z, {9 p1151126 APD VIA_STRUCTURE Getting "group is not appropriate at this time" message when using Temp Group.
4 a9 i" D4 _7 B5 z! e/ u0 D1151458 GRE CORE GRE crashes on Plan Spatial2 H) q/ o6 t( k# E e6 s
1151932 F2B PACKAGERXL PXL error when case is wrong at differen levels in hierarchy% W9 o8 u& q+ r0 M% g; L
1152151 ALLEGRO_EDITOR INTERFACES dxf2a gives error [SPMHGE-268]
) T' v1 ?" q* D( D, k0 h; V1152475 Pspice SIMULATOR RPC server unavailable error while simulating the attached design
Y# `( J0 y7 T; v' }/ y0 D1152737 ALLEGRO_EDITOR skill dbids are removed because highlighted objects in setting the xprobe trigger/ B5 ]: v5 Z5 Q+ v4 R0 Y& u
1153006 ALLEGRO_EDITOR SKILL axlUIWPrint dose no work correctly in allegro PCB Editor 16.6.4 t/ P8 l% ~- f& `
1153279 CONSTRAINT_MGR OTHER Netrev changing design accuracy from 3 to 2 dec places
; P: \0 u M' I2 l }0 ~1153461 SIP_LAYOUT DIE_EDITOR Regression problem in 16.6 ISR: Dia Abstract ECO is causing Die Editor Finish to fail
M# K$ ]8 N+ k2 c; M2 k1154973 APD EDIT_ETCH Same Net "Line to Line" violation occurs even with "Allow DRC's" turned off.; {3 B0 ]7 o1 j0 ~: L) M' a5 x
1155227 ALLEGRO_EDITOR DRC_CONSTR via to shape check on the negative layer& J& N( e4 y5 \
! i% q& o, L- m1 r- z3 j! k
. \" I3 U2 A) f) c1 Fhttp://pan.baidu.com/share/link? ... 0&uk=38260382945 p1 ^: l2 N: b1 Z$ g- a3 v( e% ]' w
& U: G& ]. ^+ ?- h _
; t- U& K. a: u1 E0 z- S2 e7 y3 b& D% C7 ?: b; ?
|
|