|
|
EDA365欢迎您登录！
您需要 登录 才可以下载或查看，没有帐号？注册
x
本帖最后由 dsws 于 2013-7-1 20:32 编辑 ! P1 v: N2 Q6 b" _
4 j# h6 Y( C$ ?) Z) rDATE: HOTFIX VERSION: 012
' W, ?! C. o8 Q2 x8 \; a k===================================================================================================================================
2 v8 U8 G% L& MCCRID PRODUCT PRODUCTLEVEL2 TITLE; P# Z: m! B/ U2 ^ \$ a
===================================================================================================================================
2 \4 ^9 _! ]2 h& `, `' p% A914562 allegro_EDITOR GRAPHICS 3D viewer, PCB Symbol view in DRA needs to be same as in BRD" a# e, E+ V3 J% |5 H
1120397 concept_HDL CREFER CreferHDL attempts to create missing vlog004u.sir files$ {$ P; N! U! N2 N3 R, t
1136449 ALLEGRO_EDITOR GRAPHICS about previous shape fill display4 t! r# a( ?1 J4 g4 X( o& h
1145635 ALLEGRO_EDITOR SHAPE Auto Voding on the same net shapes with other parameter.( p% B9 y3 s( W- n3 ]0 I
1150334 ALLEGRO_EDITOR EDIT_ETCH AiDT deletes the clines and turns it back to PLAN line& L6 I. x4 o: _7 G3 R, Z* P
1151100 APD VIA_STRUCTURE Net filter not working in replace via structure command.) L4 P3 M ]2 M5 v4 X. o& C
1151126 APD VIA_STRUCTURE Getting "group is not appropriate at this time" message when using Temp Group. ~5 y' A2 h3 w5 k: I/ n
1151458 GRE CORE GRE crashes on Plan Spatial% e ]& k b7 }- n
1151932 F2B PACKAGERXL PXL error when case is wrong at differen levels in hierarchy
* l2 }" A% a5 ^! _& Y- p1152151 ALLEGRO_EDITOR INTERFACES dxf2a gives error [SPMHGE-268]1 g% \% \1 C" x" C9 P" v7 h7 s
1152475 Pspice SIMULATOR RPC server unavailable error while simulating the attached design+ b2 K$ C# d$ Z. {4 Y$ C, D5 j" t
1152737 ALLEGRO_EDITOR skill dbids are removed because highlighted objects in setting the xprobe trigger
+ _9 W& y4 b" n" ~: k# ^% ]1153006 ALLEGRO_EDITOR SKILL axlUIWPrint dose no work correctly in allegro PCB Editor 16.6.. b$ M1 U) l' X7 X
1153279 CONSTRAINT_MGR OTHER Netrev changing design accuracy from 3 to 2 dec places
# m1 a4 C2 a, Z) X4 H1153461 SIP_LAYOUT DIE_EDITOR Regression problem in 16.6 ISR: Dia Abstract ECO is causing Die Editor Finish to fail
3 G& k; n+ K: v, X; x' a1154973 APD EDIT_ETCH Same Net "Line to Line" violation occurs even with "Allow DRC's" turned off.
2 M+ X4 n& L. ~1155227 ALLEGRO_EDITOR DRC_CONSTR via to shape check on the negative layer( o8 d; K0 F6 _* o6 N4 d
3 t# M3 [, }9 p2 X& r
' g0 @! r+ l; ]' H9 {5 P4 X, Phttp://pan.baidu.com/share/link? ... 0&uk=3826038294
@; o5 B6 \( F& D0 C' M/ H( q0 R& f3 E
6 I" C9 e+ c" G; D: E) l. ]5 x
1 g5 _" U: x/ `7 i; J
|
|
[复制链接]
/1 
发表于 2013-7-1 12:00
收藏
淘帖
支持！
反对！
