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本帖最后由 dsws 于 2013-7-1 20:32 编辑 $ L- V# Y* f3 G$ o9 |
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- H- j ~' b1 H9 a7 P* n# Z: G" i5 C914562 allegro_EDITOR GRAPHICS 3D viewer, PCB Symbol view in DRA needs to be same as in BRD* o1 g9 R# s) P% x! |* T5 ?
1120397 concept_HDL CREFER CreferHDL attempts to create missing vlog004u.sir files
1 ~& |: T1 _- n0 l' J% Z$ D1136449 ALLEGRO_EDITOR GRAPHICS about previous shape fill display
! U W: i3 \5 D( i+ C H; I7 ]1145635 ALLEGRO_EDITOR SHAPE Auto Voding on the same net shapes with other parameter.8 w7 Z$ C L$ O, k
1150334 ALLEGRO_EDITOR EDIT_ETCH AiDT deletes the clines and turns it back to PLAN line
4 Z, q$ M) P r1151100 APD VIA_STRUCTURE Net filter not working in replace via structure command.) w3 e$ x |, u' h# y
1151126 APD VIA_STRUCTURE Getting "group is not appropriate at this time" message when using Temp Group.
6 E: ^8 n r5 s' {1151458 GRE CORE GRE crashes on Plan Spatial
) C# L" K4 \' z( x' U8 k7 l0 p( u1151932 F2B PACKAGERXL PXL error when case is wrong at differen levels in hierarchy( v2 u8 ~& v. F1 @. n; s2 G2 q
1152151 ALLEGRO_EDITOR INTERFACES dxf2a gives error [SPMHGE-268]
* o7 D1 X+ D% e, f% T* G- m; H; O4 G1152475 Pspice SIMULATOR RPC server unavailable error while simulating the attached design3 p" ~2 Y& U, y4 m9 J; X" o; Z
1152737 ALLEGRO_EDITOR skill dbids are removed because highlighted objects in setting the xprobe trigger
+ K+ g2 v' m3 A; O" e) h1153006 ALLEGRO_EDITOR SKILL axlUIWPrint dose no work correctly in allegro PCB Editor 16.6.; u$ m& B: q( t8 z. o9 j; c
1153279 CONSTRAINT_MGR OTHER Netrev changing design accuracy from 3 to 2 dec places- e1 Z+ P! B- P; Y. [9 X
1153461 SIP_LAYOUT DIE_EDITOR Regression problem in 16.6 ISR: Dia Abstract ECO is causing Die Editor Finish to fail
5 q! T; ?. L( R( i& C( q1154973 APD EDIT_ETCH Same Net "Line to Line" violation occurs even with "Allow DRC's" turned off.
" d; L/ v7 c5 W) h1155227 ALLEGRO_EDITOR DRC_CONSTR via to shape check on the negative layer4 z7 B! |! _( x1 E( E3 K- [8 ? z
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发表于 2013-7-1 12:00
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