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大家好，同样一块板子，第一次artwork时没有问题，第二次增加了两侧的工艺边后，artwork是报错，Dbcheck不通过，然后进行database check 一下为database的描述：; B" T5 ~1 z. x9 R9 v0 @% z' H
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4 J1 z* u$ l! i8 r8 X* i/ S8 b* PeRFormance checking for design Z:/E/supcon/PRD-13002/hardware/ESP-300 V1.1/ESP-300 V1_1.brd! D1 Z* | |& \. N2 Q: b& M& q- E3 N
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( {0 B7 \' P6 I7 ? N9 s( p
' U- o* h, `' @) WRatsnest schedule check; Z2 l6 K, ?8 A/ c. G) ?1 d6 A
-------------------------------
# K1 g# Y* D/ ? m6 i* OK.
8 x+ W6 N- y, u# ^6 o9 Y7 j) \. ~( C4 Q# t
DRC check
: G$ g4 w7 ?* j, M7 S0 m# m/ J- M----------------------3 |; b( w1 A# b, v2 u$ n
* The number of physical/spacing csets is 0.060241 larger than the number: n8 {3 u+ n9 ~+ n& K" a& L7 P
of nets Suggest examining constraint model.! \5 d5 E- n( F7 t# n6 R
ISSUE: Misuse of the allegro constraint model such as using a spacing# \+ @# w' |. A) @
cset for each diffpair in the design. Result is system
: O/ ^* _( H2 L# d; x* v& r performance degradation.
4 `. D0 q6 X/ y* _8 H
$ p3 V( o( \; \' g U6 [2 P7 J& h/ c* f2 n( o
Constraint region check
5 \0 [) _9 ^' ?% j+ a1 z( k/ _3 c- i-------------------------------
& b, J% }* c& h% |* Region on all - MINIUSB: Suggest use by layer or outer/inner regions.0 y( U/ U/ p! w7 t- b6 E1 G1 D
ISSUE: Encourage use of new layer based regions which helps performance and3 X) ]3 X* C- D/ ]2 H- ^1 l
simplifies constraint management.
3 P5 s$ q, n& @/ s* ?9 q+ i/ F; |8 B$ v) V
" E8 {# a0 _0 R6 [) D3 e
shape/region location: (35.1028,-31.5976)$ O& N! \) C1 g3 T6 T/ K
class: CONSTRAINT REGION subclass: ALL, o9 m9 [; y% Z; |
( P- `7 Z3 U x; A& O1 T, u8 O. e* Region on all - CPU: Suggest use by layer or outer/inner regions.
; p. a. W m$ V% N( E6 N ISSUE: Encourage use of new layer based regions which helps performance and
2 C$ `% t1 c! Z8 C, R9 U- d$ V simplifies constraint management.
& x3 r9 Y2 V) B2 X
1 F7 L) q9 T% K4 ~+ l/ |& g Y5 `+ ~* o* c, U1 ^
shape/region location: (7.9883,19.2659)6 A6 f) J$ v7 S1 P) J& i5 B4 W8 x
class: CONSTRAINT REGION subclass: ALL
0 t! i" F0 ]' s4 F
2 r" I7 h4 ^0 t4 H" F% }( j3 C8 u
Dynamic shape check1 @& p/ `( ]9 Q4 j4 x; d
-------------------------------
2 K) I6 {0 r! _6 D; F- W* t% t* OK.
6 b9 I- k9 g) g* f: u) P) p( N0 Y- E% ~
Sector table check
" A' [+ t" R) b2 z, a- u9 f-------------------------------: U+ R0 e6 C1 V# D# y$ _
* The ratio of design extent to route keepin extent is too large (10.375068). Suggest reducing design extent.
0 M; z: F% Y7 R" n, a: c7 |1 G& ?+ S6 P4 M9 \
Constraint set check
# y5 M7 Q( D* ^6 l& k, _--------------------------------- L2 x- r- q+ h, Q0 D) ]/ w8 t7 [
* Unused csets list (4):' E4 r) C7 c r- U) O
ISSUE: Design maintenance issue, slight performance impact.- b4 X9 T1 O& q
! n. S# v2 s/ [7 D, V- D1 T
SNCS: SN-POW0 f$ ~4 ^6 p; ~; l% I& J& T( b
PCS: PHY-LCDBG
y( ^$ H0 U" K+ B PCS: PHY-POW
! S( z' d# J, \# H- C SCS: SCSET-POW+ x, m W, f9 L. V; B- z+ @. c
5 V) V2 b6 y) |: P
* O, V- S' _' u; K% \7 LNODRC_SYM_SAME_PIN check
; ]2 Z W! K& Q c+ a! F# g+ x x---------------------------------
* z- I ^6 T# K6 i* OK.+ t- l K- |/ r3 U; C& @' w
( R x8 C9 u* ~3 d0 V( `Cross section check for bad dielectric constant values& M" k1 v* i% R8 Q
--------------------------------------------------------
& u! a: U" C( X3 R# s0 m# N* OK., S/ w4 a1 Z. K0 F, V
* L) ~9 m6 C7 A* [
padstack size check
G7 i! ^" S; i. |; H---------------------------------8 `4 _2 U3 q$ Z8 U$ ?; E
* OK.
' p6 m, A) ]! M$ V# {# ?7 B+ k6 h( x. a* @+ G: u2 U( Y
0 u' P. J7 R" g4 |1 @4 problems found. 1 maintenance problems found.
3 Q7 K1 v& U. y$ w! p: X* D7 Y: `3 ?1 a! p: C5 g- i
7 h0 W0 s4 `6 G* N$ s
问题：5 X) ]6 A+ Q9 t
1、artwork时是否有勾选实时数据检查；
' G( l& c; U$ J2、database check中哪些可以忽略，甚至屏蔽；
6 I \) t" h- N) c% T还有相关问题可提出，望大家一起，群策群力！！！$ M, k# P" E: P. R) L" b
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发表于 2013-6-20 08:51
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支持！
反对！