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07 Jun 2013 SPB16.50.044, Version: SPB:Hotfix:16.50.044~wint
; T- I3 J# @3 z) r0 ]5 ]* v% p, D6 v8 |3 F8 a7 U9 e5 T; F
DATE: 06-7-2013 HOTFIX VERSION: 044# `4 R# g; d* _0 ?& `; V# V3 P
===================================================================================================================================3 t; f! z+ o; f# X( ^
CCRID PRODUCT PRODUCTLEVEL2 TITLE8 w3 F2 Y+ k& t8 T6 L
===================================================================================================================================) B$ d* D7 ^: Q7 k3 k4 F( J) y
1055338 SIP_LAYOUT DRC_CONSTRAINTS Soldermask to Via drcs on bondfingers/ V7 f& R' r$ q0 d m& F' ]
1084716 allegro_EDITOR OTHER Getting an MPS error when updating CM from SigXplorer- G2 a) |8 c! |- d. g( q w
1104145 ALLEGRO_EDITOR SCHEM_FTB User defined properties do not appear in PCB
+ x' Q, _6 ]% `! `1106116 FLOWS PROJMGR view_pcb setting change was cleared by switching Flows in projmgr.! D! f* L+ n+ ^) h& T, h: M# X
1106900 concept_HDL COMP_BROWSER Component Browser peRFormance utility should honor CPM directives for include and exclude PPT
4 @& [8 q! Z1 @3 ^" f q1110323 APD DXF_IF DXF out is offsetting square discrete pads.
* p0 b b2 k, L( h2 T1 C g. ?3 P1119007 CONCEPT_HDL CORE PDF Publish of schematic creates extremely large PDF files
' _. r: {; t5 Y Z3 f( n- D1121020 FSP MODEL_EDITOR Cut-Paste from Excel causes empty cell in Rule Editor
* i+ A2 n# }4 K: |2 o1121353 ALLEGRO_EDITOR INTERACTIV Local env setting will change after saving and reopening.
& a/ C" H4 X" {4 U$ [2 _1122781 CONCEPT_HDL CORE cfg_package is generated for component cell automatically8 |/ K h; T! G3 l2 k3 T% w7 W
1122909 CONCEPT_HDL CORE changing version replicates data of first TOC on 2nd one
" e: ^' J+ l+ e8 s7 I- E1123581 ALLEGRO_EDITOR MANUFACT Dimension Line gets changed on board
( k- j+ N; `* z" r% k- t7 ?& g1124544 CONCEPT_HDL CORE About Search History of find with SPB16.51 q1 p& ^9 X% t! x e
1125366 CONCEPT_HDL CORE DE-HDL craches during Import Physical if CM is open on Linux4 K: ]3 Q L y, m; e; D5 d
1125628 CONCEPT_HDL CORE Crash on doing save hierarchy: ?3 y* H$ R' `+ F6 v% k0 @. x
1126182 ALLEGRO_EDITOR DRC_CONSTR Shape fillet DRC in same net thru via to thru via was removed after update DRC.* \) B9 k9 z* V s* m
1130945 SCM SCHGEN SCM Export Schematic does not copy all cells in the library9 X' Y7 ^) e1 t% F' O# m
1131567 CONCEPT_HDL OTHER Lower case values for VHDL_MODE make genview use pin location to determen direction.7 e: U. l7 W9 _) f2 z% @( B% Q
1131650 ALLEGRO_EDITOR PLOTTING PDF Publisher doesnot display few component defination properties in Property parameters0 e8 i/ ]6 L8 D9 c, x: Q; R$ C
1131868 CONCEPT_HDL CONSTRAINT_MGR Many net-class constraints "fell off" the design after uprev and Import Design of GEP4
+ g) r% M) @) W) M1132457 CONCEPT_HDL CORE The schematic never fully invokes and has connectivity errors.
$ s8 e* H7 n Y- k. E# v1132575 CONCEPT_HDL CORE 2 pin_name were displayed and overlapped by spin command.9 z x Q( c: n# V: |2 i( l
1132638 ALLEGRO_EDITOR DFA 'dfa_update' crashes when running the utility on the attached foder.
3 R, Y0 Z6 U2 a. Z; I# q1133677 CONCEPT_HDL CORE Cant delete nor reset LOCATION prop in context of top1 J v1 m& ]2 X. V6 q7 ~
1133791 CONCEPT_HDL CORE Cant do text justification on a single selected NOTE in Windows mode.1 E7 M, c# U1 k
1134083 CONCEPT_HDL OTHER Published PDF file's hyperlinks do not work fine when user use double digits partitions for page Border.
% ~' ], Z6 v. s1134761 CONCEPT_HDL CORE Why does Mouse Pointer/Tooltip display LOCATION instead of $LOCATION property
3 i/ m' a! J0 Q4 U1138586 ADW MIGRATION design migration does not create complete ptf file for hierarchical designs# r6 y; K0 y% N9 e
1139376 CONCEPT_HDL CORE setting wire color to default creates new wire with higher thickness
4 k7 a7 e& _- S7 l2 c) t' k6 Z1141300 CONCEPT_HDL CORE DE HDL hier_write save hierarchy log reports summarizes Successfully saved block x while block was skipped
! P1 O( X* k5 y9 X5 ?$ l1142876 ALLEGRO_EDITOR SHAPE No DRC error when airgap between place bounds exactly zero
4 a- ]% [. E: p& h1142884 ALLEGRO_EDITOR OTHER Boolean type user defined property doesn't export to the PDF
8 p1 j9 V5 R" x5 |2 P t+ V1145112 CONCEPT_HDL CORE Warning message: Connectivity MIGHT have changed
$ q3 B3 |5 T+ i4 c- V1 D1145235 CONCEPT_HDL CONSTRAINT_MGR DEHDL CM gives error when trying to launch SigXP' u! Q% `5 P- W9 w' O
1145253 CONCEPT_HDL CORE Component Browser adds properties in upper case8 m. T/ M) J/ \/ g
1145284 CONCEPT_HDL CORE Publish PDF crashes DE HDL
+ ]+ p2 }$ c9 B+ f; c1 K1145333 ALLEGRO_EDITOR SHAPE SHAPE boundary may not cross itself. Error cannot be fixed.' i$ E6 S) c# v9 @3 M) c1 T3 A
1145856 ALLEGRO_EDITOR DRC_CONSTR DRC Line to Thru Pin appear while Fillet be added
7 [- m, D5 u) {) {9 Z/ s1146287 PCB_LIBRARIAN CORE PDV expand pins and change origin sets coordinates for few pins wrong and places pins on top of each other after collaps* X$ G: L% c( B& E+ P
1146728 F2B PACKAGERXL DCF with upper and lower case values on parts causes pxl to fail
5 O4 T( g8 [! W) L1147326 CONCEPT_HDL CORE HDL crashes when trying to reimport a block) ~( t) B. b! B& o1 t7 q
4 h, G! P$ Z) ?# GDATE: 05-3-2013 HOTFIX VERSION: 043
7 r% W; u$ K0 H5 {- D===================================================================================================================================) ~0 z' R) ?6 i' _/ ]7 R+ v ^
CCRID PRODUCT PRODUCTLEVEL2 TITLE! R0 h& A$ b- h. k9 \0 d, f! y' |' N
===================================================================================================================================7 {, K; V# P3 i
876711 ALLEGRO_EDITOR GRAPHICS Mouse wheel will only zoom out using Win7 64 bit
& \$ O. D- T0 ?' `. p- { ]+ M1103246 FSP OTHER New FPGA request - Arria V - 5AGXMA1D6F31 - IN2P3
2 i( |+ }1 t. U4 B! U0 G1105249 ALLEGRO_EDITOR OTHER PDF out--- component user defined prop doesn't list the prop selection form0 u9 \5 v3 A2 i* t, M
1105504 PCB_LIBRARIAN CORE PDV on Linux Move pins by arrows does not stop when release arrow key but keeps on running( Z) v6 a+ G0 L( p% y0 O
1107132 FSP OTHER Altera ArriaV (5AGXMA5GF31C4) support.$ J# E! ?1 |: a6 B6 m" N
1118874 ALLEGRO_EDITOR INTERFACES Oblong pad shapes are not shown with correct orientation after DXF export from Allegro% d A8 Z. p. {" H! l
1121540 F2B PACKAGERXL pxl.chg keeps deleting and adding changes on subsequent packager runs
( f6 G+ o9 v2 S' _1125201 CONCEPT_HDL CORE Connectivity edits in NEW block not saved( lost) if block is created using block add% M; D% B9 [5 k3 U+ T# _9 @. H, M
1130737 F2B PACKAGERXL Error - pxl.exe has stopped working6 D {: a* T' e0 w; d
1131764 ALLEGRO_EDITOR EDIT_ETCH Line segment will not slide using the New Slide.% j6 E1 a1 @' ^; P5 l* ~( S1 F
/ ^; p0 f2 ^2 c; i, t
DATE: 04-20-2013 HOTFIX VERSION: 042
% G2 r3 k0 l; w3 S2 Z% Y; d8 ?===================================================================================================================================
$ ~" l7 }! V$ L- `- f/ z' F8 k1 oCCRID PRODUCT PRODUCTLEVEL2 TITLE
+ n7 q; \8 C; ]===================================================================================================================================
0 K9 N/ a, X1 i# @801901 CONCEPT_HDL CORE Concept Menus use the same key "R" for the Wire and RF-PCB menus' Q8 t& ~+ z5 |9 L q: P4 c
1076604 ALLEGRO_EDITOR SHAPE Sliding via in pad corrupts surrounding shape and generates false DRC Errors9 N; j1 q4 ~: G5 [# g7 Z. q
1077552 F2B PACKAGERXL Diff Pairs get removed when packing with backannotation turned on
) }4 b# @2 r! \4 ?1080386 CONCEPT_HDL CORE Unable to highlight netclass on every schematic page using Global Navigation
5 X ?9 W% ^0 C0 n S/ i: Y8 V1102698 SIG_INTEGRITY ASSIGN_TOPOLOGY ECset will map on single ended nets but fails when the two nets are define as a diff pair., U; [7 l% M" f/ o% ?/ \" G. K( Q
1104071 SIG_INTEGRITY REPORTS Shape Parasitic value changes for bottom shape for changes in top shape2 `% q# b8 C* _4 Y1 |
1105128 CONSTRAINT_MGR DATABASE Import dcf does not clear out user defined schedule.* L' Z& N: \5 V5 K
1116886 CONCEPT_HDL CORE Crefer hyperlinks do not work fine when user use double digits partitions for page Border.
/ E6 T) Z* n9 X+ I2 m- F. A: v9 R; m1117825 CONCEPT_HDL OTHER SHOW_CONSOLE_ON_LAUNCH throws an unrecognized directive warning in the schematic editor
# I$ T$ C2 i. `# C" P1117845 FSP DE-HDL_SCHEMATIC Schematic Generation fails without a reason8 w& |& i% J% _* v
1118526 CONCEPT_HDL CONSTRAINT_MGR Upreved design now has Constraint packaging errors
5 ]( r1 j$ H1 O1 ?1 F* {( d1119711 F2B DESIGNSYNC Design Differences show Net Differences wrongly
i/ C; f2 F' F& ?/ D1120397 CONCEPT_HDL CREFER CreferHDL attempts to create missing vlog004u.sir files9 @' w# E# `2 e+ ~+ Q+ ]- J
1120660 CONCEPT_HDL CORE Save hierarchy saves pages for deleted blocks." }9 W1 K: z1 A8 z! d c7 g+ D- V
1120669 CONCEPT_HDL CORE DEHDL crash on multiple replace of hier blocks; w6 z, S# R2 G3 [: Y ~
1120810 ALLEGRO_EDITOR EDIT_ETCH Cannot slide cline segment.0 F' h0 c# f4 g
1121171 CONCEPT_HDL CREFER PNN and correct property values not annotated on the Cref flat schematic
4 F6 y5 L/ `: O1 M1122449 ALLEGRO_EDITOR DRC_CONSTR Uncoupled length DRC for diff pair shows different actual length value between show element and CM.
# y% U! q" c8 m1 @: b; ] f1123764 CONSTRAINT_MGR OTHER Allegro crash while importing DCF file3 P1 y. w5 c% d
1124183 ALLEGRO_EDITOR EXTRACT Output from EXTRACTA gets corrupted with refdes 50
: @$ u8 F& J' P% E y: X, r) H
/ \# w/ V$ E5 x4 v$ a2 S mDATE: 04-4-2013 HOTFIX VERSION: 041' l* U w& D, P6 r
===================================================================================================================================$ a2 T. Y0 O: {) d+ f2 Y
CCRID PRODUCT PRODUCTLEVEL2 TITLE: n: Y9 L" W" z! b. c( k; [
===================================================================================================================================; k7 D A$ j: ^# s
835944 ALLEGRO_EDITOR OTHER Customer want to change for Jumper symbol by other Alt symbol.
1 i; @% A" Q# `0 F) I3 N988019 ALLEGRO_EDITOR PLACEMENT Allegro hangs when doing place replicate create
: Z9 P6 e8 v; w1065641 PCB_LIBRARIAN CORE PDV symbol editor is crashing when deleting a group using delete or CTRL+X
, ^( y& Y/ y9 G x9 @1073152 CONCEPT_HDL OTHER Printing Published PDF schematic has missing lines
% h9 N+ X8 b6 ^) E7 Q- y; j1082587 FSP FPGA_SUPPORT Support of Xilinx's Zync device" V2 [7 S$ {7 m1 V& o) o
1100945 SCM SCHGEN SCM generated DE-HDL has $PN placement issue
" }0 Y3 f: v2 z1 Y* M" l1107172 CONCEPT_HDL OTHER Project Manager Packager does not report errors on missing symbol( n8 v2 H% C3 ~+ ^1 r$ Q0 i
1107397 SIP_LAYOUT PLACEMENT Place Manual-H rotates die
7 p/ |8 |3 P# j7 o6 A1108603 PCB_LIBRARIAN VERIFICATION PDV Tools Verification > View Verification (CheckPlus) leaves <project>.cpm_tmp.cpm
7 i, m V6 G5 M4 p$ n1109466 ALLEGRO_EDITOR ARTWORK Artwork create some strange gerber lines for fillet.
+ }* |7 W7 U/ C0 N8 ?* X' V1109926 CONCEPT_HDL CORE viewing a design disables console window% I k3 b! b; Y B
1110077 ALLEGRO_EDITOR DRC_CONSTR Duplicate Drill Hole DRC's are not shown for Pins overlapped in same symbol unless "Min metal to metal" DRC is turned ON8 ^& _5 H) s& m9 r. |7 v8 m! O; g
1110264 RF_PCB FE_IFF_IMPORT IFF Import in DEHDL has component offset; Q! S0 p) A7 G. I0 d! E
1112295 APD DXF_IF Padstacks� offset Y cannot be caught by DXF.4 |5 Q! K5 ], D6 f0 o+ c& ?
1112395 CONCEPT_HDL CORE 璞BASE\G� for global signal is not obeyed after upreving the design to 1650.
: ?2 p9 h* p5 T/ F1112774 GRE CORE Allegro GRE not able to commit plan after topological plan- N* ^, M! D: F' ^5 Z: G( G: q
1113317 CONCEPT_HDL skill skill code to traverse design not working properly
0 X1 e3 X4 U* T2 g" a: P+ q6 U1114630 CONCEPT_HDL ARCHIVER Archcore fails because the project directory on Linux has a space in the name
0 y, `# ~1 g- l/ ]. k. J7 Q0 m- G7 p7 x1114689 CONCEPT_HDL CORE Unknown project directive : text_editor- D( J$ U) T( V4 Q# L: B7 |
1114928 F2B PACKAGERXL 激rror (SPCODD - 5) while Export Physical even after change pin from A<0> to A$ m+ C! Y6 Q5 I
1115625 ALLEGRO_EDITOR SKILL Design extents corrupted when axlTrigger is used.. l; f. i% M2 e% W3 V
1115708 ALLEGRO_EDITOR INTERFACES Export DXF is outputting corrupt data on one layer.1 G0 I. v2 q; _- c
9 w( H2 T% |% r6 W P2 W. P6 X4 Z
DATE: 03-14-2013 HOTFIX VERSION: 040% ? m1 W& y! G. y% P% n: e* V# F
===================================================================================================================================
' l, \ I( T: `CCRID PRODUCT PRODUCTLEVEL2 TITLE% F& y. W0 v+ v6 a0 a
===================================================================================================================================% e5 ^* i: L4 g8 g% M
625821 CONCEPT_HDL CORE publishpdf from command line doen not work if temp directory does not exist.
7 E# i% p7 \. \1 X% x+ U3 M/ k- ^1092933 CONCEPT_HDL OTHER PDF Publisher saves the pdf generated in the previous project folder3 c) @+ f% V( X
1096318 ALLEGRO_EDITOR INTERFACES IDF import not removing MCAD tagged objects during import8 }; z" i: c: s1 g; \. i
1100449 ALLEGRO_EDITOR ARTWORK Pad with Net_short property and shorted to shape supressed wrongly with Pad Supression in Artwork
" [5 u8 Q5 F8 G* k1103631 MODEL_INTEGRIT OTHER Model Integrity license when using orcad- k6 ]; L% d3 F+ _* v" c, E
1104575 CONCEPT_HDL CORE Allign does not allign offgrid symbols correctly
- B- R, b3 C* k* x: D4 [: j# e1105286 FSP DE-HDL_SCHEMATIC FSP crashes while creating board in Schgen if it does not find any available license.8 w% l% l% T* Y- E3 u& Q; e
1105822 ALLEGRO_EDITOR SCHEM_FTB Netrev failing with compact pin syntax# h. _" {' |% F% k; A" m3 O
1106626 CONCEPT_HDL CORE Concept HDL crashes when saving pages
3 c E# z. P7 E' n7 X1108032 CONCEPT_HDL CORE 'Find' option does not list all Components in the Design
( _4 U; k5 m$ k5 \) h/ T1108118 ALLEGRO_EDITOR OTHER PDF Publisher pad rotation messed up with flashed pad." Q$ d9 a' `7 _
1109425 CAPTURE STABILITY B1: Capture crash due to Flash; g. ]0 G9 z7 P
1111234 ALLEGRO_EDITOR MANUFACT Double digit drill character overlaps with figures triangle, hexagon and octagon in NC drill legend
! V' Q/ v" P, n4 z" v {, h4 Y
, d; S5 N" ]( n; U7 [3 [2 cDATE: 02-28-2013 HOTFIX VERSION: 039% m; `. i; U+ h% J5 p) |; Q
=================================================================================================================================== n! w8 ?3 X. Z8 J4 n* Q
CCRID PRODUCT PRODUCTLEVEL2 TITLE
! O+ u3 c% g0 M: `===================================================================================================================================
4 _# M8 R2 A( s W/ b# a0 {868981 SCM SETUP SCM responds slow when trying to browse signal integrity8 K" C* X3 w. c( }
1086740 ALLEGRO_EDITOR mentor mbs2brd: created shape are duplicated
7 t" }# c- W1 q4 l1089356 SIP_LAYOUT DIE_EDITOR Distributed co-design : launching die editor taking more than an hour to bring up edit form; X+ i% Q ^- c. @( P0 [8 k
1095701 CONCEPT_HDL CORE Replace part in replicated block only preserves the Refdes in 1st instance of the replicated block5 `( D$ l t" o z0 I7 Z: f- h
1097241 CONCEPT_HDL CORE Concepthdl - zoom in to first object in Find result automatically
0 r" N, U0 l4 N z* W: P, x$ Q7 C1099175 CONCEPT_HDL CORE CPM directive that enables the Command Console Window in DE-HDL
) ?' i* f* E- C( t$ v+ b4 }1099773 CONCEPT_HDL CORE DE HDL goes into recursive loop if a custom text locked at site level is deleted from Tools > Option2 F! C, |+ K5 L% r
1100442 ALLEGRO_EDITOR PLACEMENT Placement queue shows components whichs are already placed4 z3 w- H0 z" z- j. @ U* Y3 l/ a
1102798 SIP_LAYOUT OTHER Stream out puts offset pad in wrong position if pad is mirrored but not rotated.
+ j# z8 K) r0 r A( |1103703 F2B DESIGNSYNC Toolcrash with Design Differences3 v6 K( U; D! |+ x
1104011 ALLEGRO_EDITOR DATABASE Place replicate move group of a modules leaves traces behind* E7 U; e3 u2 J0 d
1104605 F2B PACKAGERXL Pins of function swapped part in block not displayed
6 r% ^8 l& {. K; m: \) i$ s, T" T/ a1105066 APD IMPORT_DATA Import NA2 worked in 16.5 "035" but fails in 037 and 16.66 k4 b9 j, Q" w, y* b& N4 I- L" j, W
) P1 b8 m8 T3 b7 yDATE: 02-15-2013 HOTFIX VERSION: 038
& b& A- q1 Y( E- b2 a7 Z===================================================================================================================================8 ~+ @7 R3 g( \8 V8 `- H j
CCRID PRODUCT PRODUCTLEVEL2 TITLE
5 y, r9 ^- E; ~2 X8 X=================================================================================================================================== Z8 w! ~3 Q* ^: s- n8 b$ j. a$ O
787041 FSP DE-HDL_SCHEMATIC FSP Refdes inconsistency when gen schematics
: f) `! u) M: }, }) L% X2 ?911292 CONCEPT_HDL CORE Property command on editing symbol attaches property to ORIGIN immediately" e4 h5 c- b3 h N: Y8 s- t W
995532 FSP DE-HDL_SCHEMATIC Hierarchical block name representing FPGA does not get updated in DEHDL after refdes change in FSP.
. {7 |2 V9 S' T6 G: Z1005812 F2B BOM bomhdl fails on bigger SCM Projects
( L5 k- Y2 L0 ?! l1045500 CONCEPT_HDL CORE Why Search results does not display the correct Physical Pages.
) ?, W' u* g( @! G1 ~2 u' _1059037 CIS PLACE_DATABASE_P Enable Refresh symbol libs menu in CIS explorer
' Y! N5 R( Z7 w1065636 CONCEPT_HDL OTHER Text not visible in published pdf
0 p% N T, A: d# E/ U0 {4 W# L1067283 SCM PACKAGER ALLOW_CONN_SWAP does not work for lower level schematic parts
& I, e& a* F' O& h1073354 CONCEPT_HDL CORE Bubble defined on symbol pin is not visible on the schematic
" B9 c; g6 v* h+ J1077527 CONCEPT_HDL CORE ConceptHDL net with name U cannot be found using Global navigate9 J1 ?9 i4 b3 k! @! `/ G' E6 n+ I* G) G
1083761 CONCEPT_HDL OTHER AGND text missing from PDF Publisher
z( F4 c6 N( ~1 }5 S7 d6 {1091335 CONCEPT_HDL OTHER Color change cannot remain in some situation.
! f3 x, g% e e" | p5 c1093050 ALLEGRO_EDITOR DRC_CONSTR Taper trace on diff pairs not checking to min line spacing.4 e" P& O* N0 u9 Z+ q5 c
1094513 CONCEPT_HDL CORE How to display $PNN for which SIG_NAME is not visible?% \% |8 V% r% z- n1 B! d- R
1095705 CONCEPT_HDL CREFER Cref_to_list not updated on repl icated blocks in 16.5 release worked fine in 16.3
) \9 `; n" E4 x3 P% x/ i1095786 ALLEGRO_EDITOR DRC_TIMING_CHK Allegro PCB crashes when running DBDoctor* F3 L: z6 J( g( b3 R1 B6 ^
1095861 F2B BOM Using Upper-case Input produces incorrect BOM results0 U6 ~9 c# J: V
1096234 ALLEGRO_EDITOR DFA Via pad connected to shape didn篙 show up after 燙uppress unconnected pads� option.
* S+ C, E( Q4 o3 U! T B1096313 RF_PCB LIB_TRANSLATOR Allegro Discrete Library to Agilent ADS Translator offsets in the CDNSsymbo.iff1 g" Z- ^9 C9 l5 D( |0 X: S" q
1096613 ALLEGRO_EDITOR INTERACTIV Enh-While moving parts silk ref des should remain visible h4 h# ?- @- }% l3 |& S {. ?
1096676 CONCEPT_HDL CORE SPB 16.5 HF36 breaks designs that workded fine in HF35- T& l6 ~3 N" B2 O
1096913 APD IMPORT_DATA Import > NA2 fails to bring in the Y1 component.
% {/ a" t% }7 f& y3 N7 P- q* K1 y2 \1097751 ALLEGRO_EDITOR DATABASE Import CIS netlist crashes.
/ W$ K* V9 W# ?4 G, [1097889 ALLEGRO_EDITOR DRC_TIMING_CHK Allegro crashes when routing from a via to a pin using High Speed option license.
# `) A& @) ]# }& o5 `) p+ c1098252 ALLEGRO_EDITOR MANUFACT Double digit drill character overlaps with figure "circle" in NC drill legend
! {; j( i) Z3 r9 A& e7 I1 s5 {1099151 SIG_INTEGRITY SIMULATION All Neighbor crosstalk numbers reported when there are no aggressors* l7 q' |( i/ q4 _. ]
1099998 CONCEPT_HDL CHECKPLUS CheckPlus marker file not locating signal when signal name includes the # character.* ^8 A U, {/ t0 ?
1101009 CONCEPT_HDL CORE Cursor stays as arrow after performing File > Save Hierarchy
& @! w, M) J& ^: _4 G8 {) x+ `
7 \/ @. f; c W) c, e0 JDATE: 01-31-2013 HOTFIX VERSION: 037
+ C6 k& `/ f$ [' t5 D===================================================================================================================================
, e' b' ^3 b: X: N# K- ^CCRID PRODUCT PRODUCTLEVEL2 TITLE
; L, a! u4 T& o1 j) j5 ^+ h% Y===================================================================================================================================& q5 |) M4 M p9 n# r
1067272 PCB_LIBRARIAN CORE Unable to retain the symbol outline changes5 u; N' f7 ?8 }2 X) {4 n5 x
1070465 CONCEPT_HDL CORE Why does ConceptHDL crash on renaming a Port Signal
3 D; ?9 R5 G$ E% E6 O1077728 APD EXTRACT Extracta.exe generate the incorrect result
; P. o4 x5 p, F1083934 ALLEGRO_EDITOR PAD_EDITOR Error(SPMHUT-41): File selected is not of type Drawing.
6 a. R% U* ^/ P6 V( `, F( `1084711 APD DXF_IF Padstacks with offsets cause violations in Export > DXF9 t: W5 `' P( K5 W9 ?
1085791 CONCEPT_HDL CORE Publish PDF can not output Constraint Manager properties into PDF file.
7 @2 X2 x, ]! z1086749 ALLEGRO_EDITOR MENTOR mbs2brd: DEFAULT_NET_TYPE rule is not translated
& a4 F% G3 {# u3 ~! q1086886 CAPTURE PROPERTY_EDITOR "Is No Connect" check box in property editor doesn't work for power pins ?. U7 X9 F0 Y9 W( b) Y: I, \, b4 m
1088252 CONCEPT_HDL CORE Menu commands grayed out after Save (with 16.5-s035) when launched from ASA.; _# s+ q+ J/ g; R
1089259 SCM IMPORTS Cannot import block into ASA design
& m. G v) Z6 T Q) k1089368 SCM OTHER Can't do Save - cp: cannot stat ... No such file or directory
7 S/ q3 B! N1 V; H1089605 CONCEPT_HDL CONSTRAINT_MGR Power net missing from the CM opened from DEHDL Schematic editor.
5 H* e4 s, i* a0 }8 u4 {4 V" y1090369 SIG_INTEGRITY LICENSING Impedance value not updating in OrCAD PCB Designer2 V" _( f7 T4 Y5 C _" @
1091047 ALLEGRO_EDITOR REPORTS The "Dangling Lines Via and Antenna� report seems to be missing vias that are antennas.1 D' v; B- z) @6 H: I( e i
1091218 ADW LRM LRM is not worked for the block design of included project
9 H7 g# u2 d3 J$ Y5 l1091347 CAPTURE TCL_INTERFACE The Project New link on Start Page doesn't work when Journaling is enabled
}/ R) @2 O: y. M: _3 P1091443 ALLEGRO_EDITOR OTHER Crash when toggling suppress pads
, }" o' t6 [. `2 h8 u1091662 CONCEPT_HDL CORE Incorrect behavior with the SHOW_PNN_SIGNAME directive
7 E' I" ^- P1 c: O! o0 F1092426 CONCEPT_HDL CORE Getting ERROR(SPCOCN-1993) while saving a Hierarchical Design$ q$ z! b% l( f0 n1 ]
1092874 CONCEPT_HDL CORE DEHDL wire short during move not detected with check enabled
: X3 Q% P; ?1 W( ?5 G: g6 C1093327 CONCEPT_HDL OTHER Getting error SPCODD � 369 Unable to load physical part in variant editor! }0 A$ ^: X. g* ~
1093717 APD DATABASE Design is crashing in Tools > Update DRC and in Dbcheck but seems inconsistent
' u3 _5 c3 U& d9 I1094618 CONCEPT_HDL INFRA Unable to uprev the design in 16.5: m( P* G# q( p8 r( s
1094788 SIP_LAYOUT WIREBOND Wirebond edit move command
" }7 A, S0 B0 J9 I" p
, e6 r) L6 s- K- e2 R/ \9 UDATE: 01-18-2013 HOTFIX VERSION: 036
$ ]7 i% W: ]9 I ]===================================================================================================================================3 Y1 H q2 m, `. T( ^9 U! B( Y
CCRID PRODUCT PRODUCTLEVEL2 TITLE. [3 i+ n. q1 D p+ w
===================================================================================================================================
& [' B( c/ O: p9 `4 ~ A: L) q491042 CONCEPT_HDL SECTION Prevent PackagerXL from changing visibility on SEC attribute* D1 O0 d2 O8 Y" U# v+ Z/ K
945393 FSP OTHER group contigous pin support enhancement
8 Z1 l& ^& q* ?5 [2 b1005078 CAPTURE ANNOTATE Copy paste operation does not fill the missing refdes
9 V, z! b5 D; L& `1018756 CONCEPT_HDL CONSTRAINT_MGR Match Groups with Pin Pairs are not getting imported into the schematic CM during Import Physical
* p8 h( p! j1 D: F4 v; a# |1032609 FSP IMPORT_CONSTRAIN Import qsf into FSP fails with 燕LL PLL_3 does not exist in device instance�
2 z6 t+ j4 r8 Z% N% a1071037 Pspice SIMULATOR Provide option to disable Index Files Time Stamp Check
3 P M) H' c& ~7 B- y$ S1073237 SIG_INTEGRITY GEOMETRY_EXTRACT Some nets has no result at Bus Simulation and Comprehensive simulation.
7 ^" n. |: o2 s6 P( @' Y1076898 CONCEPT_HDL CORE User can not increase logic grid size value continuously using Up button on Design Entry HDL Options
, k k! d% i! ^$ [; j1077169 APD SHAPE Shape > Check is producing bogus results.
+ E/ ^" ]( N; t5 f$ a0 G A8 b& q1078270 SCM UI Physical net is not unique or not valid" h" a' Z4 X- i4 A0 [
1078497 ALLEGRO_EDITOR INTERFACES Import DXF does not seem to work correctly.
, t; F. W3 H- l7 o; d) N2 X0 Z1079821 CONCEPT_HDL CORE Project Setup does not respect $TEMP variable for temp_dir and creates a directory in project calle
/ [: r) I( {" U: ~1080336 CONCEPT_HDL CORE Backannotation error message ehnancement& J- B( r C3 E/ |% o9 Z. b
1080982 CONCEPT_HDL CORE Crash of Allegro Design Entry during a copy of a note.
8 `$ C" ?& G" y) h" D/ b+ t1081200 CONSTRAINT_MGR OTHER In the DIFF_PAIR worksheets various Analysis seem to take a long time to complete., d: f" ~1 S* j+ `. _# K
1081553 CONCEPT_HDL OTHER Model Assignment can not translate M (Milli-ohm) property value of DE HDL.
" N5 G" B8 i: V, S5 V8 K4 k1081696 ALLEGRO_EDITOR INTERACTIV Compose shape not working when radius is set to 1.0
, R5 ~: G7 W) M s5 k( h% ]8 C6 ?( m1081760 FSP CONFIG_SETTINGS Content of 澹PGA Input/Output Onchip termination� columns resets after update csv command' D5 ~. S# X, F$ I: v
1081834 CONCEPT_HDL OTHER PDF Publisher fails crashes DEHDL
8 u- _* P9 f2 e6 V" |1082220 FLOWS OTHER Error SPCOCV-353
; g& v5 [9 E. Q+ @8 r( Y; P; w1082785 CONCEPT_HDL CORE DE HDL should clean the design with non sync properties in some automated way2 r( O! ]& T4 v) g' h) F7 W$ N
1083533 CONCEPT_HDL CONSTRAINT_MGR Bug -Net-count under few of the netclasses are not in sync between Schematics & Layout: @% k3 p- d, _6 }# [2 x, i
1083637 PCB_LIBRARIAN CORE Save As is not renaming the NAME in the symbol.css file
9 a7 ?, x# O# y; D$ L6 S; H8 C1084148 CONCEPT_HDL CHECKPLUS The CheckPlus hasProperty predicate fails in the Physical environment.) ?" N6 q: |1 p* A- V' M" J
1084285 CONCEPT_HDL INFRA Corrupted dcf was never fixed and caused PXL error
' \+ w0 G& N4 @1084441 CONCEPT_HDL CORE Assigned net property value changes to numeric
9 ~0 `' w o9 e1084542 ALLEGRO_EDITOR DRAFTING Dimensions associated with frect doesn't rotate with the symbol.8 S, E# h1 C& p
1084736 APD IMPORT_DATA Import SPD2 file from UPD-L shape Pad and text issue" Y+ U9 P- ]4 r8 c# ]- i
1085008 ALLEGRO_EDITOR INTERACTIV Relative (from last pick) option in the Pick dialog not working for pick command
: M ?" u+ X! P" s+ G1085010 CONCEPT_HDL CREFER Crefer crashes if the property value in the dcf file has more than 255 characters
! h( R( d' b6 `" N1086576 CONCEPT_HDL CHECKPLUS CheckPlus hangs when running Graphic rules.6 b& j# B3 H/ ^; X9 l4 S
1086902 CONCEPT_HDL INFRA Problems occurred while loading design connectivity( g, }& C; s5 Y4 O
1086905 PSPICE SIMULATOR PSpice crash while simulating circuit file with BREAK function
; k% d- e+ S/ i0 i; j+ d# t1087658 CAPTURE PRINT/PLOT/OUTPU Lower level design pages are getting print twice: h" m5 {1 ]( u1 o
1087770 ALLEGRO_EDITOR EDIT_ETCH Allegro crashes on a pick with the slide command.
$ M3 a6 x, C8 t* Z! d% Y1088231 F2B PACKAGERXL Design fails to package in 16.5
% r0 O4 s8 O `# S& Q1090838 SIP_LAYOUT PLATING_BAR Can't create palting Bar' O+ {& |7 R4 p
* K$ H* f5 [+ J8 Z. {. UDATE: 12-7-2012 HOTFIX VERSION: 035* s& a# h& G. m7 B# _
===================================================================================================================================
; [: }0 E5 s$ P, |5 J8 KCCRID PRODUCT PRODUCTLEVEL2 TITLE
+ l& V8 A) h! t===================================================================================================================================
6 W% q2 T% {; U/ G) I: z7 r825813 CONCEPT_HDL CORE HDL crashes when copying a property from one H block to other y0 b( |) s5 B/ ]+ n- |& U% |* U: T4 g
871899 CONCEPT_HDL CORE 'Multiple:' column of Grid window in DE-HDL option is too wide& Y# [& ?) _' ^ t9 t! F# N: j
873917 CONCEPT_HDL CORE Markers dialog is not refreshed5 I% \0 Y$ |' t1 G
887887 CONCEPT_HDL CORE Option to find unconnected Pins/Nets with DEHDL L License
$ q+ r b/ p3 p' q892857 CONCEPT_HDL CORE packager treats R? as a unique reference designator3 f) h" z& K6 @8 w) b* R
995011 ALLEGRO_EDITOR INTERACTIV Why Snap to option for Arc / Circle Centre is not working in this symbol file
' L( D5 v& q2 m9 K& N- z7 n1045863 CONCEPT_HDL INFRA Customer had the crash several times when they run script with SPB16.51.$ E3 a0 @) O% y4 q1 a1 ~
1061529 CONCEPT_HDL CORE Space can be included in LOCATION value and cannot be checked by checkplus
- @/ R6 N& ?2 k/ U" Y W, _1063924 CONCEPT_HDL CONSTRAINT_MGR Highlight the net between DE-HDL 16.5 and Constraint Manager.
, U" Y" V* p( _2 k; |! K4 O1064035 CONCEPT_HDL COMP_BROWSER Component Browser crashes on part number search using a library containing >23K parts) m4 Q5 d* g4 U3 j# {
1067339 CONSTRAINT_MGR ANALYSIS Relative Propagation Delay analysis in the Partition file seems very inconsitent.! `% ^$ S/ h( z
1067400 CONCEPT_HDL CORE ERROR(SPCOCD-171): Port exists in symbol but not in the schematic- k' h+ u' m5 n1 k" r- D7 `8 {
1067451 CONSTRAINT_MGR CONCEPT_HDL ERROR(SPCOPK-1053): Cannot find a ppt part that matches the instance
) o* s/ N/ N% g$ A. z1068878 CONCEPT_HDL CORE Rotating symbol causes the pin name to be upside down
2 z3 h2 v6 P# s1070007 ALLEGRO_EDITOR PLOTTING Export IPF omits drill figure characters for backdrill holes) }+ {, O. h3 R) [, B
1071352 ALLEGRO_EDITOR UI_FORMS Via label display option doesn't remain selected
9 y2 g6 K) T, c! e- }8 W: m5 ]1072067 APD EXTRACT When expoting using Extracta oblong pads with anyangle are abnormal ~) l& [# m; Q
1072342 ALLEGRO_EDITOR INTERACTIV Snap to Arc/circle center does not snap to the exact center in move command when moved about the symbol origin
7 A3 ?8 O2 h+ I6 A: b7 R9 Q1072691 CONCEPT_HDL CORE Customer has the crash from Run Script of DE-HDL 16.51 again(#3)
) Q7 ~' I* H+ K, \* V2 T1072843 ALLEGRO_EDITOR PLACEMENT The move command that was present in the right mouse pop up menu during manual placement is missing in 16.5
- z& {) O$ d7 }( G; o1072859 SIP_LAYOUT DIE_EDITOR padstack selection window crash from Die Editing: Component editing of Co-Design Die2 y/ V" j5 `/ R! P/ W7 u
1073745 CONCEPT_HDL CORE Import design fails/ H4 R9 g9 E2 u
1073852 ALLEGRO_EDITOR INTERACTIV While doing a Copy Via use the last 'Copy Origin'( p: [. ~ z8 T, E2 g
1074791 CONCEPT_HDL HDLDIRECT User gets port exists in schematic but not on symbol message even though the port does not exist2 Z. ]1 o8 k- h" @! }* I( o) l
1075151 ALLEGRO_EDITOR SHAPE Cannot change global shape parameter back to thermal width oversize after having used fixed thermal
( K& Z3 h5 Z5 w5 t1075256 ALLEGRO_EDITOR OTHER Import > IPF in 16.5 is dropping data.9 _" L |' n% t" H
1075587 CONCEPT_HDL PAGE_MGMT Unable to insert page in schematic
3 D- q( s3 l$ n# Y- a3 B1 r1075622 CONCEPT_HDL CORE PDV Edit Symbol in DE-HDL all editing functions disabled since Hotfix 33
- D0 Y$ m7 F& X1075964 ALLEGRO_EDITOR SHAPE Shape voiding is not consistent in conjunction with odd angle and arc traces
/ U0 p9 x! v0 M1076086 SIP_LAYOUT IMPORT_DATA missing wirebond after import SPD2
( n9 ^4 y/ k9 }( o& t) a2 h7 R1076117 PSPICE PROBE Copy & Paste text/label in probe window changes font size and later gets invisible
' e0 w- ^& X4 h# g1076538 CONCEPT_HDL CORE Property visibility changes in attribute form not updated in schematic canvas.* A& H |4 ^3 g( D5 G# N" ?
1076566 ALLEGRO_EDITOR EDIT_ETCH Sliding diff pair cline that has a min/max prop rule displays the HUD meter inconsistently.$ E6 L6 p: s! B8 I
1076655 APD DXF_IF Dxf does not get offset value if die symbol padstack has offset value
2 E. k: C, `( G5 M4 R1076909 ALLEGRO_EDITOR DRC_CONSTR Allegro crashes while placing modules from database
. k; I; S7 p* m1 s1077026 CIS LINK_DATABASE_PA fonts changes while linking db part in 16.5, {1 ^) } {' ]: @* L
1077621 CONCEPT_HDL CORE DEHDL crashes when saving page 3$ P, |! X6 Z6 ?1 C$ L
1078103 CONSTRAINT_MGR OTHER Updating of Bus Group by Importing an Updated DCF file fails in first attempt and suceeds on second.2 a6 a' e5 R. z5 N9 \# I
1078380 SCM OTHER Custom template works in Windows but not Linux
% N W, r! m' R, \3 W s9 V1078682 ALLEGRO_EDITOR DRC_CONSTR Unaccetable slowness with Slide: p6 R- L/ }/ J+ g: a# ^2 C
1078688 F2B PACKAGERXL ConceptHDL crash immediately after Packaging* c4 ~9 S1 Y7 { i/ u3 C4 q
1078700 CONSTRAINT_MGR OTHER The cmdiffutility is failing when comparing 2 different .dcf files.. q- ^8 c3 H. R' Z( q: w7 U
1079068 CONCEPT_HDL CORE DE-HDL crashes on upreved design when loading specific pages and having directive SHOW_PNN_SIGNAME '& v8 p) k6 ?2 ?
1079400 ALLEGRO_EDITOR OTHER desired angle vs. max angle for fillet) t6 c) c5 L y$ l: N; z
1079616 CONSTRAINT_MGR CONCEPT_HDL Packager error in 16.5 which is resolved when system is re-booted, U) W3 q6 V0 D; q6 g
1079778 PSPICE SIMULATOR PSpice crash with RPC Server Unavailable Message
0 }2 u* {4 {, U2 x; z, X3 k, T0 {3 z# k- {) T+ ^
DATE: 11-22-2012 HOTFIX VERSION: 034( j3 L, ~( V+ R8 M" Z2 w
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CCRID PRODUCT PRODUCTLEVEL2 TITLE) a; Z4 ?/ ?3 J; _5 V
===================================================================================================================================
/ c9 ^* L, ]. M" b" ?871886 CONCEPT_HDL CORE Browse button in Signal Integrity window of DE-HDL option causes program crash$ S" J) F5 ~; l2 X I. [
1030890 ALLEGRO_EDITOR DRC_CONSTR High Speed USB Switch model/ x7 X8 a/ e2 _
1063658 ALLEGRO_EDITOR SCHEM_FTB Allegro Import Logic does not remove library defined diffpairs
6 ~7 m" u0 d5 `1069915 ALLEGRO_EDITOR EDIT_ETCH Allegro hangs with when doing spread between voids
: H, [ u& h! ~0 k0 W% l9 L( o s1072791 ALLEGRO_EDITOR DATABASE Database check cannot fix error and keep report the same issues cause artwork cannot export.
4 Z7 e% A; L! G1 F" r9 Y7 w1072904 SIP_FLOW SIP_LAYOUT Probe pins not being mirrored in Die Editor correctly in Chip Down mode.' D; d7 X! i3 e7 B0 H, Y9 l+ T
1073464 SCM SCHGEN Schgen never completes.
9 X2 J3 L/ C1 l# [5 m7 Z9 }1074279 ADW DSN_MIGRATION Design Migration fails purge if there are cells with BODY_TYPE
2 f! U5 F9 P( j* H# Z1076202 ALLEGRO_EDITOR EDIT_ETCH Allegro add connect causing crash after Hotfix
4 m' I/ j4 J" l- e6 p
" [- i/ V( z# {$ K8 L4 d: mDATE: 10-31-2012 HOTFIX VERSION: 0334 @ J8 b& w6 L/ c" T! j! Q" k
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CCRID PRODUCT PRODUCTLEVEL2 TITLE( T7 L. t0 a! O( A" k
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' p! r/ g4 d9 }2 F/ K; J103395 COBALT-COMPILE COMPILE et3compile fails if compile for 3 boards in 32bit mode
$ J$ `7 K O& D715653 PSPICE MODELEDITOR Change in pin number assignment with model import for capture symbol! N2 V+ ^( E" k- r1 m4 _; j3 R z
745682 CONCEPT_HDL CORE Attributes window requires resizing each time DEHDL is launched
* q, G9 i" Q, h) x: `825846 CONCEPT_HDL CORE The module_order.dat file gets corrupted
8 g' f4 j/ f5 q( N1 L# l, T846658 CONCEPT_HDL CORE About Change the NOTE with DE-HDL
5 Y S7 q0 j4 q& x1 G938977 CONCEPT_HDL CORE Properties attached to standard/DRAWING symbol does not propagate to parts placed in the schematic
$ A5 Y& g( C5 l3 R) ^5 B( ]942044 CONCEPT_HDL CORE ConceptHDL crashes while opening the AMS project5 G M1 V, Z8 {* I) {" v
946640 CONCEPT_HDL CORE Import Design should inherit module order defined in the imported block4 K# G& U- v9 C, I
968646 ALLEGRO_EDITOR EDIT_ETCH The Cline to Pad spacing not followed for Multidrill pad it is more then minimum spacing
' T& _$ m$ L- n4 L969535 CONSTRAINT_MGR SCM ASA retains information in the DCF file for parts/blocks that have been deleted and this causes problems.0 u8 y! x; z6 C1 e
976723 ADW MODEL_MANAGEMENT SI DML Model has to be provided the Auto Generate function for discrete components on DBeditor5 m* l* W" Q( p2 Q; W
981767 SCM UI Add series termination in ASA will crash if both output and input pins are selected.3 ~( `5 i+ }4 F' U
988355 PCB_LIBRARIAN CORE PDV moving line-dot pinshapes left to right or visa versa places pintext wrongly
4 n) s9 m4 X: t988438 CONCEPT_HDL CORE Visible constraint disrupts MOVE command
0 L6 W& W+ `% _8 M4 l6 y993562 CONCEPT_HDL INFRA After upreving the design save hierarchy is leading to WARNING(SPCOCD-34).9 c- _* K' x% d
996577 SPECCTRA ROUTE Specctra not routing NET_SHORT connections
& T/ K+ t. q Q" z4 P6 D* _997992 CONCEPT_HDL CORE Why are Page Numbers not enumerated correctly when multiple TOC Symbols are used?
: y, m5 x! |+ e1001300 PSPICE MODELEDITOR BUG: Simserver crash with encryptedm model: Q/ b& T, W% C) o8 \; `8 \3 h4 B
1006400 SCM OTHER Incorrect warning in SCM due to way voltage value is stored in tabular and schematic blocks
6 y6 e& i+ W2 B- ]3 H" j# p1011502 CONCEPT_HDL CORE Undo has an error on circle in DE-HDL during create a schematic symbol) y: D; Y4 P/ U' a
1011798 ADW LIBDISTRIBUTION generate a differential report on parts in DB vs parts in PTF while running lib_dist
/ E/ }7 L+ `# C- V1012685 SIG_EXPLORER INTERACTIV SigXP: traceEtchFactor value is not used.4 }6 l7 U& t6 p/ R0 r
1013656 SCM OTHER create diff-pair should honour diff-pair setup or ask user for positive negative leg6 X4 e v: S0 _0 p2 m. w0 A
1013721 ALLEGRO_EDITOR EDIT_ETCH Routing near a 2x3 multi drill padstack does not maintain the spacing constraints.2 ^6 _( t3 U* h; m0 `( A
1014319 CONCEPT_HDL CORE renaming HBlocks leads to crash
* C: A! u" d, m0 m# R* C1017724 ADW TDA TDO update should force the schematic to re-read data from disk
4 t, u# B S# T" K1 p1018506 ALLEGRO_EDITOR INTERACTIV Edit copy with retain net of via will assign net to pin& V0 b' p* p6 K: Y% a P. g
1019979 SIG_INTEGRITY LICENSING extracta batch command result is incorrect
& k$ R1 k0 q1 R6 D9 Y: \4 ^& S1020746 CONCEPT_HDL OTHER PDF Publisher tool behavior inconsistent between OSs
' s; B: L+ D$ @1 a9 Y$ q1023051 SCM UI Wrong and incorrect message is generated while adding connectivity in SCM matrix view � DSTABLE-140/ _; J( S( ]! Z2 o3 u$ l. C' N5 K
1023057 CONCEPT_HDL CORE Strange message when opening DE-HDL - INFO(SPCOCN-2055)7 W4 ~' L5 x& I7 h8 z9 B' c
1023281 PSPICE AA_PPLOT Bug spice advance analysis parARMetric plotter stops after 6000+ runs
2 n: u m3 i1 t0 c: ]5 h5 i1023702 CAPTURE GENERAL ORCAD Capture/CIS copy and past page to other design Issue
* k3 l" I2 X; u# x0 K" O1023807 SPECCTRA GUI Unable to close SPECCTRA using File > Quit or by clicking on standard window red close cross button- F" }; s2 N# I
1024890 PCB_LIBRARIAN METADATA con2con -metadataonly does not find footprints
* F4 j: L: s8 k) q6 v0 Y1024899 PCB_LIBRARIAN CORE PDV symbol pins grid select all does not respect the filtering( j' C/ I. W0 k7 ~6 l
1027147 CIS UPDATE_PART_STAT CIS gives ERROR(ORCIS-6274) when updating Part status from Part Manager
$ A) s/ N" Q$ E1 B1028237 CONCEPT_HDL HDLDIRECT Error binding design when generating simulation netlist
; w3 o) L( D- B* c1028432 SIP_LAYOUT DIE_ABSTRACT_IF Support pin numbers in die abstract flow8 G- F* z. V b6 @" c7 D
1029369 PDN_ANALYSIS EMVIEWER EMViewer: Unit of Current Density.# \" W. a" s0 @: J! ?2 T2 U( _4 ?+ u. z
1030591 CAPTURE LIBRARY Library Correction utiltiy locks the library and deosn't frees it even after being closed
. Y3 @& a+ j$ a) X8 r5 V( ?1031474 CONCEPT_HDL ARCHIVER Uisng Gtar as the compression utility causes the 'delete archive' to fail4 h) g! p; a- g6 | x8 q
1031765 PCB_LIBRARIAN OTHER librarian_expert feature is kept checked out for two hours/ D, \, P; d$ G3 j1 i0 t
1032703 F2B DESIGNVARI Enhancement Replace Variant Component form needs to be resizeable
2 X& G5 r# f: V/ }- O+ s8 R1033607 CAPTURE NETGROUPS Capture crash if netgroup instance name has square bracket 璟�
) l* n2 {2 ~5 h9 T" B; x1 n1033853 SIG_INTEGRITY OTHER netrev crashes when importing logic
& i# U' _1 }1 E/ W9 J. S1035624 CONCEPT_HDL CORE Options pre-selected when launching base product
+ `; L2 J9 |0 T% ~8 `' k. F j1036580 ALLEGRO_EDITOR MODULES Module created from completely routed board file has lot of missing connections in it., m3 J7 E; j& J- @3 F; \+ F
1037345 ALLEGRO_EDITOR INTERACTIV Enhance Allegro's Snap-To tools to select the origin of a sub-drawing(clip file)% s, i T6 f( n1 K$ x5 s& \
1038180 ALLEGRO_EDITOR DRC_CONSTR BGA escapes not being calculated in phase tol
8 r( z, C1 N! W$ V; {1038285 SCM UI Restore the option to launch DE-HDL after schgen.
0 q- y* p! w' i" h9 s1039147 ALLEGRO_EDITOR COLOR Need an option to change color of Text marker and Text select in Display listing# _7 Z6 a% ~: G; B
1040257 CONCEPT_HDL INFRA New license files causing slow tool performance
$ u2 W! M3 _& v0 h1 E1040575 CIS CONFIGURATION SQL database views are not visible in CIS configuration step 2.0 l$ W* e8 C/ b2 @
1040678 ALLEGRO_EDITOR MANUFACT Text spacing is inconsistant for top and bottom SM layer in xsection chart8 @4 p! ^# M3 U* D! t
1040869 CONCEPT_HDL INFRA About uprev problems to SPB16.5 from 15.77 @% t2 O- g+ n% @9 E0 U, P( I
1040976 PCB_LIBRARIAN CORE PDV replace pinshape on Linux shows very slow performance compared to Windows5 H8 p/ J3 z1 a0 Z" M
1042603 PSPICE SLPS About SLPS simulation interrupt8 A% U- Z! Z' I" n$ t
1042695 CIS CONFIGURATION Can't see database views of an SQL database in CIS configuration
5 e& f$ o1 B1 s! b1043339 CONCEPT_HDL PAGE_MGMT The .con and .xcon files aren't being updated.
. G0 D. H4 z) |* S* C' @! C* W1044029 PSPICE ENCRYPTION Encrypted lib not working for attached
7 K; I* K" N+ S8 d( n1044222 ALLEGRO_EDITOR INTERACTIV Capture Canvas Image changes working directory
3 C4 g% @! ?! g& f' c$ t1044264 PSPICE SIMULATOR Why does the 'ORPSIM-15009:This device scales to 0.0 at this Temperature' Error occur.
+ c( Q5 J3 ?" E; [8 r2 o0 T1045607 ALLEGRO_EDITOR OTHER Component get placed even after Cancel IDF in form.
# J. p0 P3 g' y) p) l4 n: z0 N1045609 ALLEGRO_EDITOR PLACEMENT Statement in the Viewlog for Update Symbol needs correction
" s; ]2 U5 M n! ?/ W K P7 ] @) P1045694 CONCEPT_HDL INFRA Why to package the design twice to pass the net_short property to the board?
( r) G6 J. k, T2 L* `2 Y @1045734 ALLEGRO_EDITOR OTHER Missing padstacks and layers information in cross section chart3 S% M7 l+ P }+ h
1046929 CONSTRAINT_MGR OTHER Unable to create physical of spacing cset after rename the default cset in design entry.
6 l2 l+ ?' N" E" h1047361 CONSTRAINT_MGR OTHER CM fails to convert static phase tolerance value to database units.
* L% B& Y3 ^; Z& [2 b1047756 CAPTURE NETLISTS Not adding user defined properties in netlist generated by orDump.dll
( F4 ]- e3 u* @# @1047823 CONSTRAINT_MGR OTHER acPutValue predicate text not being displayed at bottom of Constraint Manager window.) O0 i. F: I4 U8 v1 E
1047869 CONCEPT_HDL CORE How do I define a custom pwr/gnd symbol for correct Verilog syntax?
7 \; D4 N' B/ x2 E1049303 CONCEPT_HDL CORE Block rename deletes schematic data immediately in 16.5& ]! U" v8 n" f( y) g4 E N
1049317 CONCEPT_HDL OTHER bomhdl with scm mode not working on RHEL in 16.51 E* D. ~8 }3 Y" M5 F
1049399 SIG_INTEGRITY OTHER Toggling z-axis delay in CM shows the same value7 }+ y. C* h7 |% c. K
1049993 ALLEGRO_EDITOR EDIT_ETCH Loss of Y axis when adding via in manual group routing9 D* i2 M5 {; L
1050483 ALLEGRO_EDITOR DRC_CONSTR DRC has been waived but after updated DRC system generated a new DRC.
! t3 ?5 P9 Q; B% r4 w+ j+ G1051588 ALLEGRO_EDITOR PAD_EDITOR Pad_Designer library drill report omits some drill holes5 K$ n- }* A+ D. m+ j
1052005 SIG_INTEGRITY OTHER Huge difference in Z-Axis delay with the latest hotfix for 16.5 that did not exist in older ISR's of 16.5.
I: @, V7 r* A' U1052056 ALLEGRO_EDITOR PADS_IN Pads to Allegro translator fails with error message " ARSE ERROR: Wrong label format:Translation aborted." R- W$ m( [- z9 j: y! b& m+ `& S
1052449 CONCEPT_HDL COPY_PROJECT Copy Project does not update all relative paths in the cpm file/ ?! ?9 a' C" |% n) [; p) p8 q
1052479 PSPICE PROBE Cursor2 (Y2) displays the same value for all traces
; l+ B/ V5 `# L9 B1052753 ALLEGRO_EDITOR DRC_CONSTR Allegro showing soldermask drc only when the symbol is rotated.7 |( u9 g; O% z
1052817 CONCEPT_HDL CORE Getting packager error after renaming nets
/ @; v# F5 B! f" C5 Z1053319 CONCEPT_HDL INFRA Change in property scope in windows mode is not retained+ q, u$ q: B# V8 y2 u2 d
1053602 CONCEPT_HDL OTHER Using the attached .NDX/DML files causes a lot of delay in invoking Tools > Model Assignment.2 m/ [8 J- F6 _* U
1053660 CAPTURE PROJECT_MANAGER Find Part Pin name or number is not working
% Z7 e' A2 w" Z; |( G1054010 CONCEPT_HDL CORE MAKE_BASE
1 F! v8 j$ Z d8 A1054235 ALLEGRO_EDITOR PLACEMENT Cannot place alt_symbols for mechanical parts.: C! i$ c$ |0 J4 ]( Y
1054846 CAPTURE PROJECT_MANAGER Crash on pressing Esc key- U& S* ^, Z; b+ y
1055328 CONCEPT_HDL COPY_PROJECT Project Manager - Project Copy6 x9 r: ` D* P4 G2 V
1055729 CIS GEN_BOM Standard CIS BOM per page is not working correctly with option Process Selection" E& G5 l! r4 x) ^( p/ f8 S
1056418 ALLEGRO_EDITOR OTHER PDF exports the blank text markers whether or not the markers are visible.
$ y& [ F, g4 [$ k# X: a8 ^1057003 ALLEGRO_EDITOR SHAPE Z-copy to create RKI does not follow board outline
0 N" R) n$ }0 @9 v: P1057976 ALLEGRO_EDITOR DRC_CONSTR No Same net Spacing DRC on attached design.
3 g: H& D7 k( {1 M# j1058364 ALLEGRO_EDITOR SKILL axlTransformObject() is moving refdes text when only symbol pin is selected for move
* a# b, e a3 f/ ^% `1058940 ALLEGRO_EDITOR INTERFACES IDF(PTC) out command output wrong angle value, E( Y% l/ E% B6 m. E( ?2 {
1059901 CONCEPT_HDL CORE Global Property Change and <<OCC_DELETED>> property value.4 ?' J9 e2 x0 E% w6 ~; o
1060428 CONCEPT_HDL CORE ADW Flow Manager Copy Project fails to complete
) C' s9 z# ~! J* Q P" r4 y1060589 F2B PACKAGERXL Packager Fails with ERROR(SPCOPK-1053): Cannot find a ppt part that matches the instance properties.
! h* N8 j7 N9 W1 b! L1061172 CONCEPT_HDL CORE Unable to delete Voltage- }. D" k2 ~' A. q4 c
1061424 CONCEPT_HDL CORE Customer creates <<OCC_DELETED>> property values.
1 h7 B/ L. [* o# Y1061659 ALLEGRO_EDITOR DATABASE Unable to return drawing origin to 001 y, U, ~( ?7 t0 A
1062532 CONCEPT_HDL CONSTRAINT_MGR Our customer saw different DIFF_PAIR contentsevery time they invoke the Constraint manager.
/ \6 X1 p) `# q& H2 D! ]1062558 APD DXF_IF If set both in X and Y offset DXF only get one and not get absolutely value in 45 degree rotation( y' A# S2 J" }) G' W: B, X! U
1064707 CONCEPT_HDL CHECKPLUS Rules Checker core dumps on design
0 Q8 o1 O, A4 i1 J0 \% q1065124 PCB_LIBRARIAN SETUP PTF properties cannot be deleted from the setup in PDV
! |1 N' `9 _$ W& e1065745 SIP_LAYOUT DATABASE The logic assign net command crashes the application9 L* k) `& [& v1 A# O( d- u, Z8 F
1065860 ALLEGRO_EDITOR REPORTS Design crashes when running a padstack usage report& j" ?3 K" I' \& w' ^6 I- j8 m
1066051 ALLEGRO_EDITOR TESTPREP Auto Testprep generation creates TP with Testpoint to Component Locatin DRC* L% X7 E9 F1 d9 ?* F4 L
1066318 CONCEPT_HDL CREFER Issue with LOCATION visibility in flattened schematic$ ~4 f% @( A, X* k
1068425 F2B DESIGNVARI Out of memory message in Variant Editor while 盧hange properties� command+ K& g# s! V S
1068966 SIP_LAYOUT DRC_CONSTRAINTS DRC update aborts on this design with ERROR -3000067
' W# \3 z- z/ w1069215 CAPTURE DATABASE Capture Crash on usnig a TCL utltiy to correct design
7 ?" v0 j# m- M1069517 SIP_LAYOUT DIE_EDITOR change die abstract pins tab default action from delete to modify0 ?* r, I- M# Z8 v0 ?: j
) G& p! J z& u8 q' EDATE: 10-17-2012 HOTFIX VERSION: 032
: ]( {7 e2 T0 T& q* x! T/ G) ?===================================================================================================================================2 _3 u8 F n" n) {1 C8 p' |3 G
CCRID PRODUCT PRODUCTLEVEL2 TITLE
+ ~: j! [# \. U1 w: C" a k0 W* r6 s===================================================================================================================================* X' K) k& s' {$ E
1052455 RF_PCB DISCRETE_LIBX_2A RFPCB IFF Export to fix port direction for ADS for footprint having the same pin rotation$ `$ Y6 Y/ k/ g @ r1 |, w
1061223 CONCEPT_HDL CHECKPLUS What determines a passthru pin?
0 Y. c4 p m' F( j2 C4 M- K0 a9 i1061817 ALLEGRO_EDITOR DRAFTING Delete dimension vertex crash0 |1 \# d$ m! B3 |3 i! o7 ~3 i
1062982 ALLEGRO_EDITOR MODULES Module containg partitions has been imported to the main design and cant be refreshed.
3 J% s9 b7 H: c& q1063284 PCB_LIBRARIAN OTHER PDV Save As is broken' ^% F+ R+ y) F2 \8 z) t. x. M8 z
1063778 CONCEPT_HDL CHECKPLUS The hasSynonyms CheckPlus predicate is not returning true for all global signals.+ z/ V$ g' I* q5 }, |+ P) q& T* @
* u3 I- s, ?$ KDATE: 10-5-2012 HOTFIX VERSION: 0316 t F `' B h& p! Z8 _, Z
===================================================================================================================================
' g" G# {/ n4 e1 N" m0 g: z0 WCCRID PRODUCT PRODUCTLEVEL2 TITLE( X) \* J% T! n5 y+ }2 P9 D
===================================================================================================================================
+ P: {; E$ }% j' H; Y3 Z. P1044754 SIG_INTEGRITY SIMULATION Incorrect waveforms when simulating with stacked die
6 w8 I! m# ?7 w" p1053631 FSP DE-HDL_SCHEMATIC SchGen doesn't place DiffPairs together on the symbol1 q3 M d7 d2 ^7 U$ f! A' S
1054456 ALLEGRO_EDITOR MENTOR mbs2lib incorrectly translates refdes label& p. ~/ N9 y# ^2 F
1054871 CONCEPT_HDL CORE Problem with creating schematic from block symbol ~$ Y3 _% B' H
1055481 APD SHAPE keepout does not clear shape unless it's picked up and dropped down
+ f# d$ g: \, ^4 b W
8 b g7 Z N4 e+ y" ?DATE: 09-21-2012 HOTFIX VERSION: 030
5 R5 {) k) `4 s& ] L' H===================================================================================================================================! K T& ~" n5 X% H8 O+ Q
CCRID PRODUCT PRODUCTLEVEL2 TITLE
8 W+ R: w7 `/ k. W h) e===================================================================================================================================, f$ W: @( G6 \5 d
1008113 FSP VIRTUAL_INTERFAC importing Altera constraints verilog to make virtual interface only small percentage of nets have IO standard( @' W0 T% L4 e4 G+ H+ C0 y1 m* S
1042199 SIG_INTEGRITY SIMULATION Waveform list was not refreshed by switching tab.
% F6 A5 A* y" w0 g1042348 SIP_LAYOUT STREAM_IF GDSII export includes the full refernce path, breaks CATS flow
0 @) a( Y; S) W+ A1 O8 h1046527 ALLEGRO_EDITOR INTERACTIV Display Segment Over Void not working correctly.1 W+ _. ] y3 o9 X! J5 o+ L
1047590 ALLEGRO_EDITOR SCHEM_FTB Buses created in Allegro-CM are deleted by netrev in traditional flow
1 M% I l& e4 F; N) Z" T% k" M1047969 ALLEGRO_EDITOR NC Some route path missed in .rou file.8 M3 n, W% `9 i! K
1048907 ALLEGRO_EDITOR OTHER PDF_OUT is very slow- K6 b$ L- v2 ?8 ]
1049262 ALLEGRO_EDITOR OTHER APD and extracta crash owing to Wirebond." q1 Q# D6 @% Z ~+ k! n
1050408 APD DXF_IF Symbol has 45 degrees rotation in mcm but DXF doesn篙.) j+ z. [5 y/ s- f
1052045 ALLEGRO_EDITOR OTHER Bug - Thermal relief connects not sustaining 15 degrees component spin in version 16.5 unlike v16.3
0 j4 h( `, |7 d5 C' q4 N/ p8 Z8 p1052600 ALLEGRO_EDITOR SHAPE Adding a specific cline causing shape errors6 d& L! ^% I2 \# r$ k3 X! B* U
1053065 MODEL_EDITOR GUI The About ModelEditor form indicates an incorrect version.
4 `, V# a% y Z1054008 CONCEPT_HDL CONSTRAINT_MGR Out of memory error while launching CM within DEHDL
- S: r8 }" e8 i3 b1 d9 E$ M0 u1054269 ALLEGRO_EDITOR MANUFACT Backdrill Setup and Analysis crashes on attached design" v3 [3 F" _5 R' H6 ]; J
1055273 ALLEGRO_EDITOR INTERFACES DXF exported from Allegro has an offset in pad location for Y- direction.
8 }) t* B0 X" ]' O& R4 z& |. p( N
DATE: 09-8-2012 HOTFIX VERSION: 029
4 \6 i! M! f/ i) T- P===================================================================================================================================3 z; K( X. O4 \+ w
CCRID PRODUCT PRODUCTLEVEL2 TITLE* X* M% b% F, ]: b
===================================================================================================================================
! X0 e! c: i: [# f2 J/ i" `961420 ALLEGRO_EDITOR PLACEMENT Regardless of the aspect ratio for room of side The QuickPlace by room command could be placed comp
$ ]2 k' v! }0 l1011470 FSP GUI Multi cell selection does not show the last cell selected
3 n" W, D6 Q) Q1 u9 c1011487 FSP GUI Ability to insert text directly in 激dit Group > Group Description� field; q; s4 W" N7 o* j
1035134 ALLEGRO_EDITOR DRAFTING Placing mechanical symbol in a board drawing changes the dimension+ @: P. H, ^2 \. l
1038186 ADW LRM CPM Option to supress the Sheet Content Mismatches during ADW _ImportSheet' r& C, e+ V( ^
1043325 CONCEPT_HDL INFRA Incorrect bus members in CM4 Q: X" w8 d4 M
1043903 GRE GLOBAL This design crashes during planning phases in GRE.
! c2 g& p7 |9 j" z8 z# ^1044230 ALLEGRO_EDITOR SHAPE Fillets are causing spacing clearance larger than the defined value in CM
, {7 `; Y0 Q4 A+ M: F7 M1044577 GRE CORE Plan > Topological either crashes or hangs GRE
; n2 K) T% Y& P/ V8 \1046113 CONCEPT_HDL EDIF300 EDIF creates a 0 lenght c2esch.edif file
# q$ G: T2 @" D1 S* F9 [; q/ R8 f# U1048291 CONCEPT_HDL CORE Incorrect ERROR(SPCOCD-569) generated in 16.5/ f8 T8 H, n/ l& s2 c& W
1048403 ALLEGRO_EDITOR SKILL Allegro crashes opening more than 16 files with skill# V% s9 r _0 V+ k
7 E. h* A% H5 B8 m7 }DATE: 08-23-2012 HOTFIX VERSION: 028
! J c1 T4 J4 P0 k' K2 n8 {- o: D8 ?1 Q===================================================================================================================================
$ X3 u' [1 k2 j K9 E F& c. ]' XCCRID PRODUCT PRODUCTLEVEL2 TITLE
/ @$ n% v9 W4 t; F1 c0 ~5 M; X===================================================================================================================================
; ^" D, z8 F* s4 A' j320014 ALLEGRO_EDITOR EDIT_ETCH Differential pair fail to Slide together
" c2 V. f9 n* y# J8 L400672 ALLEGRO_EDITOR EDIT_ETCH The Diffpair rule is disregarded because of the insertion of Via.# F0 P5 w; X* B9 r. W6 t
448641 ALLEGRO_EDITOR EDIT_ETCH Diff pairs do not slide when the xnet is broken
- W" Y9 h) q! x* }# [, E501605 ALLEGRO_EDITOR EDIT_ETCH Diff Pair Sliding problem
! u, C4 J$ s/ O8 d2 e731162 ALLEGRO_EDITOR EDIT_ETCH Slide and Delay Tune on Diff pair tunes only one net when Single trace mode is not ON.
* b5 ]; ~4 ~& X1 B, o; x967082 SIG_INTEGRITY SIGNOISE signoise command didn't use Frequency set on Net.! D' L. }( u( m
979958 SIP_LAYOUT ASSY_RULE_CHECK Running Assembly Rules Check on sip causes a crash
$ s; b. Q$ G- N P' O/ l984604 ALLEGRO_EDITOR EDIT_ETCH Error when trying to split via stack. m# w `3 t# K8 P5 h( l
988446 APD OTHER Beginning layer regular pad cannot change to Null.
5 m$ g* f, @7 g% y3 e% A: @6 d995108 ALLEGRO_EDITOR GRAPHICS Strange unexpected lines show across the oblong padstack: x/ W! O7 Q+ i& B* ^
1021557 RF_PCB DISCRETE_LIBX_2A Translator dxlib2iff lists cells alphanumerically inverted.( a0 q; P0 Q! @! ^9 `
1021568 RF_PCB DISCRETE_LIBX_2A translator GUI not listing library cells alphabetically in Linux/Unix3 Y, l; j# e. r2 J
1024239 ALLEGRO_EDITOR INTERFACES DXF pin location is moved when I execute DXF out* K# g5 M) B w. {# _" H/ b: d
1039112 ALLEGRO_EDITOR ARTWORK Antietch and Boundary layers deleted when Match Display selected% Y) E6 c1 |7 i6 w. M6 ^
1039751 SCM SCHGEN SCHGEN is bunching voltage flags together to the point they're illegible
- x6 d8 Z) Q8 f3 H% u/ ]; |* r, u1040584 ALLEGRO_EDITOR GRAPHICS After installing Hotfix 16.5s026 3D viewer has been impacted.. q+ A. E7 u. [
1040653 ALLEGRO_EDITOR DATABASE Cannot update netlist data, ERROR(SPMHDB-121): Attribute definition not found." t! S& m' ]3 i5 R' a4 G# B
1041368 APD DEGASSING The Degas_No_Void properties assigned to Cline does not work.
4 O* l. T* @. Y( w* @ c- b( n1041864 ALLEGRO_EDITOR MANUFACT Allegro crashes when opening the Backdrill setup menu( r- c+ n$ Y& x0 A# m4 G
1042004 SIP_LAYOUT DIE_STACK_EDITOR Moving die pad layer from top to bottom of package is not change the die stack side
4 g! i) G2 _. q! ^& B0 E4 n1043777 ADW COMPONENT_BROWSE ADW UCB must support hyperlinks in Database Mode like we do in Non-DB Mode3 Y P2 w2 S" p% B" O3 ]& p
1043861 SIG_INTEGRITY REPORTS Derating values are NA in bus simulation report when derating table is not in working directory
# q+ E/ q9 [& i$ [* Z8 K r; Q8 v2 g: J8 w
DATE: 08-9-2012 HOTFIX VERSION: 027
5 _) B* ]/ `7 x- b' A5 b===================================================================================================================================# M6 Q3 `9 @4 N" u7 F% v% g
CCRID PRODUCT PRODUCTLEVEL2 TITLE6 _/ I7 U4 y, n5 S# z
===================================================================================================================================
) d) f& E1 x7 l- X1005030 FSP OUTPUT_GENERATIO About the CSV file of Generate PlanAhead Script command
2 y! V8 |8 Y; n1021870 CIS CONFIGURATION CIS not accessing a database with table name having '&' character
1 s/ V$ Y4 ?! j; }1 `4 Y% K1022902 RF_PCB DISCRETE_LIBX_2A Allegro to ADS translator crashes on libraries! Z- N5 a+ x5 o% }, M4 o) P
1035077 CONCEPT_HDL SKILL ConceptHDL crashes during skill execution
# X1 c5 d$ O$ U' u/ U `1037325 CONCEPT_HDL COMP_BROWSER Parse error when reading shoppingCart.xml with PTF value containing "&"( `1 Z* q7 l {$ H2 ^$ ]# a
1038063 ADW LRM Global Property(CLASS) wasn't updated after LRM updated.
! j; x& [. C$ z' X
9 D s* W! K) x5 d) q6 O* Q# i3 ~DATE: 07-27-2012 HOTFIX VERSION: 026' L+ e9 u/ V1 X0 f
===================================================================================================================================
) D- {- t. A9 s ?9 I# F9 `' j* G9 U1 ^CCRID PRODUCT PRODUCTLEVEL2 TITLE, n5 n( C, M+ q! H8 c
=================================================================================================================================== U8 _4 j4 D3 F; g
841657 FSP DE-HDL_SCHEMATIC All ports of virtual interfaces are inout in schematic regardless of VI definitions.7 `2 c# T! h7 ^1 E: t# K
868380 FSP ALLEGRO_INTEGRAT improve error message Invalid design database encountered for ECO mode. Collaboration data was found for the following d
5 e9 S# c3 C8 l# a* _8 E+ n904790 SCM OTHER Update the format of the time displayed in the session log
* J6 k! z. d* y904794 SCM OTHER Enhance the time displayed in the verilog file to support DST9 I% w4 Q! P: \- e8 u7 g
920740 CONCEPT_HDL CORE Detailed info about syntax error while executing "publishpdf" from Command Line.3 f5 h1 X3 m; y$ K* r/ M5 _' L
921934 CONCEPT_HDL CORE Clicking on Next page command would take you to the beginning of the schematic (page1)6 D0 g( K, ]) j ]8 G
923210 CONCEPT_HDL CORE Search with multiple properties does not show all properties
" N8 S: A" U1 _- ^( P1 n! O927609 CONCEPT_HDL OTHER CREF links bounded by rectangular box in generated PDF x0 Y$ m% S+ ?; }! `
957030 CAPTURE DRC DRC warning message for net group is not correct
' V6 L1 ^2 b- ^957723 CONCEPT_HDL CAEVIEWS Customer can not get DIFFERENTIAL_PAIR properties by CAEViews.
% s& | X- }8 J+ h0 r" z/ \0 p957913 CONCEPT_HDL CORE Segmentation fault when running DE HDL from a command line with a script
# y$ s2 R4 X" Q6 ~# Y; i+ D966191 SIG_INTEGRITY OTHER Xnets to be split didn't work correctly.
/ y/ ]0 c$ |) W970597 CONCEPT_HDL INFRA 16.5 schematic uprev fails if lib parts are missing' h, v4 q% E) n% B- Z( m& r
974361 ALLEGRO_EDITOR EDIT_ETCH Difference in length between Show Element and CM when Z-Axis delay is enabled.0 b# M( k( l/ t0 P# f8 ^
975531 CAPTURE NETLIST_ALLEGRO Error initializing COM property pages: Invalid pointer even after trying solution 116982805 ?8 w1 _) ?/ `: Z V; u6 p2 j
977375 CONCEPT_HDL CORE Unable to open the same Page of Base Schematic along with CRef Schematic Page.
% w0 I, U4 a4 `, P4 @7 p9 G981219 CONCEPT_HDL CORE PaperSize A1 is not correctly managed by wplot_paper
# J5 H5 ~: n% P- Q: K981613 SCM SCHGEN ASA Schegen fails/crash on specific block in ASA design
; S* T" X3 L, F7 m5 F% V; T, a- o981744 SCM SCHGEN schgen does not preserve connectivity and property related changes when done together
! c9 `) D' i: [) f/ K0 `4 T5 ?981809 SCM OTHER ASA does handle PACK_SHORT pins& L+ w% O' X- W* }
982004 ALLEGRO_EDITOR GRAPHICS Allegro crash when viewing and zoom in for subclass9 O8 Y$ }2 _+ z/ K+ t; m
982824 ALLEGRO_EDITOR OTHER Import placement fails with a zero length log file.
Z" X6 L# z Q. U989083 PCB_LIBRARIAN CORE PDV shows converted scalar to vector pins on symbol as Q_N<2..0> and in symbol pins as Q<2..0>_N
( l6 w; W+ s) Y1 M/ @989518 CONCEPT_HDL CORE DEHDL crash with Search Result tab$ \6 g0 z" m' U* _4 R
990582 FSP NET_EDITING Method to support the net names in the design to be driven by the FPGA port name
) i" |1 t! }8 X5 ^994504 PCB_LIBRARIAN CORE PDV adding text should respect the snap to grid grid settings and text justification. x% j. a# y# X u
995351 ALLEGRO_EDITOR EDIT_ETCH Enhance Allegro 16.5's slide with Vertex Action function of new Slide in SPB 16.6
2 J- {4 U7 k1 b6 l3 a995566 ALLEGRO_EDITOR REPORTS Drill data file qty not matching drill chart
/ Q6 X7 @5 z) q3 n! x2 S996019 PCB_LIBRARIAN CORE PDV having text on 2 lines having CR/LF is lost when reloading the symbol' t: ~) l7 L2 V) {
998499 CONCEPT_HDL CORE Attributes sticks to the component when its copied
/ y5 W9 {) P3 Y$ ?" }: y2 X998987 FSP DESIGN_SETTINGS Hyphen in project name should not be allowed while creating new project itself.: D, B" {6 e6 j/ x1 F% Z* ^( d
1000604 FSP DE-HDL_SCHEMATIC Component ripping off from the board after second pass of Schgen: x0 U( u: P5 o6 D( x0 s9 \
1000912 ALLEGRO_EDITOR DRC_CONSTR Dynamic Phase Tuning DRC Goes Outside the Lines
5 F7 N! ~- V* ]1001167 SIG_INTEGRITY GEOMETRY_EXTRACT Need warning message of DC shape check." x% P4 J& q$ b
1001395 SIP_LAYOUT ASSY_RULE_CHECK Shape Minimum void check reports lots of DRCs which are not necessary to check out.
* |1 L$ U$ e0 w( m* G: a1001563 FSP SCRIPTING_INTERF TCL command to dump the path to rules file and mapping file used by every part in a FSP project5 B" i' Y8 a3 Y' V9 a7 i7 Z2 x% r
1002462 CONCEPT_HDL CORE Block Stretch disrupts pins# @7 _0 H3 I6 V R9 R' g
1003110 PCB_LIBRARIAN AUTOMATION PDV Symbol Property Outline Offset value zero wrong interpreted as -200& c/ |* ~& v2 Y. s
1003253 CAPTURE PROPERTY_EDITOR property is not removed from Browse Spreadsheet in H design9 b3 k8 {$ D6 m/ S' _
1003447 SIP_LAYOUT DIE_EDITOR Rounding errors are causing problems for shrunk dies with .001 u mfg grid
$ S5 h& f/ S, p* O- G- l2 a1 w$ W% M1004093 CONCEPT_HDL OTHER Disable Default setting in Product Choice for Project manager
; s+ m* e6 {6 `; l- n: i2 |1004249 CONCEPT_HDL CORE DEHDL global search crashes on a ? search
4 m$ {3 M1 ]- }, u) m" Q: t4 I1005890 PSPICE PROBE Probe Window crashes when & is added in the Probe Page Header6 E# r; f( l& l& @1 |4 S
1006183 CIS FOOTPRINT_VIEW Incorrect pin details in 3D Footprint Viewer.
7 G' A" O- S; I! F/ G$ ~( d1006336 SIG_EXPLORER OTHER diif pair nets with shape traces cannot be extracted into sigxp; G/ x- f3 e. i9 u" z. }
1006437 SIP_LAYOUT BGA_EDITOR SCM not loading the die if dies refdes and LFnames are changed' c1 a: t+ u# u, s1 ^. ^; |
1006862 CONCEPT_HDL INFRA Uprev process is tedious and requires lot of manual effort for a design with multiple reuse blocks& h2 f% R1 S# A5 D0 ]
1007198 CONCEPT_HDL INFRA Room property getting the wrong value after packaging an upreved design
1 O$ m7 E" V: I! v4 P3 j1007732 CAPTURE NETLIST_OTHER Q: Why does wirelist netlist adds an extra NODE for some connections made using POWER GROUP?
% {0 N, l7 T: j( u" v1007781 CONCEPT_HDL OTHER Generated pdf for design upreved from 16.3 has occ_only attributes5 o2 T$ `! j3 M
1007904 GRE IFP_INTERACTIVE Setup > Design Parameters is missing the Flow Planning tab with Allegro PCB SI XL license
& i# l5 d4 ~4 l+ T2 ]7 i1007995 FSP DE-HDL_SCHEMATIC FSP schematic generation needs abiltiy to pick power symbols just like ASA' i1 [. J( M8 f% f6 J2 M% @& b
1008112 FSP DE-HDL_SCHEMATIC port directions set inside FSP need to be used for ports in schgen" [- ]7 A* O7 m- n' t
1008451 LAYOUT TRANSLATORS The brd file translated using L2A Translator is loosing the diameter of the copper area attached to the pin.' Y6 F0 p3 }! \
1008507 PCB_LIBRARIAN OTHER Base Part Developer isn篙 there with the PCB Designer license of 1650.# s9 [5 u2 x5 W+ E# f: [$ b
1008608 ALLEGRO_EDITOR INTERACTIV Add an arc/fillet with a changed radius will invert an arc at a different location" Z+ G& {; k3 H8 T' l/ a }' g! v- b' n
1009001 CONCEPT_HDL OTHER Graphics Color setting form is strange on Win7.
. p. P- v0 |+ [1009077 CONCEPT_HDL CORE unable to uprev the design
. B* `; ^; u' M! a) e" p. E* Y. [. `1009109 SIG_INTEGRITY OTHER User defined diff pair pin pairs are mixed in match group/ l9 [) i% d f2 ^# c- \2 P
1009557 SIG_INTEGRITY GEOMETRY_EXTRACT Difference in Impedance and Diff Impedance calculation is not correct. {. i3 m0 H; S
1010145 ALLEGRO_EDITOR GRAPHICS Display Issue With Oblong padstack
( P$ h9 e- F* F" s2 s# M1010374 LAYOUT TRANSLATORS Layout MAX file is not getting converted to OrCAD Peformance correctly
0 c9 J2 H G+ J! ^1010512 ALLEGRO_EDITOR DRC_CONSTR Can not check short pin in DRC
$ g6 k* H1 Z" h1010569 CONCEPT_HDL OTHER Sort Old Signal Name column in paste special9 D* ^; Q8 v) u l( D
1010661 PCB_LIBRARIAN CORE Save as the part with different in PDV changes all the property values
. o; f% h7 A) A; O+ ]1011022 ALLEGRO_EDITOR OTHER Create Fanout crashes allegro if dimension is visible! C; _: j7 ~( @! }
1011424 CONCEPT_HDL CREFER Component attributes are set to invisible in the flatten schematics generated from CRefer' T' K, G9 y9 h5 u; V
1011431 FSP PROCESS Incorrect selection of protocols under 燕rocess Options� window1 u+ k z0 @) J3 {7 h" z d' b
1011474 FSP OTHER Easier way to read lengthier message which comes in no connect report (Report for Signals).
" o g1 `7 _7 ~2 D8 Y1011525 PCB_LIBRARIAN CORE the reload does not update sym_1 immediately3 u/ X! O- }1 o [0 s, ?
1011618 SIP_LAYOUT DIE_ABSTRACT_IF Add Co-design die from DIA should add any missing non-conductor subclasses for import of package shapes.; e- B. P% `# p1 `& S6 W' F! S
1011629 CONCEPT_HDL INFRA RefDes change on schematic after upreving from SPB 16.3 to 16.5
2 {! J7 S- i0 T( |! k1012750 CONCEPT_HDL ARCHIVER The SI_MODEL_PATH from ARCHIVE_SI_MODEL_FILES directive of Archiver; C( A k, q1 K5 ~1 `
1012942 CAPTURE SCHEMATICS ORCAD V16.5 open Capture DOS SDT Schematic issue
" n' o$ G: E" E/ b1013377 ALLEGRO_EDITOR DRAFTING Allow edit and delete vertex in dimension environment
3 w A6 }1 \- }& ~, D1013795 ALLEGRO_EDITOR MANUFACT Tolerance value for Angular Dimension using "lus or Minus" type is not working correctly in new Dimesnion environment$ R5 |% z) ]. [/ B3 J7 Z+ A$ V1 }$ w
1014142 CONCEPT_HDL CORE Customer have dump file when they run Script on DE-HDL16.5
6 W& x7 ~% c$ W$ z+ D$ @' Y1014243 CONSTRAINT_MGR CONCEPT_HDL Default setting of Constraint Manager's Filter.
5 u0 p3 c5 |5 [4 W: D0 u. ~0 D1014334 CONCEPT_HDL INFRA Incorrect refdes and source after first Export Physical.
% D: E, a) O3 h1014853 CAPTURE NETGROUPS Error (ORCAP-1839) Invalid Character in Netgroup name (minus sign)
7 w# d1 Q$ O6 ]/ i* \2 k1014913 ALLEGRO_EDITOR GRAPHICS 3D viewer seems to hang PCB tool., _, |5 y1 y3 J( [+ L3 W# I+ n
1015256 ALLEGRO_EDITOR OTHER Allegro Crash while working with Dimensioning Environment
( H) C& R! ?. k b( u1015397 SIP_LAYOUT DIE_ABSTRACT_IF Support bumps provided in die abstract in hierarchical blocks/ m/ G) f' ^) Z/ n$ G
1016859 SCM REPORTS dsreportgen exits with %errorlevel%' X7 d- D, G+ ]4 U& J- N( U
1016891 APD VIA_STRUCTURE Log file does not indicate the problem or how to fix when refreshing Via Stuctures fails., d# w4 g/ l# H/ W& ?+ ]# b' f& l
1016916 ALLEGRO_EDITOR SKILL Cannot delete non etch shape from a symbol in the pcb editor.
( r0 L, w4 v+ G) X" ~1017173 ALLEGRO_EDITOR GRAPHICS moving a via changes it's size to the NC figure- }' M/ e5 a) n8 \0 _
1017337 CONCEPT_HDL OTHER DEHDL Recover adds extra page border" o4 P' F; v; }2 P: z* o
1018222 PDN_ANALYSIS PCB_STATICIRDROP DC-Irdrop happened crashed if GND shape did not be selected
9 T' s& m) \: d3 \" o! k1018348 SCM SCHGEN Generate schematic hangs when creating pages- Y4 \* i7 K+ ?. N
1018769 SIP_LAYOUT MANUFACTURING Deletion of plating bar removes "NODRC_ETCH_OUTSIDE_KEEPIN" property' ^5 `! p1 Y# N( W
1019167 SIG_INTEGRITY OTHER Top thickness not added to the z-axis delay.
; U0 g. `" P+ F, d3 t) h7 E6 |: _1019423 SIP_LAYOUT DIE_ABSTRACT_IF SiP Layout and APD should exclude characters from PinNumbers that are not valid in SPB front-end tools% }1 b/ y- ^) ~: _
1019977 CONCEPT_HDL CORE Upver changes voltage property value
7 M0 U. ~9 C+ D1020163 CONCEPT_HDL CREFER missing page after running CREFER in schcref of flat design/ [* G8 ]3 P* W0 v, c c
1020666 APD OTHER Bug - APD option for Route >Routing Layer Assign fails with Error message) b5 o6 U8 G& T
1021620 ALLEGRO_EDITOR OTHER LINUX UNIX (AIX) numlock maps incorrectly" e& @/ }# Q/ a k2 R
1021869 PCB_LIBRARIAN CORE SCM should not crash when using the attached design.
4 S: p- \' z% d& `2 U' n y e1022117 PCB_LIBRARIAN CORE Warning(SPCODD-44): File xxx/fsp.ptf not found3 H! S) v- J( P) ~- h) B: B
1023076 CONSTRAINT_MGR OTHER ECSet Differential Pair inheritence is not working when a Physical Cset is also defined on Net Object
% V% S9 K H. o" Y1023305 ALLEGRO_EDITOR PLACEMENT ALT_SYMBOLS is not available in RMB when hover over symbol
$ |! C6 h' w8 m2 `- r3 Y: f1023715 CONCEPT_HDL OTHER After runnign genview dashboard does not show the sym_1 view as being modified.
3 G( [( b7 `+ e. d; G/ v9 |1023751 PDN_ANALYSIS PCB_STATICIRDROP PDN: thresholds of each padstack are not used for DC current exceed pin/via threshold report.
6 S% M0 c! |; q c7 `7 r! U" G5 ~$ n! h1023774 APD WIREBOND After "xml wire profile data" is imported it isn't reflected to actual wire.! f3 `# I# S# i& b" q$ g9 W
1023836 ALLEGRO_EDITOR INTERACTIV Move origin undo doesnot brings origin to original location
- u9 N$ u& o7 r# J- f: |0 g, D2 K1024684 APD COLOR Layer priority not working with user defined mask layers.
4 N) F, O4 l' I) M: g( M5 h1024996 SIP_LAYOUT DIE_EDITOR SiP Layout Edit Co-design DIE shifts the drivers, the .dia for this came from Virtuoso" N6 s j1 G1 P7 E* x
1025482 CONCEPT_HDL INFRA dcf file not getting updated' n! v) z& H! n8 Z8 a4 n% r. \
1026153 CONCEPT_HDL CORE DE HDL crashes while saving.' W: n& ^. G$ v
1026403 ALLEGRO_EDITOR OTHER application crashes when we attempt to change the User units form Millimeter to Mils 38 S1 ]9 J `9 n) d: g: t" T; w8 x4 N4 Z9 C
1027336 SIP_LAYOUT DIE_EDITOR Die editor does not allow change of pkg padstack3 h2 n2 t/ D0 \5 G N5 X
1028240 F2B PACKAGERXL plx.exe has stopped working plx.log is empty
3 B0 \' t& b' O- m# s1028544 ALLEGRO_EDITOR REPORTS Wrong angle value of Module Report (180->180000), I. X: h% n y# g8 n
1029213 ALLEGRO_EDITOR SHOW_ELEM Allegro crashes on Show Element when showelement_highspeed is set.1 o: X4 |# J& Z* k6 l- U7 j$ M
1029217 SCM SCHGEN Schgen creates schematics with no visable netnames.( | U2 K/ a, Y5 @% L% o- ~
1029596 ALLEGRO_EDITOR PADS_IN PADS_IN dropping net name on few pins; w6 i% i) [: R
1029606 SIP_LAYOUT MODULES The place manually crashes the application
+ X/ E$ D+ Z# d* W- E' d& Y& w9 ^( A1030385 ALLEGRO_EDITOR INTERFACES Import DXF fails to import text and flag note symbols correctly
# Y+ Y9 z0 p% H8 R D6 B# }! k1031255 SCM UI SCM Replace Component form will not sort the columns.! J1 K5 g: M( u1 S2 W
1031324 ALLEGRO_EDITOR EDIT_ETCH Double click to add via crashes allegro
' ^4 ^+ u. Y' k' I1 c1 S1031676 ALLEGRO_EDITOR OTHER Auto Rename Refdes Crashes Allegro% o2 \" C. K4 ^, f* B+ `$ {
1031838 SIG_INTEGRITY GUI Auto Setup is unable to assign models which have been created by 15.7's Create Model rules.' g+ S- z, D+ w e
1033291 CONCEPT_HDL INFRA DE-HDL crashes if Search is started while the design is loading( t$ M6 j) u& K _
1034699 CONSTRAINT_MGR OTHER Constraint Manager Update DRC deletes waived DRC's comments.5 {, y9 f% Y0 s, Z8 a) q n
1043671 ALLEGRO_EDITOR DATABASE Dbdoctor fails on 16.5 release
* R6 { p5 `! U9 ?. @& K8 g6 E320014 ALLEGRO_EDITOR EDIT_ETCH Differential pair fail to Slide together; F J5 j( |; a# y6 X
400672 ALLEGRO_EDITOR EDIT_ETCH The Diffpair rule is disregarded because of the insertion of Via.
4 b& u- k5 P' X448641 ALLEGRO_EDITOR EDIT_ETCH Diff pairs do not slide when the xnet is broken+ V& n8 D+ p5 Q7 X# T2 b; K# v
501605 ALLEGRO_EDITOR EDIT_ETCH Diff Pair Sliding problem& U8 V9 z% n; G1 X% U
709668 ALLEGRO_EDITOR EDIT_ETCH Diff pair can not slide together., N. i4 Q4 S, {
731162 ALLEGRO_EDITOR EDIT_ETCH Slide and Delay Tune on Diff pair tunes only one net when Single trace mode is not ON.# e, x4 Q2 w. v0 e/ p8 o# F, Q- `+ c
790914 ALLEGRO_EDITOR EDIT_ETCH Differential pair routing question5 j; _# n" V5 ?* `
859855 SIG_INTEGRITY GEOMETRY_EXTRACT OddSegParallelOffset env doesn't work if Enable CPW Extraction is checked.
1 T( V4 [1 g: @2 N+ r966191 SIG_INTEGRITY OTHER Xnets to be split didn't work correctly.
8 {- [1 M9 G$ h1 s% ]. m967082 SIG_INTEGRITY SIGNOISE signoise command didn't use Frequency set on Net.2 a: o: F$ l2 g- Q
967832 CONCEPT_HDL INFRA Back annotation process takes long time on network
0 l( G( f7 u- M969535 CONSTRAINT_MGR SCM ASA retains information in the DCF file for parts/blocks that have been deleted and this causes problems.% z& ^- X5 O' r) a' m2 h- n
974361 ALLEGRO_EDITOR EDIT_ETCH Difference in length between Show Element and CM when Z-Axis delay is enabled.
: Y" Z; M/ H* f974533 SIP_LAYOUT OTHER Crashes in Edit > Die Properties and obviously has a setup problem.
. f. A+ C$ c: ?0 W8 b1 d979958 SIP_LAYOUT ASSY_RULE_CHECK Running Assembly Rules Check on sip causes a crash
7 {" F' ?. \; P1 y9 f982004 ALLEGRO_EDITOR GRAPHICS Allegro crash when viewing and zoom in for subclass
( t: @. T/ z, D% ^# E9 A- F984604 ALLEGRO_EDITOR EDIT_ETCH Error when trying to split via stack
; U+ r- B% M& g8 R; C; U% V988446 APD OTHER Beginning layer regular pad cannot change to Null. d N3 H( M+ ^2 u% \
995108 ALLEGRO_EDITOR GRAPHICS Strange unexpected lines show across the oblong padstack9 A2 s' L! ^4 w9 Z. W7 w! }" Z
995351 ALLEGRO_EDITOR EDIT_ETCH Enhance Allegro 16.5's slide with Vertex Action function of new Slide in SPB 16.60 A- K4 b2 [8 w2 }$ p4 }
996577 SPECCTRA ROUTE Specctra not routing NET_SHORT connections2 s2 \( l! H* N
4 A- d+ S7 z0 eDATE: 07-5-2012 HOTFIX VERSION: 0255 r8 Z: L: |; R2 J0 v; J
===================================================================================================================================
" S5 a- a7 U. ]; |# ~; ECCRID PRODUCT PRODUCTLEVEL2 TITLE
. w: Y1 }$ j5 Z. N===================================================================================================================================
6 K# u4 H/ F$ g2 [- Q6 E859855 SIG_INTEGRITY GEOMETRY_EXTRACT OddSegParallelOffset env doesn't work if Enable CPW Extraction is checked.( [2 Y. a) V( E! e5 a$ ]3 j
1014275 CONSTRAINT_MGR OTHER F2B: DiffPair cns was not updated if DiffPair Name didn't match.
1 `9 Z/ V2 l' [7 G1019414 ALLEGRO_EDITOR INTERFACES export DXF creates pin offset in 16.5- m. O8 v% e4 b7 a
1019688 ALLEGRO_EDITOR INTERACTIV moving dimension symbol in 16.3 crashes allegro2 G, I# M. x) r8 ~9 @9 y
1022563 ALLEGRO_EDITOR INTERFACES IDF_In do not import Arc correctly when IDF and Allegro accuracy are same.
* @* M1 N7 D+ W+ t; T2 Z1023892 SIG_INTEGRITY OTHER Need Custom Variable to control signoise.run uprev from 16.2 > 16.5 to control reading of DevLibs variables
* o/ v; I9 }$ v% n# I8 q2 S1023939 APD COLOR Assigning a color to a group a second time fails after "clear net color overrides."
+ Z* S: [: `, m9 ]1025402 SIG_INTEGRITY LICENSING Show Element window does not display and Allegro crashes.
4 ^. {/ t: w; d- E5 D( L; ]1025957 SIG_INTEGRITY OTHER Same net parallelism reports DRC errors on straight line segments
: y4 f$ l0 A3 m1026401 ALLEGRO_EDITOR SKILL axlPolyExpand returns incorrect information when expand
V: H/ R# e2 B9 U& I3 p
0 }3 X$ n* c4 [) y3 p6 SDATE: 06-20-2012 HOTFIX VERSION: 024) f7 @& [- x Q6 j1 }
===================================================================================================================================
) _8 K( y* Q* E( x8 \* CCCRID PRODUCT PRODUCTLEVEL2 TITLE# ~0 K# `; Z9 b" F9 N! i
===================================================================================================================================
: ~2 C: n- U4 x9 N& s& w [1011040 FSP PROCESS Feature to avoid connectivity between fixed voltage Output and variable voltage Input3 X* ^5 \& N, t I
1012985 ALLEGRO_EDITOR DATABASE Allegro crashes multiple times a day6 S5 D {+ G% C. }& \) C @( {" L6 y
1013644 ALLEGRO_EDITOR SHAPE Sliding trace with oops creates a duplicate shape islands* ?0 n3 q9 } _ s
1014351 ALLEGRO_EDITOR OTHER Whenever we open a file (brd, dra) in PCB Editor with an OrCAD PCB Designer license,we get a warning SPMH0D-34
, } z1 u! S* X2 O" K+ ~7 @/ Q1014893 CONSTRAINT_MGR OTHER With CM open layout is extremely slow and Allegro crashes very frequently ~# a1 \6 j# D
1015210 ALLEGRO_EDITOR DRC_CONSTR Deleting Via from an array casues DRC errors3 h/ x' m+ z2 n# p( }/ u
1016546 CONCEPT_HDL CONSTRAINT_MGR Wrong value of NET_PYSICAL _SPACING_TYPE in Attribute form
# x) j8 W0 _& c/ ^ O% f/ I1016932 RF_PCB DISCRETE_LIBX_2A Incorrect Symbol Pin Numbers after import into ADS* P0 \0 P3 m9 e8 _! b
1017332 APD VIA_STRUCTURE Refreshing Via Structures results in shorting to power plane.
2 a4 z. l5 u7 O4 K( V8 k1017931 ALLEGRO_EDITOR OTHER IPF import fails with error-IPF error : Illegal pen number0 i- }$ K. f, K
1018413 F2B PACKAGERXL Export Physical producing different results depending on how it is launched i. I9 \5 W1 r9 q A, R
1018435 APD OTHER Oblong pads in Sip are not displayed correctly in the Stream_out .sf file.
8 |8 j! o u. d' n1018936 ALLEGRO_EDITOR OTHER unexpexted DRC eror/ i+ @7 U1 _; m, }; G8 L
1018978 ALLEGRO_EDITOR DRC_CONSTR Update DRC changes DRC without any change in design
5 v7 T* D, F% D$ w1 `2 A1019303 CONCEPT_HDL INFRA DEHDL custom outport displays error
* a1 K. ]$ z$ E1019913 ALLEGRO_EDITOR DATABASE BUG:Bottom pins are also shown in DXF export; ]6 _0 E# U2 |( o, f
1019955 ALLEGRO_EDITOR SKILL axlRegionCreate and axlRegionAdd do not work in a symbol file.
6 f5 }$ y3 x% |1 a( N4 [0 l1020749 ALLEGRO_EDITOR DATABASE 16.2 Parts not updating when opened in a 16.5 database; \% |' O$ t& C8 W+ k
1020780 APD COLOR APD crash on assigning color to net using Color192
: Q/ Y% r2 C8 k! O. T; d. {1021033 CONCEPT_HDL CONSTRAINT_MGR Cleared ecsets in 16.3 reappears as mapping errors without ecset names after uprev to 16.54 e$ [2 M* V- s6 A& b% v( n
* P W! v3 m% @ r
DATE: 05-30-2012 HOTFIX VERSION: 023" g8 J" Y2 D P, s. C S
===================================================================================================================================5 ^" c o) C/ h2 G
CCRID PRODUCT PRODUCTLEVEL2 TITLE
4 q( A/ g/ g8 _: D===================================================================================================================================" Y% z6 f9 M# K7 S; c
999003 LAYOUT TRANSLATORS L2A leaves unconnected nets and improper voids on vias
, s# t' B) O$ I6 b1012375 ALLEGRO_EDITOR PARTITION Route Keepout in All subclass shape in .dpf cannot be imported back to master board.
/ Y$ c5 Z; B, F; W, e4 x1012522 ALLEGRO_EDITOR OTHER Allegro crashes during Import > Logic > Deisgn HDL and creates a .SAV file.
% J& Y1 |$ n8 J4 f: v1 U" G1012765 ALLEGRO_EDITOR EDIT_ETCH Allegro crash. F3 d8 K' Q( l- r. N8 c& T9 i
1012934 CONCEPT_HDL CONSTRAINT_MGR Backannotation destroys matchgroups in replicated blocks in customer design
" K8 y! k- z) |: x/ h; k! X1012951 CONCEPT_HDL CORE Text justification corrupted on symbol mirror
8 O1 K- h, U) A- e: J u) L+ Z1013030 SIG_INTEGRITY SIGNOISE PCB SI crashes when running bus simulations' j9 F1 U" Y4 w9 c4 c. I- c, ~
1013519 APD GRAPHICS The layer selection in the Visibility Form slows down after selecting "Nets" in the Color Dialog.
3 Y* f3 c! k' b1 A% V' V0 y( S1013853 CONSTRAINT_MGR OTHER Override constraints not working( \2 {% @, n" `( A' @
1013942 APD COLOR Assign color is inconsistently assigning colors to the clines but not the vias.
& m* d; s1 P& b- Y5 b1014402 CONCEPT_HDL CORE DE HDL crashes while saving some pages
" _' U% y. l0 q( J K, G" W3 `+ h1014757 SIG_INTEGRITY GEOMETRY_EXTRACT Huge Difference in Differential Impedance values in Cross Section between Bem2d and Ems2d Field Solver.
2 G. W- {: e$ f5 Z/ l, B: x1014956 SIP_LAYOUT DIE_EDITOR die editor pin move and add commands put things on the half grid and not on the grid as expected, ?, h O" q" `5 f' r' I0 `
2 n3 k5 V! Z# i" ^. Y0 T9 i6 ZDATE: 05-18-2012 HOTFIX VERSION: 0220 Q' a! a7 E4 ?) H4 F7 g
===================================================================================================================================
2 D" ]! g: X' g# r4 D* z$ v5 WCCRID PRODUCT PRODUCTLEVEL2 TITLE
z0 ~4 ^' i' C1 k, ~, D- ~+ J===================================================================================================================================1 ^1 f: t1 o) O3 O0 }- T
686560 CAPTURE BACKANNOTATE Changing pin group property after pin swap resets pin numbers+ w8 u0 y/ d6 ]
740162 ALLEGRO_EDITOR EDIT_ETCH Enhance Allegro PCB Editor use model when adding NULL net copper$ J# `: P2 F& K# j9 e' o
963645 PSPICE MODELEDITOR Model import wizard crashes while associating IRF150 to schematic symbol.0 `% b' |7 T! S0 ^
966422 CAPTURE PROPERTY_EDITOR References changes, done in the property editor, lost on closing and reopening the design3 I6 P3 C+ _0 }& Y H
968674 PSPICE PROBE Display Measurement evaluation does not show Measurement and its value directly.
. B$ Q6 B+ v9 N- L. ~( l/ }970281 CAPTURE ANNOTATE Annotation assigns wrong refdes to resistor.7 D/ d" o, I& `+ G
975497 CAPTURE NETLIST_OTHER Capture crashes while trying to generate other format netlist+ a/ C, \, h. F+ P
993129 CONCEPT_HDL CONSTRAINT_MGR unable to select multiple nets in schematic and highlighted them in CM7 a6 a$ e5 ?5 Y3 U1 ~" x
997518 PSPICE PROBE Mouse click on probe window is required to see Plots after simulation for multiple plots on win 7
0 r( q; O, ?/ S( D' I999603 CAPTURE NETGROUPS Capture crashes on trying to rename a netgroup member.
f- J4 s/ W4 i! U# Z) \- I1002370 ALLEGRO_EDITOR SKILL Allegro axlMeterIsCancelled function not always returning t when Stop button is selected./ T1 p, n5 y9 S) Q) f
1003205 APD DATABASE Fillet gone after DB doctor check
# b+ o/ Q+ i; D4 T M( {2 W, T# U1003821 ALLEGRO_EDITOR EDIT_ETCH Diff pair routing starts from unexpacted pin for non control cline
% e5 t3 T5 N& S# V# W+ i( x; S* ~1005793 ALLEGRO_EDITOR DRC_CONSTR Update DRC with Multi-thread DRC changes DRC without any change in design for Win 7 OS! Z. j1 Z0 c8 S* T
1005835 ALLEGRO_EDITOR OTHER Display Status fails to show rats on missing connection point. n$ Z- s% S$ O4 B
1006701 ALLEGRO_EDITOR SHAPE Shape to shape void incorrect spacing value in L3 layer.
& U! n- B+ }( K) h$ `& G' a+ I1006718 CONSTRAINT_MGR OTHER Allegro crashes while sliding nets having custom formula in CMGR
' l" G1 I8 q& g' |5 i8 n+ u1006920 CONCEPT_HDL CORE Global Navigate hangs schematic. \. M; A* k" }7 G' E F
1007102 CAPTURE OTHER Latest release on START page is not getting updated! d; d8 Z) c, z K; u& H" [, p s
1008585 ALLEGRO_EDITOR MANUFACT Manufacturing X Section Chart layer is not coming up correctly in this design
+ k$ ]" ~( K. U1 u1009047 F2B PACKAGERXL Packager crashes after installing ISR s19* D. A5 E Z& {6 N
1009443 ALLEGRO_EDITOR DRAFTING Pressing TAB key in Dimension environment results error: E- (SPMHA2-65): Error -3000314.& P0 u3 k/ |8 m. l' B& Z* m# V# y. h/ Q1 {
1009562 CAPTURE TCL_INTERFACE Library correction TCL utility is failiing to correct the corrupt libraries.
& Q! D" A2 |5 j6 U# X! p1009941 SIP_LAYOUT DIE_ABSTRACT_IF Distributed DIE abstract generated from Virtuoso VSiP Architect has errors on Shapes used in Area xfer, W; f' o7 H9 x7 B
1010201 ALLEGRO_EDITOR INTERACTIV dbdoctor on psm file returns error in open drawing& a4 E% O% r) Z R; P' ]9 p. O
1010432 ALLEGRO_EDITOR SYMBOL Error in placing Pin in Symbol editor, "W- (SPMHDB-226): Inconsistent rotation data.") d2 N& Z5 Z; e5 [
1010611 MODEL_INTEGRIT TRANSLATION Translation failed due to IBIS2DML errors.6 ^, V% Y C4 `1 G* u, U6 q* i
# [* w- f1 w8 |, W. V+ SDATE: 05-5-2012 HOTFIX VERSION: 021
9 `1 l% z5 R$ \7 T; x===================================================================================================================================
) I3 J( g- O. o9 |" UCCRID PRODUCT PRODUCTLEVEL2 TITLE
- w- b1 N9 U+ [" K===================================================================================================================================
8 ?1 P( s$ [: u642550 ALLEGRO_EDITOR EDIT_ETCH Route connect of Diff Pairs is not honoring the correct gap when entering a region.8 z: ^- s5 Z6 E5 r
921837 CONCEPT_HDL CONSTRAINT_MGR DIFFERENTIAL_PAIR property in synonymed net is deleted automatically6 _2 W; i# N' _* {
926776 CONCEPT_HDL CORE Modify the newgenasym log file to convey the multi format vector information
" }: w9 I) G* E4 C* g9 v# I969547 SCM CONSTRAINT_MGR Diff Pair, Net Class objects are being "corrupted" by making logic changes in ASA involving copy & paste of signals.
$ B2 @0 T/ m/ H3 L& A976566 PCB_LIBRARIAN VIEWERS SCM crashes when adding a part.
2 Y R* G" l- ?0 v4 p984538 PCB_LIBRARIAN CORE PDV and con2con crash on part having illegal data into symbol view
, I$ [0 A3 b, }# [, x/ d. g987120 CONCEPT_HDL ARCHIVER Customer would like to include signal models into archived project by Arciver.! |1 N7 _2 T/ Z7 f: _+ d
988683 CONCEPT_HDL INFRA CMGR Net extraction via DEHDL writes topology file at the CPM project level# z' J. b! ^& L% v% M- m1 Z* P3 h
989116 CONCEPT_HDL CORE Warning 171: Port exist in symbol but not in schematic* R- f! L5 P) d$ Z
990630 FSP TERMINATIONS Overlap of parts sig_name ctaps and refdes after schgen
7 C$ x2 _) o3 m0 }+ O' L9 H" X( q992075 CONCEPT_HDL ARCHIVER Create Single File Archive and Delete Archived Directory doesnt work if spaces are found
, V+ s$ C `* o- Y( {/ _993084 CONCEPT_HDL CONSTRAINT_MGR Problem with bus members7 Y5 `/ }2 n) {" g
994466 SCM ECO SCM is going out of Memory in Import ECO Netlist which is used in the BRD2ASA flow
+ X( w& t3 q: C9 E: z& e) ~% s# @4 ?996609 APD EDIT_ETCH Error (SPMHAC-31): The element from which you are connecting is not on the subclass. Use "Add Via"/ A( r" r1 K' J* b5 ]. T R8 ~8 Q
997076 CONSTRAINT_MGR OTHER Application not checking to class to class inherited spacing Cset
$ n/ e( G: b- }& A# d997655 CONSTRAINT_MGR CONCEPT_HDL Support Partical DCF import/Export in DEHDL
& V/ k& ]& N N L# b8 `* D) }998176 SIG_INTEGRITY OTHER Allegro crashes when extracting net from CM
8 A* j; \! ~. c2 M* s6 t8 \ G999044 ALLEGRO_EDITOR EDIT_ETCH Routing wires is confusing because of the way DRC engine resolves spacing rules.' d- }* ~/ F7 @/ x9 q A! q
999218 SIG_INTEGRITY OTHER concept2cm has encountered a problem2 ]7 h; _+ l( k8 j( O* ^; O. u
1001742 ALLEGRO_EDITOR SCHEM_FTB netrev detects an error for the part which has JEDEC_TYPE with null value.5 ]+ }9 D% b- Z0 S0 K7 G. C6 [
1001897 SIG_INTEGRITY OTHER Packaging much longer in 16.5 s018 ISR
8 b- ~" Y+ G8 a% C6 T1001913 APD STREAM_IF Mirrored text is not mirrored in stream_out and stream_in. r$ Z4 ] f4 j( o0 }, r$ b
1001953 ALLEGRO_EDITOR OTHER Allegro 16.5 database crashes when trying to downrev to 16.3
( r. H: D$ p$ ~4 B- O3 g& b1002895 SIG_INTEGRITY FIELD_SOLVERS Delay calculation is changed from ISR16 to ISR17 and above( n" {/ M* }& P2 r6 ~
1003097 APD WIREBOND How to change finger padstack that maintaining current finger angle1 C. ~1 j: t3 F R9 }8 _
1003638 ALLEGRO_EDITOR UI_FORMS Ability to filter and sort in IDX Flow Manager Export/Import
+ c5 N" \( I `* `1004196 ALLEGRO_EDITOR DRC_CONSTR Thermal ties creates shorts with Enable online DRC checked.
, `( p+ B9 h9 V3 M7 ~! F$ x4 x1004346 CONCEPT_HDL COMP_BROWSER The hyper-link under the DATASHEET column breaks after sorting7 r4 `+ |# D8 u n9 E/ W: C8 T
1004363 ALLEGRO_EDITOR PLACEMENT Place manual is inaccurate at pick up
8 v6 H8 t, J' t0 M$ r6 a# \+ g1005265 CONCEPT_HDL INFRA Uprev from 163 to 165 does not complete
2 p; i7 \5 D( a, h( G M1005398 SCM SCHGEN Crash when generating schematics when vectored pins tied to non vector signal
' s: ?4 `! m% f1005584 ALLEGRO_EDITOR MANUFACT Variant Assembly Drawing with locked symbols creates incorrect view2 w% `' C, n- Q; K# @4 \4 A5 C
1006266 ALLEGRO_EDITOR GRAPHICS 3D Viewer Crashes Allegro
& o3 p& h8 y; y0 a& L1007420 ALLEGRO_EDITOR OTHER Allegro PCB Editor crashes while doing a File > Change Editor- d/ V, ?3 H. l$ w& K* o O5 Q
# U3 { U/ i8 T, dDATE: 04-20-2012 HOTFIX VERSION: 020
( C) E. C, J. a9 }& m" e===================================================================================================================================' O9 t( b$ @- Z
CCRID PRODUCT PRODUCTLEVEL2 TITLE
$ [( L& O: w! T7 l3 G' l===================================================================================================================================
, X" u3 G3 [! F# Y6 c& N( o4 a712448 PCB_LIBRARIAN CORE $PN should be grayed out if the bus is shown in un-expanded mode.
! a( z9 d/ x' {919548 ADW COMPONENT_BROWSE After component is placed If we see the Classification of UCB that it was collapsed.
8 R3 F: z# D6 i- Z- U* T( S972909 SIG_INTEGRITY SIMULATION Bus Sim: stimulus on diff data signals were not used correctly in comprehensive sim.3 Q5 K+ x/ U! l. {$ M- L4 Y
974325 PSPICE PROBE Unable to edit and move the existing label texts.
( A4 ~& B: m# E& }8 g- T985088 SIG_INTEGRITY GEOMETRY_EXTRACT Extraction of the cline near the reference plane shape edge.' r7 y% f/ R- t" s
987311 CONCEPT_HDL CORE ERROR (LMF-02018): License call failed for feature Allegro_TeamDesign_Auth_Option8 E& O% [' ]% `
987544 CONCEPT_HDL INFRA Some component have $PN property annotated on the instance body
$ N8 O0 W) {# [/ Q6 b) i987605 APD ASSY_RULE_CHECK Not getting accute angle DRC's where there is a pin or via attached to the trace.
' s7 n7 f, v9 K$ ^% _990396 SCM OTHER SCM Clipboard does not populate contents copied outside of SCM
9 z' @( A/ b% N$ Y2 `; j/ Z2 |990961 CONCEPT_HDL INFRA Uprev to 16.5 causing physical net name change, N: U8 s5 U) y! t2 I7 ~. h6 ?
993993 SIG_INTEGRITY FIELD_SOLVERS Transmission line calculator and xsection form showing different DiffZ0 values
) R* ^- j) |5 N# g995086 CONCEPT_HDL INFRA Target net is lost in the uprev process
# q! }) e$ }& `0 M7 ]$ M2 j r996136 F2B PACKAGERXL The pstrprt.dat part entries no longer contain space after increasing PART_TYPE_LENGTH+ S3 m* O( s: C
996481 PCB_LIBRARIAN CORE PDV cell "file > save as" changes uppercase characters in PTF to lowercase
9 w3 ?6 a' F. q$ s+ d7 @% {996816 SIP_LAYOUT WIREBOND The tool is down when I do the "import wirebond"5 n: m1 X. E+ n' m) a
997137 CONCEPT_HDL CHECKPLUS Why does CheckPlus report that the INUSE� property exists?
3 g4 v. a: @) n, }0 y& e8 b997243 CONCEPT_HDL INFRA Save and hier_write fails on a upreved design with the message - ERROR SPCOCN-1995% n$ |8 l) i5 ^8 |1 ~1 \
997260 SIP_LAYOUT DIE_ABSTRACT_IF Not able to import the co-design dia file in CDNSIP with the error msg SPMHUT-110 No pin count set
0 |0 M" C9 x7 p" m9 U6 K997427 ALLEGRO_EDITOR PAD_EDITOR SMD Padstack defined for Bottom placed on Top
, `: }9 w* G1 i# c' |& W998107 CONCEPT_HDL CONSTRAINT_MGR Error message calls for Constraint Manager Synchronization. I- z# O6 {# t0 Y
998124 ALLEGRO_EDITOR INTERACTIV Copy paste with snap to pin option not working correctly' C/ F8 J0 g' h# Q' K& F; a$ a0 g* l
998313 PCB_LIBRARIAN CORE PDV on linux platform to write symbol coordinates when using PDV_Symbol_Coord environment variable
9 Q" L' m* B- I( c" M999030 ALLEGRO_EDITOR SHAPE Shape Corrupts when moving" r! G5 r2 k( d, t+ w8 ~" c
999452 SIG_INTEGRITY SIMULATION HSPICE sim from probe command fail if native ibis was assigned to components.
& n0 R4 n# {( J ^7 u1 v0 P2 d999536 SPECCTRA ROUTE Allegro router crashing with memory error.. U" H% |- \' F. P* J. ]2 f, L& p
1000060 ALLEGRO_EDITOR OTHER Board thickness in idf output is not correct
1 y( \% V: ~0 ?6 Q5 Z1000824 APD WIREBOND *Error* lessp: can't handle (14 < nil)- T8 F, A4 Z, C+ x$ ^% c
1000835 SIG_INTEGRITY SIGWAVE SigWave: can not import many simulation files at one time.$ ]7 N. l5 B7 `, U, v
1001302 APD WIREBOND Add Routing channel behavior
1 v% p$ L# B" y1 a# z. Y/ B, V' n& F& m9 Q5 k
DATE: 04-5-2012 HOTFIX VERSION: 019
1 `, x/ m: ^+ T7 X===================================================================================================================================
$ L& a. m; U4 m: |CCRID PRODUCT PRODUCTLEVEL2 TITLE/ o/ T1 [. X1 I9 N
===================================================================================================================================0 @7 X( u& i `+ p' q' l2 `
230469 ALLEGRO_EDITOR SHAPE Allegro improve performance of Dynamic Shapes" j* G! G0 k+ m, l) e
753867 PCB_LIBRARIAN GRAPHICAL_EDITOR PDV crash when graphics from one symbol to another
# f( ^9 d) L2 Y957363 ALLEGRO_EDITOR PLACEMENT Allegro hangs while moving reuse modules
9 Q' u8 a% R, }; F" d8 K3 S0 W$ ?965705 RF_PCB DISCRETE_LIBX_2A Allegro Discrete Library to Agilent ADS Translator hangs on Windows
" V. ~$ O! }/ v: X; [4 `979872 SIP_RF OTHER V-SiP Arch LVL or Compare DIE abstract fails to hilite in RED a pin location move, using REF DES against IC615 Layout
: Q" u. V' Q4 w* t: S: C/ ^# P, q983318 LAYOUT TRANSLATORS L2A translator for v16.5 fails with error -Subclass name TOP not valid for class Package keepin
# b! O6 d3 ^- U1 g6 S984503 CONSTRAINT_MGR INTERACTIV Highlighted nets/xnets in CM > Object > Filter is not working when Highlight Pattern is Solid9 \" h b! }( i: `9 l9 d
985091 ALLEGRO_EDITOR OTHER Customer wants to be disabled "Allegro PCB Design L (legacy)" of the "cadence Product Choices".
2 m! E2 \$ z: r1 u6 Q985734 CONCEPT_HDL INFRA part having a pin_name of # followed by a double digit numeric causes issues in packaging
1 o! z( J6 A# A- V' R3 f4 J985984 CONCEPT_HDL PAGE_MGMT Deleting pages inside 16.5 takes to long for larger projects5 x6 y: `9 k: e3 s- |- s
986614 CONCEPT_HDL INFRA Uprev process in 16.50 prompts Error: Exception occurred while netlisting block9 h' N$ ^" i4 Z
987276 ALLEGRO_EDITOR MODULES Placing module with Associative dimension crash
) t7 y4 I. q, n% p' S988088 ALLEGRO_EDITOR INTERACTIV Edit > Move of Vias with incremental coordinates entered at the command line makes no sense in 16.5; [, Z* s3 l7 E8 R ~; w
988145 ALLEGRO_EDITOR INTERACTIV The move command with body center selected does not behave correctly with embedded components
* K) N% u% @+ @, C F$ p988822 SIG_EXPLORER SIMULATION Incorrect hspice netlist was generated. O+ M& {' H, W) S* p
989010 ALLEGRO_EDITOR NC NC Drill file for Backdrill do not include the drills without Drill Figure. Back Drill output is bad, U1 S, b0 C2 c; z
989127 CONCEPT_HDL CONSTRAINT_MGR NET_SPACING_TYPE placeholder is not added on the net attributes on the schematic+ M6 L' |3 u1 @) ?
989589 ALLEGRO_EDITOR INTERACTIV The Options, Find and Visibility windows are deleted and we need to delete allegro.ini file for recovering them back
* ^: N. k% ^9 ^5 u5 [989593 ALLEGRO_EDITOR SCHEM_FTB 16.5 Netrev fails with the message - ERROR(SPMHNI-176) Device library error detected- [- M* H2 k# g3 }9 \$ U. |, a$ |
989597 CONCEPT_HDL INFRA Wrong values displayed in the canvas. k7 L# m3 x! ?8 E; ?1 Y v* A7 ?8 k
989624 ALLEGRO_EDITOR COLOR View Color file, result error "Invalid subclass specified" for Mask layers.
z$ d3 R2 D8 o9 A- B7 g989734 ALLEGRO_EDITOR COLOR Display showing shapes on a layer that is turned Off.6 e0 K, n$ W) J! t
989882 ALLEGRO_EDITOR PADS_IN PADS IN with runtime Error. s- t5 V2 H) Q0 S/ `! V# T
990121 ALLEGRO_EDITOR OTHER Tools > Derive Connectivity crashes Allegro PCB Editor. Z" w& e9 {8 b4 G
990607 ALLEGRO_EDITOR DATABASE package symbol fails to place. Illegal line segment .. end points9 D' L9 _; s; t# o5 ?' Y
990736 ALLEGRO_EDITOR MANUFACT Stream Out crashes with customer design2 e" q8 m+ \% X! X/ G& p
990909 APD DEGASSING The Void to Conductor (Same Layer) option of degas does not work.- V$ N: Z1 U& I. r0 o- c
991121 APD DATABASE APD crash in dbdoctor drc check. Reports Illegal db pointer" K- j5 e1 n4 B5 H$ P8 p
991256 F2B PACKAGERXL What is the role of the pstdmlmodels.dat?
1 S$ l2 ^# ~) `% S# q9 g991404 ALLEGRO_EDITOR ARTWORK With latest ISR of 16.5,Artwork Control Form says "Plot Completed" when it actually completed with warnings.3 X4 p. z2 [" _) F. V4 F
991459 ALLEGRO_EDITOR PLACEMENT Rubberband between the cursor and symbol origin is missing while rotating: X1 F( \5 Q8 X) b
991965 ALLEGRO_EDITOR INTERFACES Import IDF doesnot translate Package Keepout areas. X) b" I& l! A# c6 \
992187 ALLEGRO_EDITOR OTHER add connect corrupts database
9 ]& n1 Z* O1 g% B: o( a* s992195 ALLEGRO_EDITOR OTHER The numeric key pad on a Linux or Solaris workstation is not working in 16.5 when Num Lock is ON.
* h0 f/ F& A# o: H+ j992198 CONCEPT_HDL CORE Symbol crashes in 16.5 works in 16.3) K) t: A) k5 U6 J7 W* v$ ?! r" y
992331 SIG_INTEGRITY OTHER Unbalanced diff pair is losing extra net from xnet connect - fails to update topology7 j0 v/ _% z* Y, [' w8 v5 W( F5 L% Z+ H
992468 ALLEGRO_EDITOR PADS_IN PADS IN with Error
: x, r8 f* x g* R8 G4 J992643 ALLEGRO_EDITOR INTERFACES Problem importing DXF into Allegro. Error SPMHA1-66
4 S' Y( ?8 u& w' l1 p f. ^992656 PCB_LIBRARIAN CORE PDV to store sym_cords.txt when saving cell
- W; L) d) ^+ @, c% ]+ e7 X992659 CAPTURE NETLIST_ALLEGRO Improve the performance for netlisting large designs" i! e3 Y/ \8 _/ h0 t
992842 CONSTRAINT_MGR CONCEPT_HDL Global ECSet Audit is catching errors but not updating the cmgr view to fail 'red' so hard to find errors
" W! o5 F, Z# U6 Q$ J) u$ _9 h993535 ALLEGRO_EDITOR DRC_CONSTR Constraint Manager not able to analyze Diff Pair Static Phase Tolerance for PCIe signals in attached database./ D" @4 K3 M9 W( t& u P; x
993554 ALLEGRO_EDITOR EDIT_ETCH HUD for Relataive Propagation Delay turns Green eventhough the DRC is not cleared
F9 y# M: S, |, M993618 ALLEGRO_EDITOR OTHER Viewlog for DBDoctor_ui could not find log file if ads_sdlog is defined.5 V8 T2 R, _9 |5 n6 N! `/ N
993655 PCB_LIBRARIAN CORE PDV move other objects then pins on the non-pin grid is broken, W1 t8 T9 s! D# u0 {9 G+ D
993728 F2B BOM bom_ignore value is <<OCC_DELETED>>8 h4 U+ X M/ B2 V- T( H: C2 Z4 X5 J
994628 SIG_INTEGRITY TRANSLATOR Wrong thresholds are used in setup and hold measurements
( J5 H( v2 o; ^, a; |0 T994783 SIG_INTEGRITY OTHER ECSet maps to some nets but not others7 x: ], Z( _8 y, x4 I3 ?
994963 ALLEGRO_EDITOR INTERFACES Mechanical Symbol has no refdes when importing IDX) b# O4 P" C9 w z' ]% Z: H( V
995050 CONCEPT_HDL INFRA Not able to package the design once upreved to 16.5 version2 m$ l6 T. Y/ }* F z
995431 CONCEPT_HDL ARCHIVER Archiver fails in the BPc environment
8 O4 E' l/ B$ a" |% d7 U995557 PCB_LIBRARIAN VERIFICATION con2con validating a full library often reports wrong execution time in rep file0 ~0 P# f0 ^- u' W
995600 CONCEPT_HDL CHECKPLUS Global signals appearing in the multiple_signames check under Checkplus, _# R8 U! }8 w& c/ ]5 M
995699 APD SHAPE Shape fill is inconsistent.9 L( n( [4 L5 z% h6 Y# E
3 X4 n; c! a" T7 P+ M: P$ W
DATE: 03-16-2012 HOTFIX VERSION: 018
7 s* _' q* R& C; D6 u===================================================================================================================================
6 ~1 B# P6 H! ?/ DCCRID PRODUCT PRODUCTLEVEL2 TITLE
& U, t" s% c6 x, V u===================================================================================================================================
2 u1 J6 a( Y+ | S% @758924 PDN_ANALYSIS PCB_STATICIRDROP IRDrop via current report with flag for over current& Q) H% O6 q( G" z' C2 U
903166 PSPICE FRONTENDPLUGIN Pspice > View netlist not working if .NET is assiciated with Capture
$ |7 D7 I7 r. a' ] U947680 PSPICE FRONTENDPLUGIN Out file is not displayed with view output file option in Win 7/ B) O% `! K/ z; I9 h
951483 CAPTURE GEN_BOM SYLK File format is not valid in Excel% a$ I' T5 G) R
954330 CAPTURE GEN_BOM Corrupt BOM for attached design. How can we correct it ?
; d3 _$ S$ H& S# K" _! R% h964000 CAPTURE NETLIST_OTHER User Defined Footprint getting replaced by value in Other netlist
- V% \, S+ o; E4 v! W968261 CAPTURE NETGROUPS Refdes Control required with Netgroup blocks, [& n. l7 E5 V0 ^9 D
968345 CAPTURE NETGROUPS Cannot tick in the Place Netgroup window
O# |+ l) R9 [4 G3 e8 d# w- p3 }974894 CAPTURE DATABASE Capture crashes when updating part from database
5 U+ Q- g. \# b" O$ {8 v977355 ALLEGRO_EDITOR DATABASE Presence of fillets causing no such child error during add connect.1 c) k4 D1 j* {8 z4 l9 a4 C
978007 ALLEGRO_EDITOR PCAD_IN PCAD Translation failure* V5 Q1 p# g# O- \2 A
978382 CAPTURE SCHEMATICS Placing testpoint symbol causes extra junction8 E8 }7 u8 p) f0 L
978522 SIG_INTEGRITY LICENSING Q- Is there a way to set via model option in Orcad PCB Designer Professional license?
& D/ [" u! M9 o+ }4 d' b- z/ W979041 SIG_INTEGRITY LIBRARY Contents of model_pcbsi.ndx were constantly accumulated when doing the distribution on each time; N5 }' ~, {: n
979594 CONSTRAINT_MGR CONCEPT_HDL Extra and incorrect information dumped in the alias conflicts reported generated from DE HD-CM Audit
; G0 c0 x; _4 w- h' o981621 ALLEGRO_EDITOR DRC_CONSTR Updating DRC fails to set Shape Out of Date after changing NetClass membership that affects spacing
8 \) B$ W' P( Q8 {& \983608 F2B BOM Generating all variant BOMs changes selected variant: \1 Z: \& M* H* Y7 {* y/ X5 W; M
983629 SIG_EXPLORER EXPORT No exported cross section file created in directory with spaces
1 u/ z1 P1 [) @+ j& j& d8 C984218 CONCEPT_HDL INFRA Uprev from 162 > 165 causes certain ECSets to be in an illegal conflict state which is false% r9 E( @9 v" X3 `$ ~8 J
984578 F2B DDBPI PDV and con2con crash on part having illegal data into ptf view
' b& B9 {3 u0 Q4 @9 I- @) ]984768 APD SHAPE Dynamic shape finishing with strange void.
. Y+ d; _# A6 t+ v: T. |985346 SIP_LAYOUT IMPORT_DATA import netlist-in-wizard fails and crashes
+ j; s* ^' }: C: y985451 APD DIE_GENERATOR die text in results in Invalid object type passed to GetPadstackLayer9 t. r# B5 W9 X5 b6 s3 f
986268 ALLEGRO_EDITOR GRAPHICS Copy & Move graphics issue with OpenGL
% m, h3 p( a2 k3 l986552 ALLEGRO_EDITOR EDIT_ETCH The Cline is not avoided the "Route Keepout" by hug in 165. but it does in 16.34 \, n8 B/ {0 {+ w: I, s# }
986704 ALLEGRO_EDITOR EDIT_ETCH PCB Editor crashes during add connect
' p) `5 }/ e) d! O986895 ALLEGRO_EDITOR NC Any layer back drill issues
W8 Z& N' M3 Z987309 SIP_LAYOUT COMPONENT_COMPAR Component Compare with DIA file and Net Assignment fails on co-design die with net assignment done by scm
9 }& V5 A3 V( m4 j9 X* \987339 CONCEPT_HDL INFRA replace component inconsistent in .dcf file
/ x: X- A6 `( N" i' Y8 ?9 k; N987455 ALLEGRO_EDITOR DRC_CONSTR Allegro wrongly reporting Mechanical Pin Antipad to Pin Spacing drc
+ J! S h0 S# M9 M: c7 R987669 ALLEGRO_EDITOR DRC_CONSTR multi-thread update DRC causes the application to crash
6 U8 ~# v8 A w6 S H987843 SPIF OTHER Fanout vias on BOTTOM Layer are shown on TOP Layer in Allegro after routing and importing a session file from SPECCTRA. A: `. @$ I# | t
988001 CONCEPT_HDL CONSTRAINT_MGR Cant assign Xnet to Electrical class at all and CM crashes if Ecset is assigned to xnet' x2 q) W; H; s5 N3 F8 A
988133 SIG_INTEGRITY OTHER Extra pin pairs are created in Prop Delay worksheet when ECSet is assigned to diff pair. N9 B. ~5 D: @6 }3 r
988609 SIP_LAYOUT SYMB_EDIT_APPMOD When using the Symbol Applicatoin mode to edit a BGA the pin pitch settings are incorrect.
8 T1 E1 Y; `8 Y0 o$ o# Z989078 ALLEGRO_EDITOR OTHER Export IDF's total thickness is not correct
4 o+ v/ R1 @, m6 V0 w) [6 E
P& i; |" x2 f: ~DATE: 03-02-2012 HOTFIX VERSION: 017
6 {" M) B9 w+ R===================================================================================================================================
+ C& N+ J7 K5 |CCRID PRODUCT PRODUCTLEVEL2 TITLE' Z5 ?2 D0 G) J' q8 H7 n6 b$ G
===================================================================================================================================, y) N r4 A! w
867859 ALLEGRO_EDITOR SHAPE Overlapping static and dynamic shape are out of date but display status shapes reports up to date
/ d! x1 Z- G. K" Q* `* n940856 PSPICE ENVIRONMENT Simsrvr crashes when opening "Edit simulation profile" window from Capture 2nd time9 ]+ W7 W3 i) K: r3 N
951657 FSP DESIGN_SETTINGS Support for new cpld with Qualcomm flow
3 o+ \5 i O q; @# f961998 FSP MODEL_EDITOR Support for VRP and VRN as Target Pin Property/ V* A6 O2 P( D! b2 J
962132 FSP DE-HDL_SCHEMATIC Symbol viewed in FSP has a different Pin sequence than in DEHDL Schematics
6 r1 ?# t7 ?, c: h962380 FSP OTHER Differential pairs of group contiguous pin cannot be synthesized# O3 V, C# P/ o% ?
963662 FSP OTHER PGA Port� does not match with the pecify Net name�
3 ^6 k2 G+ C0 x. i1 v965353 FSP OTHER "This feature is not available" while printing PDF from Schematic or Files View.
6 ^% ~8 t2 X' H/ X# a967418 ALLEGRO_EDITOR INTERACTIV Component gets mirrored when placed after using Reject
3 w9 l, R- T3 h. R968403 ALLEGRO_EDITOR SHAPE shape void element command does not work correctly
; b% P0 R9 _" ?$ Y2 r3 F975184 PDN_ANALYSIS PCB_STATICIRDROP Fail to do static ID Drop Analysis
4 j* \' \9 i7 ?: i/ x* a% w8 Y( f% U, ~975674 CAPTURE PART_EDITOR Crash on saving an edited part with a different name, copied from another library9 u5 _& `: z2 u
976704 CONCEPT_HDL INFRA xcon and def files are not updated correctly although do hier_write
" C, ~1 X8 k, m7 Y978649 CONCEPT_HDL OTHER DEHDL crashes with highlight while cross-probing.
, E) f) r D2 e978722 ALLEGRO_EDITOR OTHER ENH: Drafting text value should be same as given0 A) @: [ D, w( X5 J2 J# F7 E
978754 SIG_INTEGRITY SIMULATION OrCAD PCB SI is not using custom stimulus
/ X* ]) c. ^( M( O4 A5 K978772 CONCEPT_HDL COPY_PROJECT CopyProject is changing the library order in the cpm file when you rename the library name8 S& P; T7 T! m& N, C; x* K
979075 CONCEPT_HDL INFRA e signoise.run and sigxp.run folders are getting created at cpm level on concepthdl in spb165* E2 Y" [8 }% q% N& R+ S
979451 SIP_RF FTB V-SiP Arch constraints not passing Front2Back for differential pair assignment
0 P4 K: v. P. G9 @; L2 K& @979458 CONCEPT_HDL CORE Add port Genview Move pin on block - pin name disappears9 e% D {2 i. @4 c/ x8 {) O* Z
980204 ALLEGRO_EDITOR SKILL different output value before and after the execution of axlLayerCreateCrossSection skill function0 z! H/ i1 P3 W( D
980211 ALLEGRO_EDITOR MANUFACT Empty Dimension Group Subclass on package symbol is corrupting the symbol when placed on board file.+ U* m6 u8 y; D1 i9 J. A
980532 PDN_ANALYSIS PCB_STATICIRDROP PDN: PDNSIM_32BIT fail if no return path exist.
8 U9 G9 s5 P* t3 K980584 ALLEGRO_EDITOR PADS_IN mbs2brd crashes when translating the Mentor design to Allegro.5 c8 W$ `& i6 N' D& v+ e
980721 SIP_LAYOUT WIREBOND import of wirebond xml file with malformation does not indicate any error in the file9 K4 y) t- l0 e/ t: b4 D U
980904 SIP_LAYOUT WIREBOND Why is min and max wire length in status window showing the same value which is not taken from the constraint settings+ O$ B# M% c- ] K
980933 PCB_LIBRARIAN IMPORT_OTHER License call failed for feature Capture version 16.500 and quantity of 1
* e( n3 \& L4 L- Q( `: A0 G4 ?981156 APD GRAPHICS The cline display remains while moving a finger.7 y( K( F! ?+ v. _1 X" O4 j$ `
981309 ALLEGRO_EDITOR OTHER Change DFA code so a perfect square is an ambigious condition and uses the most conservative value
+ A* j3 d' J4 d& I+ I' O4 d981345 SIP_LAYOUT DEGASSING Degassing causing strange voids.
A. W, K. n, l" @. R2 q- m. _981436 ALLEGRO_EDITOR OTHER Unable to add cross section chart after deleting the chart with the delete command
8 ~! R6 \- d$ Z8 ~: T X# a* g981756 ALLEGRO_EDITOR OTHER Associative Dimensioning: Change Text changes the Unit instead of Value+ s2 E0 h( `" K: ]# I( z# V% d
982272 ALLEGRO_EDITOR OTHER Line Fattening is in incorrect license tier area
% v% k1 a) E3 b5 q! ^% s983231 ALLEGRO_EDITOR OTHER Change Text in dimension Environment, is not working as desired
/ o+ s4 a' M/ S/ f983736 CONCEPT_HDL CONSTRAINT_MGR Voltage Sync property is being removed from CMGR during Back annotation due to PXL annotate net enabled
! g" K) {- {7 G' r9 ?: j983848 SIG_INTEGRITY OTHER Model names with a comma are not corrected
6 v& q& H; y& @0 J984120 ALLEGRO_EDITOR MANUFACT Test prep crash Allego when using RMD on Existing Via column header$ {$ o% D- c) M+ W
984283 ALLEGRO_EDITOR SHAPE Allegro crashes when selecting a shape
- a/ ]& a& Q d* G; v, E
7 Z8 r; K8 C' t3 BDATE: 02-17-2012 HOTFIX VERSION: 0160 Q3 v/ ]! S% t1 B' C j b
===================================================================================================================================
/ S) M2 w/ y) u" K/ R: b" I2 [CCRID PRODUCT PRODUCTLEVEL2 TITLE7 |- Y F! [% W0 j' R, ~' ?4 f7 J
===================================================================================================================================
1 b. h* q* q5 I& v. D9 F! k+ b840105 PCB_LIBRARIAN USABILITY PTF subtype is getting changed when Save As option is used in PDV9 p$ {3 b8 ^, H3 S( B+ W$ M8 ^9 T% c* X
873075 PSPICE PROBE Decibel of FFT results are incorrect.7 L | R: {9 C
938744 ADW COMPONENT_BROWSE Need ability to customize shopping cart columns to include any Part property+ _6 Y( j$ ~" ]
943003 SCM REPORTS The dsreportgen command fails with network located project, j$ e3 d$ @# b
961530 ALLEGRO_EDITOR INTERACTIV The problem of Display measure command
3 F: j" R" q$ q$ D% M( w962157 CONCEPT_HDL CORE Where is the setting for enabling the Enable PSpice Simulator menu?: l3 C0 i' h: y5 ~
962206 CONSTRAINT_MGR CONCEPT_HDL Import physical not passing all constraints from the board to frontend
; Y0 c1 I! Q! l$ G968205 PSPICE DEHDL_NETLISTER Change SPLIT_INST property to PSICE_SPLIT_INST for Quad Switch type of design.1 M# x& o! L: ]7 M' _1 k! E
968509 PCB_LIBRARIAN METADATA Incorrect pinlist.txt was generated if DIFF_PAIR_PINS_POS/NEG was set.1 |6 r- c) `) n2 r) a9 E# g" T
969450 LAYOUT TRANSLATORS OrCAD Layout to Allegro Translator crashes
- | X G4 ]0 f: r9 N* u969997 CONSTRAINT_MGR CONCEPT_HDL ERROR(SPCOPK-1053): Cannot find a ppt part that matches the instance pro~
' t9 W9 y( ?" ^1 t' V971193 CONSTRAINT_MGR UI_FORMS Copy and pasting a formula causes the application to crash on windows.6 {8 q! u9 l* ~5 [+ Y
971601 CONSTRAINT_MGR CONCEPT_HDL ERROR(SPCOPK-1053) and WARNING(SPCODD-66) because of directory structure: l7 Q9 V7 P/ Q/ \% n! }* k4 K
973398 CONCEPT_HDL OTHER It should be not packaged with error while working the packaging process if the design has a ERROR
U+ }9 T% p' j! [2 y973859 PSPICE ENCRYPTION Pspice crashes with encrypted model
0 A8 u! H _; x) C n973938 PCB_LIBRARIAN VERIFICATION pc.db is missing6 R/ x3 } n' v ~ d4 z
974540 CONCEPT_HDL CORE Graphics updates are real slow- ^+ U; t* ?: \5 p( M5 ]
974791 F2B DESIGNVARI Variants are not back-annotating to schematic and turning to ?* b1 ~- B; B( |* R4 ?7 i
974818 ALLEGRO_EDITOR NC Backdrilling produces 0 plunges yet no errors reported.' n& r, f+ j1 l" d7 O& D( [7 t
974945 ALLEGRO_EDITOR SKILL Why is axlPolyOperation is giving different result and not working
# t& S' M/ M4 U/ `' \0 O* `974946 MODEL_INTEGRIT TRANSLATION ibis2signoise returns the error - Delay measurement fixture must contain V for ECL technology
( o9 z/ i! S0 q. \975396 CONCEPT_HDL CONSTRAINT_MGR Constraints are dropped after migrating from 16.3 to 16.5( [7 x$ `2 ^3 I( G
975633 ALLEGRO_EDITOR GRAPHICS 'dynamic_layer_visibility' option in 3D Viewer when checked or unchecked should not change (until next change)
5 N2 b8 S0 n; |8 b0 a975720 ALLEGRO_EDITOR DRAFTING Datum dimension lines not adjusting to text move% ?8 C$ J( x) s7 A0 E' Q
975745 ALLEGRO_EDITOR SKILL cdsServIpc different 16.2 vs 16.5 when Allegro exits7 k" [6 y/ i3 w6 d
976013 CONCEPT_HDL INFRA Power pin connection of FPGA symbol is missing in netlist.
8 V- M. _+ y r! i# B4 {976058 CONCEPT_HDL COPY_PROJECT SCM Copy project does not create the con and dcf files in tbl_1 views
* l: V; _# L# h1 G2 i976073 CONCEPT_HDL COPY_PROJECT All the constraint data is lost in the SCM copied design! C5 I: |! |; _8 e1 F5 e9 V4 z6 a
976160 CONCEPT_HDL CREFER Cref fails due to some Caeviews error in the design
% L8 X" i: ?4 d7 e976204 ALLEGRO_EDITOR DRC_CONSTR Application falsely reporting Mechanical Pin Antipad to Shape Spacing DRC
0 Y1 E' b8 f% E976448 F2B PACKAGERXL ERROR(SPCOPK-1069): Invalid POWER_GROUP property value
; y5 U6 D9 j8 p |- {8 P7 |! O976521 ALLEGRO_EDITOR DRC_CONSTR multi-thread update DRC causes the application to crash
* `/ `3 Q$ r n6 {# b7 `976838 SIG_INTEGRITY OTHER Unable to create XNET for highlighted nets on attached database even after assigning proper Signal Models.1 }" j) \4 |# Q2 w1 e( m* k
977517 F2B PACKAGERXL Export physical fails after update to 16.5 from 16.3
# P5 V5 b* v+ `7 G+ E! x; F977902 ALLEGRO_EDITOR DATABASE generate module is crashing allegro
V/ N0 m5 L: N( T4 h978652 ALLEGRO_EDITOR PADS_IN PADS_IN fails with ERROR: Finished with errors.
' r5 c8 j* Z) p978744 APD DEGASSING Some shapes will not DeGas on this design
6 P" P5 Z" p2 f979940 SIP_LAYOUT OTHER SiP Layout Leadframe autobonding with profile selection6 k6 f# S$ _% g9 i# d6 q3 t; ]
981699 CAPTURE HELP Start Page still shows Hotfix 14 after installing Hotfix 15# ?9 A) P' [' X" t3 F
, ?6 Q$ g ]/ `; \0 |. TDATE: 02-03-2012 HOTFIX VERSION: 015
5 j6 ~) a- c* A" N. A===================================================================================================================================' S) u! H+ Y, O% K( K
CCRID PRODUCT PRODUCTLEVEL2 TITLE6 U9 m1 F+ S& J& V
===================================================================================================================================2 b! S; @- F- Q: N
871567 CONSTRAINT_MGR SCHEM_FTB Ability to filter out Single Node Nets from Constraint Manager( x1 [. z/ G$ O
921436 ALLEGRO_EDITOR MANUFACT Change in 'decimal place' for new dimension changes the already placed dimension
- r! s4 k- T m. i2 i941433 CONCEPT_HDL COPY_PROJECT 16.5 Copy Project should warn if trying to copy a 16.3 design+ x8 A8 f- X8 t. m
954375 ALLEGRO_EDITOR MANUFACT Change dimension accuracy for few instaces of associative dimensioning: q: n; ^: a) x* N1 c1 T9 E$ W
961646 PDN_ANALYSIS EMVIEWER EMViewer Help > About shows wrong version' \3 Z- B! N7 H8 a0 v* j" N
964912 CONCEPT_HDL COPY_PROJECT ASA project crash after using copy project% _2 r8 u- \9 V
967223 ALLEGRO_EDITOR MANUFACT Bug:Oval slots orientation in one direction only9 O& V; J/ k F9 x1 |
968865 SIP_LAYOUT DIE_ABSTRACT_IF load of die abstract fails due to differences between component and symbol
/ f# c6 Y! v3 C' m# D969485 ALLEGRO_EDITOR SHAPE Shape does not update correctly in 16.5* o/ q4 W/ @* }+ x+ O: ]. H
970331 CONSTRAINT_MGR ANALYSIS Impedance worksheet shows a zero value for impedance) k! N& H. G4 b. \
970600 SIP_LAYOUT SYMB_EDIT_APPMOD Option in Die Editor to be able to "physically swap" pins
j) H3 n' O/ w# v% P. K( ]7 ]' ]970910 F2B PACKAGERXL Our customer has problem with pin color after pxl 16.5.1 z/ l& J" ~9 X4 Y) W
970970 SPECCTRA FANOUT Fanout Vias is placed far away from decaps and does not change the Fanout length even when max_length is reduced.
, q3 p) ~9 u# O! }970985 SIP_LAYOUT OTHER Importing a .spd2 database file using NA2 will cause the APD/SiP tool crash
9 M+ f# b; Y6 l971757 CONCEPT_HDL INFRA Crash while Saving/Packaging the Design% U) `4 N* b0 K- H) @
971923 ALLEGRO_EDITOR MANUFACT Allow to change decimal accuracy for dimension instances
( d" T! ^, L, T8 r4 V, i0 M0 A2 n972568 CONSTRAINT_MGR UI_FORMS Tools >Excel missing from CM" w/ k6 y6 b+ V: x( V5 I" }
972821 CONSTRAINT_MGR CONCEPT_HDL connectivity server warning: Unable to add property WEIGHT+ J4 V5 _& B; @2 g
973185 SCM CONSTRAINT_MGR ASA2 block not seeing all instances in a package.
; ?5 y" j; P% q, w973211 ALLEGRO_EDITOR INTERFACES IDX Object Type Change not recognized
/ _3 b8 J( Y' V; k$ A) c0 w973214 ALLEGRO_EDITOR INTERFACES IDX import package keepout height value change assigns incorrect value
; u0 g: y1 e9 S7 s2 p% O2 k }& R973384 CONCEPT_HDL CHECKPLUS The multiple SIG_NAME has to be occurred an ERROR at the SPB16.5.
) z1 p) Q; b; G7 R8 I973514 SIG_INTEGRITY OTHER Mapping error when Ecset is updated to constraint manager from extracted net
) I- S* @0 Y$ t) e5 r973950 ALLEGRO_EDITOR SHAPE Update to smooth crashes application5 l, ?/ c' e/ s
974533 SIP_LAYOUT OTHER Crashes in Edit > Die Properties and obviously has a setup problem.5 \5 U1 p0 }" E( I U* c, G& s
974809 ALLEGRO_EDITOR SKILL argument available for hiding a property with function axlDBCreatePropDictEntry is not working
3 z" e) e9 J8 g/ H: p4 D E4 |0 Y976179 INSTALLATION ISR Installation of ISR S014 to 16.5 on windows is breaking the documentation index6 F" @9 `9 d1 c/ `" h) O' n4 o: I
( p8 h( a5 I* @' _+ |
DATE: 01-20-2012 HOTFIX VERSION: 014. O! q/ N" D$ ^8 l% e
===================================================================================================================================2 l* [5 x+ k, d' u2 X1 |" l/ B& V
CCRID PRODUCT PRODUCTLEVEL2 TITLE
) w: W2 F$ G5 h; y# N. o===================================================================================================================================
" k; X0 ^! \$ s7 _- V3 [733285 PSPICE SIMULATOR Enhancement:In server-client installation use existing index file from server
o3 _" o- _, x& d# m941020 SIP_LAYOUT OTHER Soldermask enhancement
* v. z9 Z6 C' D$ V" I+ O946407 CONSTRAINT_MGR TDD When is it safe to open a 16.5 design in 16.3?
8 B! c( J% \: p+ P4 L5 z953067 CONCEPT_HDL OTHER Variant Editor "Error/Warning messages" form is unusable
' e$ P! S6 O0 H3 T4 A, S0 n954818 CONCEPT_HDL COMP_BROWSER Replace button turns to Add in component browser when a component replace is done on the schematic! G+ i) T) n' A! B0 r
956450 ALLEGRO_EDITOR DRC_CONSTR Analysis always shows analysis failed in uncoupled length in some diffpairs* c! p/ @" R# a, C) ~7 B" k$ C
958259 F2B DESIGNSYNC ds.exe crashes on a big design when accessing the design from network drive
# F- l% ~, I0 m+ @- A958395 ALLEGRO_EDITOR SHAPE shape voids won't merge
& b0 _7 z0 J" ^$ t# |( a; [# z959212 MODEL_INTEGRIT PARSE Attempting to use "Mark qualified" option on DML File results in dmlcheck and Modelsim wanrings.6 i- v# ~. m* G
959940 APD AUTOVOID Void all command gets result as no voids being generated.* {+ y6 Y: m- ]1 Z
960252 PCB_LIBRARIAN CORE Splash screen in PDV prevents showing error message& E* d) @, k$ T# e' u7 |9 x7 H
961634 PDN_ANALYSIS EMVIEWER Cannot launch PDN EMViewer from withing PCB SI. N& ^9 O' }+ q+ G. k
961645 PDN_ANALYSIS EMVIEWER Standalone EMViewer will crash when opening any result file in the form of *.emv file.
, X1 L4 } M6 }; J5 c& ]( E+ N2 V961700 ALLEGRO_EDITOR SHAPE dbdoctor reports ERROR(SPMHUT-144): Illegal arc specification
$ d, [4 _7 M b/ d961733 ALLEGRO_EDITOR SKILL Allegro crashes. Appears to have a memory leak.% a' L' o0 b: Z' a' g8 Y& c: n1 ]
961758 ALLEGRO_EDITOR DRC_CONSTR DFA check produces no DRC when the dfa bounds are not a rectangle.2 T# d+ [" m2 k& n, Y: O6 [
961887 CONCEPT_HDL CONSTRAINT_MGR Match Group created from ECSet cannot be deleted in the same session of CM. ?& g# ^6 G- S% j/ ]+ e6 z; Z
962552 APD EDIT_ETCH BUG:APD crashing when we try to slideget information but move works fine
: i& b. D, ~- x5 r; B" v962869 CAPTURE STABILITY Capture crashes after RMB click on rotated parallel wires
! G1 q. w& V$ [- p K963232 CAPTURE MACRO Macros not being played in Windows7
* n: N8 F1 T+ I2 N! \! r963300 ALLEGRO_EDITOR DATABASE Create > Module crashes in 16.5 but not in 16.39 j. ^ h7 n5 |- y* `$ X+ T) L$ v
963651 CONSTRAINT_MGR CONCEPT_HDL ECsets are renamed after packaging on linux# {" m! p7 J/ L
963663 CONSTRAINT_MGR ANALYSIS Q- Why the customized worsheet for Diff pair Impedance not analysing at all for this SIP design+ }7 n. Q, X5 e& P- ^# Y
963715 SIG_INTEGRITY OTHER Application only adds the bottom conductor thickness for the via z-axis length
. E' a& p. H. J& R6 z6 ?& U( G964068 ALLEGRO_EDITOR INTERACTIV Allegro crash when using move alt sym mirror alt sym...& V6 _ q2 H! S( U
964267 CIS PART_MANAGER Capture become non-responsive, working on Part Manager and creating CIS BOM, for large designs
- E8 t! J$ h; B% Q- w, k( V4 m964597 ADW LRM Issue of LRM license checkout after renewal license by 16.5 (ADW15.5_S23+SPB16.3): ^- k4 t/ m" w6 y2 ?" X8 e
966148 APD INTERFACES Character Limit for DIE Files (*.die) Import
' g8 E) W5 {% V0 ?7 M; m966416 F2B PACKAGERXL Cannot package this design
$ O# }) j0 A0 J3 `+ G5 H* e966421 CONCEPT_HDL CORE DEHDL Crash when applying property on components in duplicated blocks3 m8 l5 F- o, i# J+ m8 ^0 }1 `
966693 CONCEPT_HDL CORE DEHDL crashes when doing model assignment if CM is open5 H+ O( K+ p; v/ F( p7 r9 {, ?
966795 ADW ROLLBACK rollback utility does not honor -product option from command line
% H6 A6 r; H# F+ _967089 SIG_INTEGRITY OTHER Matchgroups created by ECSet not deleted when ECset is removed from object.
( _7 `: y6 O3 T" ]" I2 y' Q$ Z967222 ALLEGRO_EDITOR OTHER PDF export is leaving data off the drawing! F& t+ ~5 o3 \# A& H: t `2 i
967240 SIP_LAYOUT WIREBOND Change default bond fingers selected on multi-site leads during "bond to leads" program
# R9 D, N; [" {5 h' {7 b& Q( ^' s: P967297 ALLEGRO_EDITOR OTHER Dynamic Fillet&Eliminate unused stacked vias cannot be used as the Miniaturization option.
. s; ]1 Z2 a" g% s7 F9 J0 _967576 CONCEPT_HDL CREFER Occurrence location property values do not appear in flattened schematic generated by CreferHDL8 b9 P4 f/ f( H+ o) J' P, B$ n, ~) ]
968096 ALLEGRO_EDITOR DRC_CONSTR Mechanical Pin to conductor spacing is not followed.
% P3 X$ Z, z: [& A968222 SIP_LAYOUT DIE_EDITOR die pin loses IC net for a co-design die with multiple ports within IO-cell9 D; x+ q( |2 g$ d; D
968358 CIS PART_MANAGER Capture crash on removing a part from subgroup in part manager" a# r$ A1 X, u3 C, E) F$ ~
969594 CONCEPT_HDL CORE The dcf file is not updated with schematic changes( y0 N3 P- A0 R% Z
' \/ o5 @) ]2 D# l9 o6 n7 lDATE: 12-16-2011 HOTFIX VERSION: 0133 Y5 s- k z4 Q; K( W- R2 t" @
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CCRID PRODUCT PRODUCTLEVEL2 TITLE3 P1 Q& `& Y( W7 K, G4 K- O
===================================================================================================================================) j& L/ j- Z# q% }0 ~
875695 SIG_EXPLORER INTERACTIV Enforce Causality check box doesn't work.
( }% J$ d5 V, Y; n j9 D8 E927148 CAPTURE PROJECT_MANAGER Capture crashes on creating scehmatic folder with name which already exists in design
$ ~% D9 z/ _! {1 P938013 CAPTURE NETLIST_OTHER The netlist in RINF Format contained two identical lines for PCB FOOTPRINT( `: L+ y& |' l, U5 h
941409 PSPICE PROBE BUG : Search accuracy wrong in new cursor window
- f5 y. b" |( o1 L) p9 w/ Y( ~9 s- S945242 SIG_INTEGRITY SIMULATION Unable to select "shapes" in find filter for 'show parasitic ' command/ U% f9 f3 g! J; v
946293 CONCEPT_HDL ARCHIVER Archiver hangs if there is a whitespace at the end of the path of cref.dat& e/ a' C- c5 e, j- L% K, l5 Y/ {
946770 CONCEPT_HDL CORE iew Design� function is missing in Windows Mode after reseting the menus.
. z* i) I( i6 I$ s950994 CAPTURE NETGROUPS Problem in expanding the netgroup in Auto Connect to Bus function
$ m% W; C9 r( E953530 SIG_INTEGRITY GEOMETRY_EXTRACT Display Parasitics is displaying wrong results for EMS2D Field Solver compared to topology extraction using Probe.
# h2 }- n" @6 H0 B: P1 M. f953713 CONCEPT_HDL PAGE_MGMT Random page replacement/duplication in block1 x V# w0 L" J; y3 M. v
953917 CONCEPT_HDL ARCHIVER archcore should handle errors correctly H4 w0 @* \$ n
953971 ALLEGRO_EDITOR MANUFACT NC Drill files not generated correctly when using the option "eparate files for plated/nonplatedholes�/ H& \9 G0 w4 O- w9 c* x3 V& T
954400 CAPTURE NETGROUPS BUS members of NetGroup are getting converted to Scalars in Export-Import NetGroup.- Z% Y' H; ^# T# i, U5 B
954498 SCM B2F SCM crashes when importing physical9 z4 A; u( Y }$ i- t0 {; U0 T6 {
954623 ALLEGRO_EDITOR EDIT_ETCH Unable to complete connection with Add Connect - related to soldermask to cline check?7 N3 m$ \ Q: H! Y, Q5 g
954894 ALLEGRO_EDITOR MANUFACT Dimensions disappear when opening database in v16.5 from v16.3# W& i; I( z0 O) A( B9 ~ J( x' Y
955029 CONCEPT_HDL CORE custom text font size not recognized in symbol view
! e7 M) W; O* j+ m4 L955133 SIG_INTEGRITY FIELD_SOLVERS The Field solver creates the differential trace model which is reversed T(D1) and T(D2) of bottom side.
1 X7 ^- w* Y/ V955290 CAPTURE DRC Description for UPD0014 missing in the Browse DRC markers window
, E+ m: `- T. @; e k# e% D955299 ALLEGRO_EDITOR DRC_CONSTR drc text to smd pin does not work any more on this database in 16.3 S039
. H, z6 J" E' Q( g955338 CONCEPT_HDL CHECKPLUS Need to change PART_NAME6 x9 z# f2 l& j3 K
955447 SIG_EXPLORER OTHER Model path set in DE HDL Model Assignment not used by SigXP from CM in DE HDL9 ?1 D5 d1 ~7 J% s6 K! \
955740 SIG_INTEGRITY GEOMETRY_EXTRACT Crosstalk with Timing Windows does not work correctly! S6 A. P* i# `+ [9 N* G
955749 ALLEGRO_EDITOR MANUFACT show element Info shows symbol dimensions on incorrect subclass
9 H5 s# P( W, @" Y6 W955912 ALLEGRO_EDITOR OTHER Shapes with voids that are exported to PDF have gray filled area over the void
) P0 d; t4 F4 {! ?% ^5 i956129 CONCEPT_HDL INFRA DEHDL uprev hierachical design from 16.2 to 16.5 packaging failure.
0 E- ^9 S% Z# y" P, G; g) @956373 ALLEGRO_EDITOR NC drawing name doesn't display in the log file
! i6 V1 }# f9 G X+ ~3 x+ N956393 CAPTURE PROJECT_MANAGER "GENERAL" and "TYPE" tabs are missing from "Properties" dialogue box.
$ j% [7 |2 J1 r3 \, t, x7 g2 T: H( G956448 PSPICE MODELEDITOR Can not generate a DEHDL symbol from Model Editor, because no Capture license found
' [+ ?; n1 H( y& ^+ |% a$ W1 F; a- C956456 CAPTURE NETLIST_OTHER OrTelesis netlist not transferring user properties defined under combined
! \8 z9 f4 {5 C8 A4 e# H$ ]956489 ALLEGRO_EDITOR MANUFACT dimensions lost when symbol with diemnsions attached to symbol origin placed on board
( C* M& ]" c; h5 s8 e956603 CONCEPT_HDL OTHER Part Manager "has stopped working" after changing a component6 |1 m1 T6 H& O% X# o
956751 ALLEGRO_EDITOR ARTWORK Import Gerber command does not work correctly
5 R! h0 c9 N, p# E5 Y- R5 `$ `956847 PCB_LIBRARIAN METADATA PDV - Partdeveloper symbol to function linkage broken/changed in 16.5
8 {: T6 J A; E2 J! j8 \. ]956987 CAPTURE OTHER Find from "Search toolbar" doesn't gives complete results
0 x& Z3 _6 U0 B8 L5 D7 R956996 CONCEPT_HDL INFRA Correction to ERROR(SPCODD-7): Following Primitive instance causes CM to empty
' Q* }9 {: C* {957009 CAPTURE NETLIST_OTHER Problem getting database property in Mentor PADS PCB netlist
. l: [7 `! J6 G: C( ?; U; Y4 A957137 APD DXF_IF DXF out command dose not work correctly.$ U- {( ^* \' `2 y3 [9 ?2 q
957167 APD GRAPHICS Highlighting for Static shape with display_nohilitefont environment variable.
" S- k8 z; D' z# L957232 SIG_INTEGRITY OTHER Allegro crash during Model Assignment.
$ m" v$ G( p+ ~957267 CONCEPT_HDL INFRA Packager Error after Import Design
( B2 f8 q$ O5 Y8 f# ?, p. d957866 SIP_LAYOUT DATABASE Cavity outline is not getting deleted from symbol file
1 k+ O- n2 Q9 r9 \5 o, \ f958010 ALLEGRO_EDITOR REPORTS Wants the ability to extract "Batch" reports from Partition ".dpf" files.
# R2 Z3 U) _* d; x- x958252 ALLEGRO_EDITOR TESTPREP Resequence testprep with the option - Delete probes too close crashes the design
- ?# Z0 R% A" B) F& }5 c958253 ALLEGRO_EDITOR REPORTS Shape did not have thermal relief connected to pin but unrouted nets still shows zero.# b+ Y H. x2 @( s( Y* e8 f
958433 ALLEGRO_EDITOR DRC_CONSTR False embedded component DRCs( E" M) O$ v6 D7 Q( s8 W% |$ G+ g8 ?0 |( m
958753 ALLEGRO_EDITOR SHAPE Dynamic shape is getting corrupted in 16.5
/ ^: d& r- X0 S$ J3 T0 L) W3 y0 {, u959011 ALLEGRO_EDITOR OTHER copy problem of via and cline
* L0 m$ F* f9 g$ _* k959101 ALLEGRO_EDITOR EXTRACT Using extracta with excluding Thermal reliefs
% _+ b- o& O# g959253 CONCEPT_HDL INFRA Design will not open- Y1 u/ `. X% c2 N4 ?
959299 APD MODULES Getting ERROR(SPMHDB-279) when trying to update modules placed on the Top side
6 P9 h1 H) H* R# W! C2 `( G959884 CONCEPT_HDL INFRA Design Uprev/concept2cm crashes with Application Error/Out of Memory Error.
" ?" N+ B ?6 ^) X959909 ALLEGRO_EDITOR SCHEM_FTB Site level propflow.txt file is ignored property is transferred" i& V. B7 G3 y, c$ s/ Y
960067 SIP_LAYOUT PLATING_BAR Creation of plating bar removes "NODRC_ETCH_OUTSIDE_KEEPIN" property from the clines.
, l5 p7 y) g- O4 f' W) q- m( H A. Y. K960126 SIG_EXPLORER EXTRACTTOP Allegro PCB SI license is used automatically at Topology Extraction of Allegro Physical Viewer.
1 U( e; N/ v" m4 Y4 [960143 SIG_INTEGRITY GEOMETRY_EXTRACT Running simulation in Bus sim happened crash while enable Coulpled Via model to S parameter% ^$ Q5 j& r) {. m' ]$ F
961349 CONCEPT_HDL HDLDIRECT Motorola designs have broken connectivity compared to 16.3 l0 r1 m" R' j( C F- i$ q
961816 ALLEGRO_EDITOR INTERFACES Normal Export > DXF fails and offsets the pins of the BGA symbol- } A0 a' k7 I. B: P
962519 SIP_LAYOUT WIREBOND Align option doesn't work for wb_tackpoint fingers4 ]0 g# D9 s7 e8 ]6 Z
/ j4 v$ z! Y# a8 h# rDATE: 11-30-2011 HOTFIX VERSION: 012
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CCRID PRODUCT PRODUCTLEVEL2 TITLE- B/ Q* } f: K4 E3 s# k4 P
===================================================================================================================================
) B T a3 p R' A959581 CAPTURE NETLIST_OTHER PCB Footprint is getting replaced by VALUE in OTHER netlist formats9 i) q( B& J! A G5 \4 C) x' T
# W- m# R0 h, u2 z
DATE: 11-18-2011 HOTFIX VERSION: 011
# ?" F- B3 W5 @2 R===================================================================================================================================; E7 `& W/ t" M& a5 s( x4 ]$ u
CCRID PRODUCT PRODUCTLEVEL2 TITLE
/ B0 D' H+ }; ?, Z( `===================================================================================================================================
. L5 n- {, f# r0 [, v735439 PCB_LIBRARIAN CORE PDV Moving line-dot pinshapes by arrow keys breaks the pinshape
( l# q- ?9 f# v" j) `894815 CONCEPT_HDL COMP_BROWSER Why does genlibmetadata command give 'Aborted $PROG' Message?
' w* D& s O/ H$ V$ z903073 ADW COMPONENT_BROWSE datasheetl_url directive should support a display string for URL( [8 g/ [( u" X; |
909919 CONCEPT_HDL OTHER Why is the PublishPDF UNIX command line looking for "true" script?
' C" q3 m9 u4 l7 T911561 CAPTURE CORRUPT_DESIGN Capture crashes on trying to save the design." F( l1 h3 p/ l" v
919579 CAPTURE PRINT/PLOT/OUTPU Print mode be selected based on schematic mode
7 ^- ~3 k+ o; C& h- c6 N921247 CONCEPT_HDL COMP_BROWSER genlibmetadata.bat file does not have err defined6 Z/ e% w- U4 t* m( j
925182 CAPTURE PROJECT_MANAGER ENH: Feature to run update cache on all the parts in design cache at once.
! f' e w/ k" m) J0 ?926858 CONCEPT_HDL CORE Usability- Modify Component dialog forces user to do 'Reset Filters' to see other ppt rows! x( }/ C$ j) R! B) z4 r# D
927657 CAPTURE NETGROUPS Enhancement: Placement of netgroup definitions under design cache list! H( U1 w) g0 D$ W; D
934684 ALLEGRO_EDITOR MANUFACT The relation between the linear dimension and the symbol breaks., v1 v: z0 W( k C
935836 SCM SCHGEN ASA crashes when generating Flat Document Schematic# ~# `0 J$ G- v( A' r9 i1 s/ [
937165 SCM SCHGEN Can't generate Schematic
+ J$ x+ _; {. f( [% d! Z- V937292 CAPTURE GENERAL Memory usage keeps on growing and finally gets exhausted while search
+ c# F/ v* G, s/ Z" h- ^2 _# n# l937322 CONCEPT_HDL CORE Master.tag file alters the sequence of the files and Genview fails
! V3 G* c T2 x: l! o! _1 r* I5 x939135 CONCEPT_HDL CORE Unable to uprev a 16.3 Design to 16.5 with DEHDL-L License p' X [- }& p# p! m* F8 s# c
940373 CAPTURE TCL_INTERFACE Enhancement: TCL command to add nets to Netgroup
; w1 h. g, q% T4 P* e- @/ K+ N0 l940547 TDA CORE ERROR(SPDWSD-69): highspeed cannot be checked in8 E4 W6 _0 |+ t8 ]2 L
940607 SIG_EXPLORER OTHER Inconsistancy in License usage for opening sigxp -orcad2 @$ ]& h" _' ?' o7 m% B
940790 F2B PACKAGERXL User doesn't want to display pin numbers after Export Physical 16.5.3 e$ @" o# F- ]8 b: p: v
940944 SIG_EXPLORER OTHER Inconsistant license usage while opening Orcad PCB SI using allegro -sq -orcad and allegro -sq
2 n/ r$ m0 G* C+ O, `' J; A; L941354 CAPTURE NETGROUPS Enhancement: Option to rename the unnamed NetGroups
% x- t1 [9 n. ?. q941455 ALLEGRO_EDITOR MANUFACT The Dimensioned mechanical symbol when placed in the board does not show all the dimensions.- `* K+ O9 @/ y4 |3 N$ I
941863 ALLEGRO_EDITOR EDIT_ETCH Different behavior of design in v16_3 & v16_5 when add connect is executed on a segment thru script
4 M% V7 m" o# v/ D1 l* @941881 CONCEPT_HDL COMP_BROWSER How can I suppress the dialog from universalbrowser -genlibindex?
" R$ t0 R M( J& h* S, H942474 CAPTURE NETGROUPS NetGroup member type of last added member must be remembered by Capture
9 W- V. K) [7 V8 w942522 CAPTURE GEN_BOM Export in excel check mark doesn't invoked BOM in Excel
( _9 ]% J+ N7 L7 Q6 D& @8 [942557 PCB_LIBRARIAN EXPORT_OTHER PDV Export to Capture crash
5 e2 C7 j" a0 n5 N; W; H5 W/ g9 _942569 ALLEGRO_EDITOR MANUFACT Dimension move and change text deletes leaderless balloon) K7 W1 K, n3 D
942573 ALLEGRO_EDITOR MANUFACT Balloon type parameter has no effect on leaderless balloon.6 t! \, }4 _) \2 K
942613 CONCEPT_HDL CORE Genview supports only SCHEMATIC/SYMBOL/VERILOG/VHDL views as input type. .xcon not recongnised8 H; y" p+ h0 O$ b9 Q% W
943032 SCM OTHER ASA is not passing the correct reuse_module name to Allegro PCB layout.
7 ^ H2 q' b. q; e. O943401 CAPTURE NETGROUPS Alphabetical ordering of NetGroups in Place NetGroup8 K# E; ?& E: y/ M3 P5 H% ~
944006 ALLEGRO_EDITOR EDIT_ETCH Vias added to shapes behave differently
/ R; b5 |$ R: @& _944367 CONCEPT_HDL OTHER Too late to do Model Assingment in conceptHDL 16.59 t: P+ K2 q7 M2 R1 k. j+ G2 ?
944788 ALLEGRO_EDITOR GRAPHICS Oblong Pad shows unexpected lines
6 A9 n* f9 C. y4 I0 `' l; g945221 CONSTRAINT_MGR RETAIN_CNS CM Conflict Resolution fails on more complex designs using ECSets and constraints
4 z- v6 F p7 p( ^4 T5 b946270 ALLEGRO_EDITOR PLACEMENT The Rotation Type was changed to "Absoute" if the "iangle 90" use at placementedit mode of spb16.5
) A" E' B, V) U( U946350 F2B DESIGNVARI Variant Editor rename function removes all components
3 j& P' f5 U) }946380 F2B DESIGNVARI Some VARIANTX properties are hard some soft - why?
A: q0 |9 ~, |: T1 ^1 J946419 SIG_INTEGRITY SIMULATION Cannot select component on BoardModel for controller in bus setup form' I# V2 {0 ~0 w2 n' q( t% T
946458 SCM SCHGEN Schematic generator adding an unnecessary page
$ [$ \! X0 U3 O" f947667 ALLEGRO_EDITOR PADS_IN Need support for PADS-POWERPCB-V9.3-BASIC5 k" ]" S! ~9 } w P2 i( o! L: D
947789 ALLEGRO_EDITOR MENTOR mbs2brd crashes during translation on the attached design.
; C& x6 ]9 N) F- @948110 CONCEPT_HDL CONSTRAINT_MGR Concept HDL craches when opening SigXP from CM
: j, o' X q" V% w+ ~950970 ALLEGRO_EDITOR MANUFACT Unable to generate artwork, dbdoctor fails to fix errors.
, c& \' r" s s5 n) w/ D1 q- |3 ~951901 ALLEGRO_EDITOR EDIT_ETCH In 16.5 add connect to same net is shoved
3 g x1 e: e& A- r' L9 {951919 ALLEGRO_EDITOR OTHER Exported package symbol soldermask and pastemask padstack locations not the same as original
. l. C8 h! w+ S( M+ v951926 CONSTRAINT_MGR OTHER What is MaestroNotifyNotSetReport.txt file?
7 F% [% }6 T; C# g3 E# z. `3 I' R. V951939 F2B PACKAGERXL Uprev to 16.5 is changing refdes for some pages
3 K0 k' j/ ]# s; z3 {951983 CONCEPT_HDL INFRA Problems converting an Allegro design from 16.3 to 16.5
; Z# }4 P' u" l- E2 {( ?952057 SCM PACKAGER Export Physical does not works correctly from SCM
; L2 Q6 |8 `' v9 r# Q- O. B952217 ALLEGRO_EDITOR GRAPHICS crash when opening 3d viewer in PCB Editor. |7 B+ a4 Q% a: ^3 y
952634 CONCEPT_HDL CHECKPLUS Checkplus logical rule fails on a design which packages fine in 16.5. Q2 A- L3 H# m; S
953018 APD REPORTS Shape affects Package Report result./ }- P0 w' f4 X
953337 ALLEGRO_EDITOR OTHER Allow netname and padstack names to be visible for testpoint vias when viewed in Allegro PDF Publisher.- G J8 R1 z. L, S2 _( a- h
953827 ALLEGRO_EDITOR EDIT_ETCH Snake Breakout function crashed Allegro
2 I$ U# Q$ a7 r953918 GRE CORE GRE cannot route second and third row of pad in die symbol.
8 ]5 R! c" |& B954055 CONCEPT_HDL CREFER Crefer fails with UNC install path3 D O9 f3 S6 l/ p* [5 I
954920 SIG_INTEGRITY CIRCUIT_BUILDER Each neighbor crosstalk simulation crashes or returns blank report
$ D6 |/ @+ _* D
2 y$ C7 g# ~+ u* o# b, eDATE: 11-7-2011 HOTFIX VERSION: 010
3 k9 c# C+ r, N. u6 `===================================================================================================================================" v& z x3 k5 C7 `; }2 Z
CCRID PRODUCT PRODUCTLEVEL2 TITLE
' t$ E7 x# w7 ]# p# Q$ c$ X===================================================================================================================================
' `1 L, I. J; m$ y, o% E658866 ALLEGRO_EDITOR EDIT_ETCH enhancement option - so that Sliding a via inside a pad does not create a cline6 o6 `9 @" f, \1 w2 [- i* ] i
928624 ALLEGRO_EDITOR GRAPHICS Layer visibility control for 3D Viewer
' P( Y1 f; M: Q) W; t934991 SPECCTRA LICENSING Specctra_adv option is not working correctly for PA3100 plus PS3500 license in v16.5 tiering profile( [4 M0 v0 d# b* n( i% e
938073 ALLEGRO_EDITOR PLOTTING Plot Page size A0 and A1 with problem* {3 n" q" ~8 Z9 E
938128 ALLEGRO_EDITOR DRC_CONSTR DRC changes when do update DRC.
/ O( Z/ p; Y9 T" A5 v; X, k938648 ALLEGRO_EDITOR GRAPHICS Enh - Requesting a way such that Package keepout appears transparent in 3D Viewer/ C' q, }* {9 `- }* ^
940518 SIP_LAYOUT SYMB_EDIT_APPMOD Swap pins command doesn't complete
+ k1 |. y) R Y' C& Z8 H941426 CONCEPT_HDL COPY_PROJECT Copy Project fails - Updating opf view This can't happen!
/ ]2 B8 _! O, p. l' j941499 ALLEGRO_EDITOR DRAFTING BUG imit Tolerance isnot working for Dimensioning
% `3 t& ~% u8 @ I+ a941814 CONCEPT_HDL CREFER CreferHDL crashes during ScheGen2 S& q& w* P! K1 {! G( _
942914 SIG_INTEGRITY OTHER ZAxis delay calculation3 _' C4 w# _- f4 R9 r3 b3 X) E! ^
943053 ALLEGRO_EDITOR SHAPE Modifying the Board Outline shape will cause the tool to crash
. n0 i! \8 [' a8 L945321 SIP_LAYOUT EXPORT_DATA generation of a xml file from cdnsip for shrunken die" d. Z6 X0 l o) L
945350 ALLEGRO_EDITOR SHAPE iPick does not work on shape boundary edit.7 h2 @8 _; T4 ?+ ?8 [
945449 APD SKILL When they create a new menu entry with skill APD crashes with next menu selection.
$ I( O' h* g' I! M2 Q946390 ALLEGRO_EDITOR DRAFTING refresh_symbol crash when trying to refresh mech sym that has dimensions6 ]9 S9 w3 ~) y; B; W1 _3 c
946401 APD EXPORT_DATA stream out gdsII results in shorting of PWR/GND nets due to elongated etch3 @8 }% l" ]* e7 L/ T+ R, J1 p
946819 SIP_LAYOUT DEGASSING Shape degass command
6 R: c* _! Z: T8 z946869 ALLEGRO_EDITOR OTHER Allegro PDF arc representation needs cleaned up; z$ h C. A! W9 P. n
947230 ALLEGRO_EDITOR SKILL Skill execution crash Allegro 16.5 but work correctly with Allegro 16.30 y1 A: d& f$ T7 g
947603 ALLEGRO_EDITOR OTHER Component Properties (Default or User Defined) not transferred to PDF file: Y$ C6 G( [, ^+ p- ^$ d
950995 SIG_INTEGRITY OTHER Netrev fatal error when importing logic6 Q! }! C: `2 K ]+ I
951123 ALLEGRO_EDITOR INTERFACES IPC fails to output drill hole info in columns 33-37/ \: R. i8 r( C8 k+ B% {( b
951557 CONCEPT_HDL CORE Cannot create the entity folder for old plumbing symbol
2 [; {5 F& }$ z
( a0 m2 Z [% m' jDATE: 10-26-2011 HOTFIX VERSION: 009
6 Q$ h' n& k! x# C' `===================================================================================================================================
. N7 D2 `; y! R: bCCRID PRODUCT PRODUCTLEVEL2 TITLE8 T( }3 p5 B1 Z& o7 T0 _
===================================================================================================================================
! `/ h/ M3 I3 }6 P; b8 B945788 CONCEPT_HDL CORE Some component properties on the parts are incorrectly changed after Import Sheet# y* R& c% W& f# A
945789 ADW LRM Some component instances are not updated by LRM even though cache ptf is updated from reference
3 M2 u( A% m9 V+ m6 k
/ O# }" e* Z6 B# gDATE: 10-21-2011 HOTFIX VERSION: 008
) r8 R# k$ o3 n2 s6 p; X$ e===================================================================================================================================. |; v! j; @8 J2 Y" Y
CCRID PRODUCT PRODUCTLEVEL2 TITLE
! r9 V" u$ `) Q3 a/ I7 i2 G===================================================================================================================================9 @# N( D; |& X
906827 ALLEGRO_EDITOR DATABASE Logic > Parts logic does not work correctly.* Z5 B: k3 N, E: i& k
923346 CONCEPT_HDL CORE Not able to move the reference designators inside hierarchal blocks after uprev to 16.5
) M7 p% _8 C6 U- x1 }! j I" X926347 ADW COMPONENT_BROWSE Usability- Libflow Part check in comment should end up in Comments attribute for UCB/Designer to see it- T' d( c# }6 M! r! V$ |1 E {
929348 F2B BOM Warning 007: Invalid output file path name! O/ k7 n6 d/ ^7 K6 F
929777 CONCEPT_HDL OTHER Component Revision Manager gives internal error) k, q0 l. N. t* X$ h
930783 CONCEPT_HDL CORE Painting with groups with default colors- ^ {2 i* I9 O( J$ p
936748 ALLEGRO_EDITOR INTERACTIV "Unplace Component" menu inconsistent between General Edit and Placement Edit Mode.. K0 W2 U) B2 Q# L0 {
938143 ALLEGRO_EDITOR CREATE_SYM Why is this Extra Property 'ECSET_MAPPING_ERROR
3 l" n: D" t- F2 T" x938281 SIP_RF OTHER export_chips creating bad data when symbol is split and contains V- V+ pins
* h+ f! c: u+ J4 u; p938812 ALLEGRO_EDITOR SYMBOL Cannot create a BSM with this DRA, errors out but does not state a reason.! K/ ^' g# L( L' D
939075 CAPTURE TCL_INTERFACE Texts are getting garbled in command window
0 t( k; T8 x4 U" ?# j5 C9 }939193 F2B PACKAGERXL ERROR(SPCODD-439): Connectivity server is unable to load the design.5 @; t" x0 g% a* X: ]* A9 a' b
939199 CONCEPT_HDL DOC "Retain electrical constraint on net" mismatch between schematic (YES) and design (NO)
' a) u# i+ b9 O! e- O# ?939346 ALLEGRO_EDITOR SHAPE Shape disappears when updating with variable shape_rki_autoclip set.
9 k7 S+ i7 ~) M: e! ^9 [939901 CONCEPT_HDL INFRA NET_SPACING_TYPE shows �?� on lower hierarchy level nets after Upreving to 16.5 version.9 g: f2 H- U" |- m; `& E
939918 PSPICE PROBE Print > Preview for output file causes Pspice crash.
. q% O' D' f6 a4 B940217 CONCEPT_HDL COMP_BROWSER UCB reports 'No Symbol found for the part'
$ N6 h M5 u% W940835 CONCEPT_HDL INFRA Desing package different after uprev to 16.5 where comp instance propeties are lost lost3 e+ E0 g1 `" ~/ J! F
941125 ALLEGRO_EDITOR DATABASE Performance advisor doesn't skip non plated slot padstacks) c, S k6 w$ r- v" N9 X5 z
941876 SIG_INTEGRITY OTHER Illegal model name cause pxl fail in 16.3
9 |( H, o: k3 t( o$ U942210 SCM OTHER Is the Project File argument is being correctly passed?
, {. c/ I5 X2 w942274 CAPTURE PROJECT_MANAGER Crash on renaming a Design Cache part in Project Manage after doing replace cache8 u' T i- F$ x) c& T
942839 ALLEGRO_EDITOR GRAPHICS Graphics Issue- Pads are not visible
2 i" @& }3 W6 E( S3 l! J9 O$ R943055 ALLEGRO_EDITOR SKILL axlDBCreatePropDictEntry causes application to crash2 `. e$ T* f$ y6 R
7 D& }: u6 g0 {# L) B- u- r3 B0 }9 v
DATE: 10-21-2011 HOTFIX VERSION: 007
& J; S+ g0 S, A( w6 Y) U===================================================================================================================================4 j. m0 o7 }( K- v
CCRID PRODUCT PRODUCTLEVEL2 TITLE
, I2 s: A2 z. @0 W: x===================================================================================================================================
( O" {7 n" M- g841096 APD WIREBOND Function required which to check wire not in die pad center.
8 W+ z, ]: ?* i9 ]4 s903263 CAPTURE SCHEMATIC_EDITOR ENH: Selecting parent netgroup must select the underlying netgroup bits.
! r- W6 o6 o; m5 |% ~3 O8 ]) D906692 ADW LRM LRM window is always in front when opening a project" z w$ O6 f$ k0 V4 ?
912942 APD WIREBOND constraint driven wire bonding, Q" A" Q; u3 W B. i
912951 CONCEPT_HDL CONSTRAINT_MGR Need to manage temporary files on Linux systems+ a" }* d7 K3 y! s
915178 SIP_LAYOUT DIE_STACK_EDITOR Die Pad names changing when updating Die in a design
, [' p0 y: d6 ]( o917887 PCB_LIBRARIAN VERIFICATION Part should not be released if the alt_symbols has errors
* D5 a4 A7 a9 e8 i- }923315 SIG_INTEGRITY GEOMETRY_EXTRACT crosstalk simulation fails with TMP popup failure$ _4 e7 z- p! c- Q& t( t3 }
927382 CONCEPT_HDL CHECKPLUS 'Verify Symbol' forces the use of 'Concept_HDL_Studio' license
( |9 l" M3 v- n927664 CONCEPT_HDL CONSTRAINT_MGR Internal Error disposeipsp- h. B6 \) M7 j' p% G
930152 CAPTURE NETGROUPS Scalar net names when being connected to net group overlap when connections are made one by one
0 k% C% _. M! }+ ^9 B) g& x930180 CIS LINK_DATABASE_PA Visible property position on schematic get reset on "link database part" operation! f: G+ h3 V. {
930188 CAPTURE DATABASE Capture 16.5 crashes in being re-invoked.
& d9 Z5 v7 {) _% A3 z( ?5 E930541 CAPTURE NETGROUPS NETGROUP element renaming doesn' renames the associated net ?
) k- ~6 o: x6 A; U' m930866 PDN_ANALYSIS SETUP OrCAD PCB SI Session crashes when we open PDN Analysis with "OrCAD PCB SI" license./ T5 K, t- d, f! p1 K
930926 ALLEGRO_EDITOR GRAPHICS Via and Holes not visible eventhough set to Visible in Color form
v1 y9 S8 ~9 |& t* L: I931274 ALLEGRO_EDITOR DRC_CONSTR Negative Plane Islands waived DRCs reappear after performing update DRC.
) w8 J" V) [6 W: C& A( F7 n# ?932091 CONCEPT_HDL CORE Prop attached to SIG_NAME property
8 D( i' E4 W6 j$ X8 D& G932255 ALLEGRO_EDITOR GRAPHICS Change in Zoom level makes arc segment to disappear/ y" T, b$ |( e/ E0 p
932292 ADW LRM LRM crashes during Update operation on a customer design. \0 m8 N. c! [6 |( ]
932639 SIG_INTEGRITY OTHER Add Connect command hangs for about 14 seconds and then returns.$ e8 I/ X Z, l6 D, i* q, }
932704 APD DEGASSING Shape > Degass never finishes on large GND plane2 f* g; g/ X" \) {3 Q& ^+ \
932871 APD GRAPHICS could not see cursor as infinite
; a$ I7 v1 a3 P* D, w/ I/ E932882 CAPTURE SCHEMATIC_EDITOR Capture crash with FIND command - ISR05
1 ^9 u- b2 X/ b932969 CONCEPT_HDL CORE ConceptHDL crashes when you save the design in 165 > hotfix #05
5 j8 ?/ Q$ ~/ D+ q& k6 B1 }933024 CAPTURE NETGROUPS Naming restrictions for NetGroup members
5 k5 I8 ^! ?7 S1 d9 ^" s* u: p933145 F2B PACKAGERXL Add Subdesign list is truncated in Force SubDesign Design Name pulldown
8 w" Q5 G7 |) y+ n. f0 F933214 APD ARTWORK Film area report is larger when fillets are removed
% X2 d/ c6 `5 v z933356 CONCEPT_HDL CORE Net prop display size become 0 if it was attached to SIG_NAME prop.
$ x; H0 {# {6 p$ d) {933532 ALLEGRO_EDITOR COLOR Bad color assign and initialisation during creation of new subclass
" v, E% O/ o. A933549 ALLEGRO_EDITOR OTHER Chart text missing in export PDF file.; R- ~ U3 H2 _( z( Y1 H
934008 ALLEGRO_EDITOR REFRESH refresh symbol updates symbol text to some unexpected values M8 M9 U9 A3 p% [9 g
934031 ALLEGRO_EDITOR DRC_CONSTR Bug : Update DRC removes Waived status for some DRCs
+ F: F. R/ n- c- M934087 CONCEPT_HDL CORE Opening DEHDL and Model Assignment before design loads causes crash
2 [% n9 }4 P. J4 T6 _- p" V934396 CAPTURE SCHEMATIC_EDITOR Find operation is not searching power symbols with + or - signs.* `0 y0 X( q9 w5 d8 H
934533 F2B DESIGNVARI The Variant Editor errors are not written to the variants.lst file. Z5 E) Y, F& d) L+ H
934811 SIP_LAYOUT UI_FORMS CDNSIP should not hang if contraction value in z-copy command is out-of-bound. z$ K% i7 b% ]6 V$ O0 `
934909 SCM UI Require support for running script on loading a design in SCM% }5 L8 S& B$ \. \; k5 D
935632 CAPTURE SCHEMATIC_EDITOR SHIFT+Mouse wheel scroll(horizontal) of page is not working in Auto Wire Mode.
9 O# g( L+ B$ N6 X. I1 S5 }2 c" i935794 ALLEGRO_EDITOR SHAPE BUG:Shape not filled in 16.5 but it does in 16.36 n; D: c: T% f1 s% O) H
935988 ALLEGRO_EDITOR INTERFACES When attempting to downrev this 16.5 design to 16.3 the tool will crash
+ _2 \0 v+ u4 F( I936056 ALLEGRO_EDITOR DRC_CONSTR place_manual crash while moving mirrrored symbol
% B% j+ ]1 J& O- S" Y1 b; b936098 ALLEGRO_EDITOR SKILL axlDBCreateCloseShape does not work correctly.
) \% W: q, o! f, t# q/ I# c: D936212 ALLEGRO_EDITOR INTERFACES DXF not created if Blocks created for Symbol and padstack; Z: t# M9 |, N2 o6 B2 Q% O! ~" f
936797 CONCEPT_HDL COPY_PROJECT Copy Project crash
* [: b8 ~3 j( B1 U936808 ALLEGRO_EDITOR DATABASE Allegro crash replace mechanical symbol
1 {6 U8 P$ O( G, s w1 A j936853 CONCEPT_HDL CONSTRAINT_MGR DEHDL crashes when trying to extract net from CM& | l) V9 u3 c4 |1 Y
937087 CIS DESIGN_VARIANT Upreved design becomes very slow in Variant view mode. DELEET THE DESIGN AFTER RESOLVING THE ISSUE
/ U; W) @2 R- U5 N6 ^' ^) |9 ~937173 CAPTURE OTHER Wrong license information "UNLICENSED" in Capture >> Help >> About
& H/ }1 g1 {! g' q7 s+ ^# [937290 APD PLATING_BAR Plating Bar checks does not recognize connection made through etchback through shape.$ k; |6 _; G# \1 x, d, @. K
937411 ALLEGRO_EDITOR DATABASE downrev_library reading from one directory and writing to another hangs the command.7 e6 C5 u& H1 c: Z- T- U& ^
938235 SIP_LAYOUT STREAM_IF Die Orientation is not correct after importing a stream file.
# i* Z( s1 f; ?3 @938273 ALLEGRO_EDITOR OTHER PDF export is is not opening viewer with ads_sdlog variable set1 { p2 U+ I" W' `: O# @( A9 z
, K* E6 }" p, K+ f. I
DATE: 09-16-2011 HOTFIX VERSION: 006
, Z! K( F+ y5 X; ]8 F# @===================================================================================================================================! A; ?1 T: O8 N7 Z6 [% `+ p/ ~
CCRID PRODUCT PRODUCTLEVEL2 TITLE
Z( {3 w$ N* m) b d===================================================================================================================================# U. \7 \. R& k0 x$ S4 y l* a+ h. z
820131 CONCEPT_HDL OTHER Moving symbols to other page will make Allegro components unplaced because logical_path changed.* ~0 X5 J6 Y. U! e5 r/ d7 I
863860 CONSTRAINT_MGR SCHEM_FTB CM should display or Local Interface and Global nets to help defining low level constraints
( A; ~5 O8 L) m. r4 Z919822 TDA CORE Cannot configure LDAP to only list the login name
% g ~* Y+ {$ I/ Z922907 ADW TDA ast_callout_file� directive in the BOM section is empty causes tda for show Access Denied error( `2 v+ H/ E2 M
924322 ADW COMPONENT_BROWSE Random - No instance properties are added on Add To Design (RMB or double click) from Search Results
% ^" P. m* W9 e" P8 _924448 F2B DESIGNVARI Design does not complete variant annotation
; x. ]5 Y; g, s; N% S' h3 c1 b6 M6 y925584 CONSTRAINT_MGR SCHEM_FTB 16.3 upreved Design passes the SLOT/Function Properties to PCB4 p M$ A6 F3 s3 B" E7 B$ Y4 Y
927102 ALLEGRO_EDITOR OTHER Question of Conductor Detailed Length Report6 D6 O8 w5 a) D2 s( {
927104 F2B DESIGNVARI Tools > Annotate variants crashes when there are ASCII characters in the property values
2 ~7 x2 [8 j2 Y* A# M+ j p927142 F2B DESIGNVARI Incorrect pop up asking while executing variant editor from the command line
; I, C2 l8 _ k( b. X- z927166 CAPTURE NETLIST_ALLEGRO ENH: Feature like NET_SHORT in Capture Allegro flow which allows user to short 2 or more power nets
) s( R$ L' ^& \2 H! ]) ]927410 ALLEGRO_EDITOR DATABASE ERROR(SPMHUT-144): Illegal arc specification error when Run DBDoctor
( |5 R6 y# r+ |( Q$ V( ?927475 CONCEPT_HDL CORE About forcereset command of nconcepthdl" a+ i M( y3 q( }
927498 CONCEPT_HDL CORE Pin_Name starting with minus causes incorrect behavior for $PN display7 k6 t7 O* H/ G1 a9 ]7 z R
927608 ALLEGRO_EDITOR PADS_IN Import PADs fails with error message: Failed to close the Allegro database
8 j3 n5 e; U ?# Q927637 SCM CONSTRAINT_MGR ASA crashes on change root and also performance is too slow.
! J \0 V* @; ]6 M928429 SIG_INTEGRITY OTHER Request - Package Wizard to work in PCB SI.$ M+ b2 ?& {6 u2 o2 [" k9 v; z" P
928483 ALLEGRO_EDITOR DRC_CONSTR Running Update DRC removes Via List DRC Error when via is actually not in the list- V6 S5 [7 a5 Q3 {, F! v
928738 PSPICE PROBE Y-axis grid settings for multiple plots' [3 r: z, J0 c, k$ ^# C
928748 PSPICE PROBE Cursor width settings not saved( t6 N7 z* y$ B$ O; a. q! g: I
928779 CONCEPT_HDL CORE Error (1053) occurs on a copied part in SPB165 release
4 Q3 z" R9 U; v; L6 A1 j928838 CONCEPT_HDL CONSTRAINT_MGR ECSets not migrated in 16.5
& ^8 P9 K% g- Z/ h% \5 P928885 SIG_EXPLORER EXTRACTTOP PCB SI crashes when extracting a net from Probe
g5 m3 p: }: \6 r/ a929284 CONCEPT_HDL ARCHIVER archive does not create a zip file: a8 `# o; m& Z0 L2 Q: ?0 a3 U
929542 SIP_LAYOUT DIE_ABSTRACT_IF net issue of multiple ports of co-design die in SiP: l, g; b. [3 K1 e8 [) ~
929656 ALLEGRO_EDITOR PADS_IN PADS translation fails with Microsoft Visual C++ Runtime Library error1 N# B' {* q# g8 t3 B
930063 ALLEGRO_EDITOR TESTPREP Test prep crash Allego when it can not create pin escape) w/ m6 m; P8 n- ?/ U1 F! ?) c
930217 CAPTURE NETGROUPS Net aliases doen't gets assigend to bus bits if bus name is checked in NETGROUP.
! g; d* S: M3 |, p7 R$ H930355 SIP_LAYOUT WIREBOND about "wirebond add nonstandard" command0 R. N `& k6 v/ C
930607 APD OTHER Layer mapping information is reomved from Layer conversion file upon exporting DXF from board file." w) W3 T4 p+ p
930646 ALLEGRO_EDITOR DRAFTING Bug - Adding Linear Dimenstion for ISO standard add the Angle information as well
3 R) U) r0 [* `; N6 P930894 CAPTURE TCL_INTERFACE PDF export doesn't creates property file if some symbols are used in page name/folder name
7 J2 J8 E( j+ y( P( r, K7 h4 U930944 ALLEGRO_EDITOR OTHER Setting variable 'appmode' equal to 'none' is not changing the Application Mode when reinvoked
( a, n L2 j5 n2 X930978 ALLEGRO_EDITOR SCHEM_FTB 3rd party netin error - Pin is connected to net <netname> not reconnected no longer happens
! _' P+ H0 s/ ?( O931248 ALLEGRO_EDITOR DRC_CONSTR Match Group was removed if member nets became xnets.
, t+ x+ B6 r& n! `8 y6 Y931278 CONCEPT_HDL INFRA $PN gets copied when upreving design from 16.2 to 16.5 version
; o4 g/ }: |6 a* P; z! m! ]3 C0 ?, L931349 CONCEPT_HDL COMP_BROWSER DEHDL craches and corrupts connectivity file when using Modify command extensivly.
$ S6 G* j% Z {% P1 C, g
0 [' |! H' f* a) p3 oDATE: 08-31-2011 HOTFIX VERSION: 005
2 O2 K# m: X1 w& ]1 q===================================================================================================================================* E% J& P$ p- A1 N4 D5 ^: {7 g
CCRID PRODUCT PRODUCTLEVEL2 TITLE; _8 N6 E0 G4 ?* _ W6 N$ n. Q! f
===================================================================================================================================
* z# y% m' o$ N Q# E* s825848 ALLEGRO_EDITOR SHAPE Shape not filled when edges from 2 RKO shapes touch around mouting hole7 U+ M7 I% }. j. p
837723 CAPTURE PROPERTY_EDITOR Occurrences of external design not related to current root should not show" b1 L1 M _* r( F+ @% t7 k
891079 CONCEPT_HDL CORE DEHDL crashes with large number of commands in Winodws mode( h$ Q/ _( W$ l) l: `7 N H% H
910908 SIG_EXPLORER OTHER Cannot open top if Tx AMI dll name contain more than 2 dot.' e# ^0 \' N7 d7 i; q
914036 CAPTURE LIBRARY ENH: Option to delete a corrupted part from a library and leaving other parts intact in the library.) @1 u T/ p' D) r- j
914679 ALLEGRO_EDITOR INTERACTIV Custom toolbars are not retained when switching between brd to dra and back to brd file using the File > Recent Designs: b- S! [0 h# W7 S! _$ M
914870 MODEL_INTEGRIT OTHER mergedml fails to merger 2 DML files from the model integrity4 \& `% ]# V8 J$ b& ?: O6 D* O
915645 ALLEGRO_EDITOR MANUFACT Allow the user to place the cross-section chart at a desired location
q# _8 O. K$ A! Z, `! I, r9 `915653 ALLEGRO_EDITOR INTERACTIV unable to delete non-etch shape
% u* f! ]* N/ R B& V/ }4 }915711 ALLEGRO_EDITOR MANUFACT dimensioning tolerancing by limit not working* f. \: O5 E- y; k) E# m7 |$ u+ v
916321 CAPTURE GEN_BOM letter limitation in include file
- x* \! a7 w( Z916907 CAPTURE SCHEMATICS uto Connect to Bus� should place the wire through non-connectivity objects
6 H. {8 A/ u$ e. s4 z920327 CONSTRAINT_MGR ANALYSIS The TotalEtchLength predicate in Constraint Manager does not work for a netclass with a bus.
8 I2 O! ]. E. X- h* Z X' Y; M920753 ALLEGRO_EDITOR GRAPHICS If I confirm to padshape with zoom-in after install the s002 It was changed to wrong shape.
$ g# G) Q" e) e921097 ALLEGRO_EDITOR GRAPHICS Padstack seen partail filled when Zoomed in even "static_shapes_fill_solid" is set. A, @% c. r8 F& ~3 } Z$ m
921226 ALLEGRO_EDITOR DRAFTING Unable to select Package Geometry class when dimensioning in the symbol editor.; J* i7 k; x- U
921623 ALLEGRO_EDITOR GRAPHICS Bug : Symbol not visible when zoomed in 16.5 S002
7 P7 i3 p8 o {6 x Q921891 ALLEGRO_EDITOR DRAFTING dimensions are lost after downrev(ing) a SPB 16.5 design with associative dimensions
! q: k/ C6 i; {2 P c9 H2 {. l921937 ALLEGRO_EDITOR COLOR Padstacks with shape symbol are not showing correctly
7 B1 u5 N! N$ `% T4 U. l922066 CONSTRAINT_MGR ANALYSIS Custom measurement Actual not being cleared when layout changes.9 a' s6 Z0 T, G8 j* Q3 s
922117 PSPICE PROBE Label colors are not correct in Probe
: W! |* q. \3 w1 L$ a$ q5 g922519 ALLEGRO_EDITOR SKILL add_bviaarray command fails for some clines but not all: i; r) d6 M' j7 l
923224 ALLEGRO_EDITOR GRAPHICS Thermal flash Display problem in Allegro v16.5 Hotfix S002
# v5 t$ Q5 C N5 g3 x. x: j923286 CAPTURE DRC DRC markers not reported for undefined RefDes
4 b' z- L2 Z6 [' E- V923362 ALLEGRO_EDITOR PLOTTING Print to Postscript file not correct in 16.5
) V: X; X/ B+ i4 q923416 ALLEGRO_EDITOR PAD_EDITOR Pad Designer crash on clicking on the Arrow before Soldermask_top, m+ [3 q9 q3 P* J0 v
923507 CONCEPT_HDL CONCEPT-PCBDW The function of Import Design in the SPB16.5 Design Entry HDL (for data of ADW15.5_S23 + SPB16.3), b7 Y9 P: Y1 e' p
923910 CIS PART_MANAGER Copy & Paste operation from Part Manager copies properties only to first section of the part.
! q) B1 b d( r i7 w923913 CAPTURE PROJECT_MANAGER Capture runs slow on attached design2 ^' q( |1 h0 ~7 F; i: X7 O# M3 H+ Y
923937 CONCEPT_HDL CORE Back annotation time significantly increased with the metadata generation on2 j! [; F3 k% J* T8 m3 O
923949 ALLEGRO_EDITOR INTERFACES Incremental DXF_IN gives 'Invalid subclass' error8 _) C: z( H6 j, d+ T* i( S8 j# P
924458 SCM OTHER Project > Export > Schematics crashes
$ I' ]% h7 q* e. j, |" W9 p924621 ALLEGRO_EDITOR SHAPE Dynamic shapes are disappearing upon updating them to smooth.
5 s$ B- ?% P8 q7 L& J6 \# U925193 SIG_INTEGRITY FIELD_SOLVERS Diffential Impedance (DiffZ0) values computed in the layer stack-up is incorrect
: ~7 \+ w: z% D' V925195 ALLEGRO_EDITOR DRC_CONSTR Incorrect pin to shape DRC error: o* \9 g3 d9 q) l M9 U! u8 ^
925338 CONCEPT_HDL CORE This application has requested the Runtime to terminate it in an unusual way
4 N% Z: a9 f( ?' ~% D. r: H5 c925435 CAPTURE TCL_INTERFACE Capture crashes if ave design as UPPERCASE� option is disabled.* B/ f3 s7 h2 e. ^! G$ t
925530 SIG_INTEGRITY OTHER Why the single line impedance value for Top and Bottom layers are different for this design?, M) v5 X" j, Q
925864 ALLEGRO_EDITOR DRAFTING Ability to add dimensioning to different CLASS/SUBCLASS# |9 G) \, Z) M; A/ X+ B) f
925976 ALLEGRO_EDITOR MENTOR mbs2brd fails to import data
/ U! h- z6 n& J926409 SIP_LAYOUT DRAFTING Exporting a 16.5 design to 16.3 will cause the leader/dimesion lines to be removed.
* y1 x; Y% S; V. [3 O" Y6 r4 W926443 CONCEPT_HDL CONSTRAINT_MGR In new 16.3 "035" ISR Concept2cm will crash with error.. n3 }- k% c2 M- K
926503 CAPTURE GENERAL Memory leak Capture/Pspice
- w0 `' g8 f5 B926553 CONCEPT_HDL CONSTRAINT_MGR CMGR ERROR There is no net in the Cset that has pins matching those in net 1 in the Xnet
. X3 D8 N5 L' _& a9 Q- k926691 ALLEGRO_EDITOR OTHER Crash while Importing Technology File in CM, with Overwrite Constraints.# N0 ~7 M0 p. M( c9 U" G: Z
926887 CONSTRAINT_MGR CONCEPT_HDL Pin pairs lost after Export Physical, d2 D8 C4 V+ W( m
927159 CONCEPT_HDL CONSTRAINT_MGR Export Physical fails due to errors in ConCM.log when SIGNAL_MODEL injected property is ''
2 i- E3 E4 B% t9 x2 R# G9 v+ l1 C' z" Z
DATE: 08-19-2011 HOTFIX VERSION: 004% G$ D# i' x6 n: {
===================================================================================================================================
. R6 m: }, `. x3 C' ]- DCCRID PRODUCT PRODUCTLEVEL2 TITLE
* V/ g. }* b: l/ u% P1 ~9 a===================================================================================================================================1 w2 v- Z! e% q0 A
785417 CONCEPT_HDL COPY_PROJECT copyprojectui crashes with a Windows runtime error6 l2 q8 n! z% Z
851044 CAPTURE GEN_BOM "Export BOM report to Excel" does not appear in the Standard Bill of Material Window.
, z* _5 a" Q- }6 M" U868216 PSPICE MODELEDITOR Encryption of subckt names, internal nodes, comments
5 V# l! ]' p& \, x870247 PSPICE SIMULATOR Encrypt a model and simulate it, info about inside nodes being dumped in the probe file: S& i+ a. I' C1 L+ M( y- R
877091 CAPTURE SCHEMATICS Save JPEG, GIF, PNG and other image formats in the database in its compressed form
8 C: e( Q$ n# ] k. e$ k2 G894059 CAPTURE OTHER Enhancement: Adding column in edit>browse>parts window+ c* m* t2 A# F3 m7 }: G
895902 RF_PCB OTHER Alphanumerical allegro pin numbers are unusable in ADS 2009 Update 1
. O5 ^) b5 a6 H, X" `# }& J e8 M895919 RF_PCB OTHER Round trip Allegro to ADS to Allegro requirement: _# W- ]9 }" O% v4 r( ?; x: F; T4 y
903102 ALLEGRO_EDITOR OTHER Zcopy shape command for cline seems not to work correctly.
" N( V+ I3 b3 ?+ y+ k" Z905562 SIG_INTEGRITY SIGWAVE Noise margin seems not to be measured correctly with Eye Measure function.
# C! I$ L) D h# S909469 SCM TABLE ASA crashes when opening project/ {) R: Q+ ~, b
909595 APD LOGIC Inconsistency between export die text out and show element after pin swap
. q( o \$ W( a% Z0 o911123 CONCEPT_HDL CORE 16.2 Design uprev to 16.5 fails with ERROR SPCOCD-152# ` k9 w3 X6 l. o
911569 CAPTURE EE_INTERSHEET_RE Q: Why is capture assigning incorrect Irefs in attacehd design ?
% ]. r G% j; {915657 ALLEGRO_EDITOR OTHER Allegro PDF Publisher Mirror capability; h* Z. _& P2 |9 D5 E$ E
915755 CONCEPT_HDL CONSTRAINT_MGR Cannot view net in SigXP8 @: V4 p6 r4 x( C( z
916062 CAPTURE GENERAL Auto Wire Crashes Capture
: b$ X& U9 N5 m4 T2 X$ [2 d916820 F2B OTHER RF create netlist with problem
, G/ T9 L5 b) R# `5 X' f917967 ALLEGRO_EDITOR REFRESH Update symbol resets refdes location for bottom side components only./ U! B. Y8 I6 y% ?
919343 ALLEGRO_EDITOR PLACEMENT Place Manual is crashing the board file1 T- a1 @. N6 a3 C3 p1 p
919481 CONCEPT_HDL CHECKPLUS CheckPlus isGlobal function is not working; K0 X: {- V+ l; D! h. R
919510 CONCEPT_HDL PAGE_MGMT takes 10 min to insert page in DE HDL
. G$ T. a6 V. y& O! t" P4 e& Y# x919976 APD DATABASE Update Padstack to design crashed APD.
& t( H( e1 x) |! C920418 SIP_LAYOUT OTHER SiP enhancement to Auto Assign Pin Use to add ability to change the pin use definition
2 M$ s; A% }# k5 k. p5 W2 I920420 SIP_LAYOUT LOGIC SiP enhancement to Logic Auto Assign Net to display a dialouge Auto Pin Use assignment should be run
# [3 I E' H/ W- ?8 r( H920712 ALLEGRO_EDITOR ARTWORK Program has encountered a problem ... error when creating artwork s3 _ s( p7 d8 Q+ g
920763 ALLEGRO_EDITOR ARTWORK Soldermask gerber missing thru-hole pins
! f7 V1 i. K! V# c! G: c6 o2 `1 h. J920976 ALLEGRO_EDITOR GRAPHICS Question regarding the difference in the behavior of 3D Viewer w.r.t. height_min9 Q* K/ M* h( K, q0 j% F0 e1 T$ F
920993 ALLEGRO_EDITOR DRC_CONSTR Minimum Metal Spacing Error is detected on Same Net
/ y6 P! t; U6 t9 |" C5 x921727 ALLEGRO_EDITOR DRC_CONSTR Pad Boundary causing P/P drc to adjacent symbol.% Y+ {2 X4 i% J) N& _: |% ]
922579 CONCEPT_HDL CORE Xcon file gets corrupted upon Save of Hierarchical design with Global nets tied to interface nets
3 Y$ f# j- X7 f2 a7 x( i922592 CONCEPT_HDL CORE DE-HDL does not report illegal connection when Global Net tied to interface net using an Port symbol and named
( k; l5 s; I6 p- ~+ i6 l& _" U922758 ALLEGRO_EDITOR DATABASE Allegro crashes while placing second mechanical symbol with route keepin
1 C# [3 B7 V5 W. _0 W' O922839 ALLEGRO_EDITOR DFA The DFA drc display is unstable. n/ X8 ~* Y1 N/ B' N8 R; e
923293 ALLEGRO_EDITOR INTERFACES File> Export> IDX is failing for this design while creating an empty error log.0 W( k$ d% q& O. P. F3 r
924772 ADW PCBCACHE Import Sheet is not bringing in Parts used in the source pages into target cache ptf0 u: P8 a5 I" O( ]2 P6 f' i
& U- L8 q; [$ n4 S$ c' H$ k5 d
DATE: 08-4-2011 HOTFIX VERSION: 003
4 ]/ a) e0 U" B1 m, b=================================================================================================================================== b) u! B& U- `& M! Y# P
CCRID PRODUCT PRODUCTLEVEL2 TITLE
% I( h( U* I: r& _===================================================================================================================================: l* {" E; C* ^) {2 m
787414 CAPTURE PROPERTY_EDITOR Part value can be moved on schematic if a part has been copied to a new design and not saved yet." C5 X+ O! J5 E3 |2 H1 l( W$ ]' w" f' y
903898 PCB_LIBRARIAN GRAPHICAL_EDITOR PDV move symbol graphics and Undo causes corruption in graphics% s% @ J @9 B C
904287 ALLEGRO_EDITOR ARTWORK some cline with arc is missed, when creating artwork.4 I$ R6 N9 G3 H$ P
904418 CHANNEL_ANALYS SIMULATION channel analysis sim does not give valid result
0 X' x1 t: a1 t+ t I905777 SIG_INTEGRITY SIMULATION User gets popup message that halts an analysis until it is acknowledged
9 o* [0 r; f% x' d0 v4 P906139 SIG_INTEGRITY OTHER Bus sim result were cleared at the next run even if no preference changed.
: L1 g! d/ g. [908680 SIG_INTEGRITY OTHER Extra prop delay due to resistance
/ X5 P0 Z* q( G+ l- T909583 ALLEGRO_EDITOR SKILL axlPolyOperation AND operation is not working correctly., |% ^* v d5 _
910315 ADW LRM Import Design with ADW causes partmgr and pxl errors- Q/ @1 r0 v" b4 B
910689 CONCEPT_HDL CONSTRAINT_MGR NO_SWAP_COMP warning after uprev to 16.5
! w4 K$ j: \) d& E; D4 \0 {# r6 ]* i3 p911684 CONCEPT_HDL CONSTRAINT_MGR Attribute Definitions are incompatible for attribute 'HEADER'. when attempting to place in 16.5
9 q) C; P" f$ Z4 u* v; x912343 APD OTHER APD crash on trying to modify the padstack" } s. T, }' ~% `/ Q' q3 K
912384 PCB_LIBRARIAN CORE PDV Symbol Editor often freezes when moving groups objects by arrow keys
1 S4 w1 a$ V4 D' r2 k912853 APD OTHER Fillets lost when open in 16.3.
9 c7 y+ F! [1 x+ u/ F913586 ALLEGRO_EDITOR ARTWORK Cannot create the drill figures in this design.
: `+ M5 I8 r! u- h( q6 P) r914009 ALLEGRO_EDITOR DRC_CONSTR Diff impedance worksheet showing almost zero impedance for differential pair in attached testcase.6 \! `) f1 g9 o8 J8 s; J$ C
914110 CONCEPT_HDL OTHER DEHDL 16.5 Uprev overides property values on hierachical blocks
2 E V% F8 Z4 e: B7 {914264 F2B OTHER Cross Probing from DEHDL for global nets present inside block doesn highlight in PCB Editor.
3 {1 l; P K' k: I+ a5 q# t% i* q914309 CONCEPT_HDL CORE 16.5 DEHDL crash on saving the user design
4 Y. M ]+ G/ i* v6 U" i# ~914558 ALLEGRO_EDITOR ARTWORK Gerber6x00 output creates unpainted niche in a shape2 W% D6 Y# {& V% O
914633 ALLEGRO_EDITOR ARTWORK Artwork failing in v16.5 while the same design when downrev'd to 16.3 is working fine.( h: a, `* \+ D- t* M! Q
914634 ALLEGRO_EDITOR SKILL IsThrough flag for a padstack is reset3 P- D c5 x2 L8 b9 l; e
914746 ALLEGRO_EDITOR DRC_CONSTR DRC Update repeats takes longer on each successive pass.# I* O, W* |! `+ K$ x
914962 ALLEGRO_EDITOR SHAPE Corruption with Shape filling% u4 r6 P' B/ \! U2 G& Y
915583 CONCEPT_HDL CORE performance issues in 16.5 compared to 16.3
* T0 t+ i9 k1 J! y915630 PCB_LIBRARIAN OTHER Error when running SI Model Interface Comparison using IBIS models& c4 V3 `; {* p* ] l3 ^
915742 CONCEPT_HDL HDLDIRECT I get a newgenasym error and crash when trying to save the symbol, o$ l8 D8 C& f, V
916154 SCM NETLISTER scm crashes when exporting physical database to allegro
8 v5 d# _; O9 n0 a X916448 CAPTURE NETLIST_LAYOUT Capture 16.5 Layout netlist contains errors' [; N, R. ]5 W' S6 y
916462 ALLEGRO_EDITOR DATABASE Edit>Split_plane>create hangs Allgro PCB Editor7 o* h) a7 [* A2 G
916469 ALLEGRO_EDITOR REPORTS One Unrouted pin does not show in Unconnected Pins Report9 k9 B; N2 a' T" q2 N0 Q+ ^( Q* S
916495 ALLEGRO_EDITOR INTERACTIV Pick selects components from invisible (Off ) layer
! ]: H+ V% x( l" S916889 CAPTURE NETGROUPS How to change unnamed net group name?
$ Q4 k* l9 M* v' u917002 ALLEGRO_EDITOR OTHER Allegro PDF Publisher creates extra circles not available on film+ V1 e. m( _# g- h; V$ x
917434 APD OTHER Stream out GDSII has more pads in output data., O1 b5 U2 l" a3 G" J2 ~
917739 CONCEPT_HDL INFRA Global Net tied to port is getting split into 2 nets in 16.5, in 16.3 it is treated as a single net" P- \# Q* c: `1 j8 g) j' O& m6 E
918187 CONSTRAINT_MGR OTHER Missing acGetTotalEtchLength predicate.
) e& T/ X9 W* `) F2 @8 s+ P& Z$ @918576 CAPTURE DRC Incorrect DRC is reported for visible power pins which are connected to power symbol1 H: E1 o% V4 c5 {2 ^
8 J6 q5 o8 V; ]% F. P0 ]7 H7 P
DATE: 07-24-2011 HOTFIX VERSION: 002
6 u6 O! y" F5 F1 F |===================================================================================================================================
3 E5 o i9 r2 C N$ |* j9 M: NCCRID PRODUCT PRODUCTLEVEL2 TITLE
, F! ` f0 ]0 `* E===================================================================================================================================5 \- V5 { [* \
527444 ALLEGRO_EDITOR EDIT_ETCH Slide command needs to be enhanced for same net spacings1 t% X$ M1 i5 [3 T
583257 ALLEGRO_EDITOR EDIT_ETCH Add Connect and slide command needs to be enhanced for same net spacings.9 r& ?2 t9 c* o7 S, ~
592956 ALLEGRO_EDITOR EDIT_ETCH Same net traces will not push and/or shove each other.
. Y j& z, C; a$ T6 l$ m745285 ALLEGRO_EDITOR EDIT_ETCH Requesting a true "shove" in Route > Slide for Same net routing.; ?, I' O6 C; S1 s1 v" {
773503 CAPTURE OTHER Doing "Mirror Horizontally" creates extra un-connects or extra junction dots in Capture V16.3.( \# [) y" Q0 h# ?' o2 d/ Q
774270 F2B PACKAGERXL Require to ignore space in Pattern setting to prevent duplicated Refdes.& Y9 s3 o% ?3 U! I
799984 ALLEGRO_EDITOR INTERACTIV Enhance the Fix command to select just cline segs, f& ^' x# G* O7 C( g! O
809008 CAPTURE SCHEMATIC_EDITOR New nodes get appeared within the design when we select the design and do "Mirror Horizontally".
4 G9 p6 T# s; C+ g1 G4 V810058 CAPTURE SCHEMATIC_EDITOR New nodes get appeared within the design when we select the design and do "Mirror Horizontally".
& f7 Q0 x4 H! J821133 ALLEGRO_EDITOR MANUFACT Output artwork for pad data that are suppressed unconnected pads with Gerber 6x00 format
! Z2 j8 ]' h' R1 e831710 CAPTURE SCHEMATIC_EDITOR Capture adds extra junctions to design by itself# m3 V9 f) u2 O4 p6 v
842410 ALLEGRO_EDITOR EDIT_ETCH Ability to slide with "Shove" for "Same Net" segments/vias.
. F! S" R6 x1 K, S% i% R J/ D854971 ALLEGRO_EDITOR INTERACTIV Capability to add cline segment in a temp group
' h6 a6 d3 O' [1 q2 i( q860772 ADW PCBCACHE Save Shopping Cart (pcbcache) is crashing component browser) k9 d/ J& b% y/ |: v
867842 CAPTURE PROJECT_MANAGER Capture crash with 'Open File Location"8 b) d1 P3 L- w' a) a% `; P
868306 CAPTURE CONNECTIVITY mirror vertically removes junction creates extra nets% X5 x* d" s" o' N" I
882677 EMI RULE_CHECK bypass_plane_split fail if BYPASS_XXXX_EFFECT_DISTANCE
5 O7 R3 d+ o* H6 `1 a8 c891439 ALLEGRO_EDITOR INTERACTIV moving cline segments
7 D2 {# A+ a! S' p+ z893544 ALLEGRO_EDITOR INTERFACES IPC-D-356A netlist issue with BB vias.! e( x3 c8 l9 X2 Q, f% f( A" t
893765 ALLEGRO_EDITOR PARTITION Mail command not sending out email on Linux platforms.: ?- e4 E) [" K) c! F3 ?: u( e
894390 SIP_LAYOUT EXPORT_DATA Generate all balls in the xml file for export to EDI's readPackage command/ u# n2 Q# b3 n" Q" k$ b9 m( F/ Q
895933 APD DATABASE Update Symbol shifts the center of the Dynamic Fillet and creating DRCs& [, G0 z3 h! F5 h
896598 ALLEGRO_EDITOR PLACEMENT error message is misleading
* R4 {- G1 {0 a! Y8 R9 D1 p897196 CIS LINK_DATABASE_PA Schematic Contents are not shown in CIS window while link Dbase part for parts placed from library% B+ ?0 U$ r1 l+ t
898598 ALLEGRO_EDITOR MENTOR Negative planes from Mentor Board Station not being translated.
/ N+ o: e8 @( Y( Y/ R' {' n% @- v5 Y- t; h899556 ALLEGRO_EDITOR ARTWORK Import artwork seems not to work correctly.
: N3 o0 q2 A5 ?; s, d900501 ALLEGRO_EDITOR PLACEMENT "Place Replicate Apply" is showing lot of DRC's during placement of replicated circuit in 16.5
3 f4 m& {( {9 F+ p S% r901141 CIS EXPLORER Japanese character appear garbled in CIS explorer window.
+ p% b9 N/ _( L% @9 i0 w6 a0 E901666 CAPTURE OTHER Home page of Flowcad-Switzerland and Flowcal-Poland is not preserved on captre restart on start page
+ x2 v7 H0 o. ]7 O: Y. R902066 ALLEGRO_EDITOR DRC_CONSTR Shape in Region not follow the constrains
5 z) U. A& P$ m! w1 x902349 CAPTURE LIBRARY Capture crashes while closing library
- ~% j+ ? N' u! R! }. @902508 F2B PACKAGERXL SPB16.5 Packager-XL consumes much more memory than 16.3
' @) ?0 U. l8 s902841 CAPTURE GENERAL Capture Start page does not show) F4 J7 P/ I( R# F6 C( O
902876 F2B PACKAGERXL Packager fails on the design upreved in 16.5
/ U7 ?% s6 g8 q902959 CONCEPT_HDL HDLDIRECT HDLDirect Error while saving design2 l: Z# J1 N% r8 T
903171 PSPICE NETLISTER Why Capture is treating hierarchical power ports as floting nets in complex heirarchy designs?7 V2 Y- l& s5 }
903713 ALLEGRO_EDITOR PARTITION Placement Replication do not work fine in the Design Partition
; |- N' \5 E8 ^6 d% `( w+ \903799 SIP_LAYOUT DIE_EDITOR Disappear die pins after exiting co-design die editor
7 u0 k) {+ N6 |/ `4 [904021 ALLEGRO_EDITOR OTHER Export PDF from SPB 16.5 produces a file not text searchable
! @, i- [0 l- h9 t, L904339 CONCEPT_HDL CORE new design crashes using the attached CDS_SITE; Y x* l2 _7 G T2 d8 n
904522 F2B PACKAGERXL Part will not package in 16.5 but packages in 16.3. e" [( u) J+ {0 h( }$ v H% [' |
904764 APD OTHER Enhance Scale Factor of Stream Out to support 4 decimal places
# ?. m1 m& z/ O+ P904771 ALLEGRO_EDITOR MANUFACT Pin Number display issue.
8 h& c& b6 v6 p w5 L904853 ALLEGRO_EDITOR GRAPHICS Enhancement for showing Static shape as it was seen in 16.3
' ^7 {' P% K4 H- Q905144 CONSTRAINT_MGR ECS_APPLY Min Line Spacing is larger than Primary or Neck Gap less(-) Tolerance but No Warning in CM# N2 v- `# ]6 M) X# N7 J5 @+ Q/ g
905314 F2B PACKAGERXL Import physical causes csb corruption
" d9 W$ l( a4 \9 {/ I905337 CONCEPT_HDL CORE ConceptHDL crashes after Import Design process.
/ i/ |" g( X6 C8 z+ R" W1 c* {8 @& W6 }905533 ALLEGRO_EDITOR INTERACTIV Pin numbers for components on BOTTOM Side are moved in Preselect mode,when the BOTTOM layer is invisible. T, V0 K5 S, y7 D" `6 q
905796 CONCEPT_HDL CONSTRAINT_MGR Fujitsu CM issue inaccurate concept2cm diff pair issues* P1 Z- S% u' Y4 D; X
905811 CAPTURE EE_INTERSHEET_RE interesheet references in the form of grid grid page number instead of page number grid
: E& Q9 ~& d- [# A2 _% N2 J906118 CONCEPT_HDL CONSTRAINT_MGR Cannot open CM if SIGNAL_MODEL value was not assigned in ptf.
2 e; H8 g. @9 j( ^! A q+ s; b6 A906153 ALLEGRO_EDITOR SCRIPTS Unable to run allegro script in batch mode on the attached board.
+ G4 [+ a& O6 n906182 APD EXPORT_DATA Modify Board Level Component Output format
" q5 H: K+ _- `7 S q* K906200 ALLEGRO_EDITOR DFA Enh- DFA drc invoked in Batch mode returns false constraint value in Show Element- N: N& i# F0 i3 l- Z
906517 PSPICE PROBE PSpice new cursor window shows incorrect result.6 k- ~4 w, \6 t, |, N
906627 ADW COMPONENT_BROWSE ppt options are not read if ucb is launched from FM. works fine if launched from dehdl.
. @9 s3 r, O Q3 }- w906647 SIG_INTEGRITY LIBRARY lib_dist creates a signoise.log in current directory (with backup files like ,1 ,2 etc.) on each run0 K2 l6 e5 ?- b. I* J+ G8 }4 s
906673 F2B PACKAGERXL Ignore the signal model validity check during packaging% a1 ~. j. |- P3 b
906688 ADW LRM A copy of source design gets created in worklib of target design after 'Import Design'
+ n- Y6 }* I p( r906750 ALLEGRO_EDITOR PARTITION Importing design partition removes the testpoint reference designation* D$ w9 k, w% p& C! V( d6 M' B$ r
906874 PSPICE NETLISTER Error less than 2 connections for unconnected hierarchical pin
& N, Q: B% j, d" ~907095 F2B OTHER Part Manager does not show Error as Undefined when directive ptf_mismatch_exclude_inj_prop is used1 A+ c; t7 f/ S' x
907424 ALLEGRO_EDITOR GRAPHICS Allegro add option for pre 16.5 shape display7 D. |# f1 }' S
907490 CAPTURE NETLIST_LAYOUT 16.5 Layout netlist is not correct. It differs form 16.3 layout netlist.
' R: A: p/ u' r t5 \907884 SIP_LAYOUT MANUFACTURING Need to add an "NC" pin text option for "Manufacturing Documentation Display Pin Text"
- [3 u" K3 \: ~- e% M907885 SIG_INTEGRITY OTHER Matchgroup targets lost when importing netlist to Allegro layout in HF31$ f. e0 S2 V% |" |7 j) r
907929 CAPTURE TCL_SAMPLE TCL command to delete a property from parts in a library is not working correctly
7 I% k9 B. D! E/ z" C( N4 e907933 SIG_INTEGRITY OTHER Single line impedence not working in OrCad PCB Professional$ y9 Y5 T: Z, y# a) I9 |. p
907963 CONCEPT_HDL CORE Design uprev issue when moving from 16.2 to 16.5
2 }$ o- z; D* a/ o908000 SIG_INTEGRITY OTHER Inconsistence z-axis delay reported on Tpoint when define at via location.8 ?" ~3 j6 O5 `% g' c+ Q# E& c/ Z
908057 CONCEPT_HDL CORE DE HDL crash with the cut and paste of a signal name
- R1 k6 e8 y0 R$ D6 E* x) B908060 CONCEPT_HDL CORE CTRL+LMB Option not working correctly in 16.3& y. @2 P" J, s. _! ]; p* s* O! N
908210 CAPTURE CONNECTIVITY Connection is being lost while dragging a component
# J4 ]6 T1 |+ H5 v5 j908241 CAPTURE DRC DRC error column is blank in DRC markers window in 16.57 s6 x. S1 D# D. _$ R% v
908339 RF_PCB BE_IFF_IMPORT mechanical holes VIAFC are not at the right place
( T' h1 d7 F' k2 V6 |2 K908534 SIP_LAYOUT SYMB_EDIT_APPMOD issues with symbol editor and copying pin arrays
; Q' R# x0 L: W, [2 a! X$ w908535 F2B DESIGNVARI When I try to view my variant file the variant editor crashes8 O% v4 H, k$ b! c$ v( ^
908595 APD 3D_VIEWER Cadence Design 3D viewer" screen pops up and is all black because the colors have all converted to b
3 N6 r/ g) I( u2 i4 V9 ]908849 CAPTURE ANNOTATE Getting crash while annotating the attached design* ]4 M( x, G8 _# t
908874 CONCEPT_HDL CORE Part Manager - No Part Found error when using CCR# 775788 feature
- l! G; T/ p) ~- c909077 CONCEPT_HDL CORE After packaging pin numbers remains invisible even when $PN
2 @2 e% E' @0 W' y+ V9 E8 }; W909104 ALLEGRO_EDITOR SYMBOL Warning message needs to be modified. It does not save the symbol and also not tell the actual problem.# Q/ e' A3 ]& q1 }
909417 ALLEGRO_EDITOR REPORTS "report -v upc" returns 'Segmentation fault' on Linux0 l9 l, q( g0 `5 f9 @& {) S7 u
909635 SIP_LAYOUT DIE_STACK_EDITOR Add Interposer crashes in SiP Layout* V5 J: U6 B+ i
909749 ALLEGRO_EDITOR MANUFACT Allegro Crash during dimensioning3 T- B" y- I E! [
909760 SIP_LAYOUT MANUFACTURING Create bond finger solder mask doesn't follow the mask opening as defined in the padstack
h& E# X) q/ m3 c, z- }909861 F2B PACKAGERXL NetAssembler broken within the latest 16.30.031
4 f: d; g; v! B/ A( x1 j910006 CONCEPT_HDL INFRA Motorola design fails to uprev from 16.3 to 16.5, xcon file is getting corrupted.1 y6 X/ k& E# W( |2 q, P" J
910141 CAPTURE NETGROUPS Modify NetGroup definition does not update Offpage Connector9 p7 {5 L! I. ]) R2 R
910340 ADW LRM Import design in schematic, only 1 page import, the entire block is getting imported.6 T1 w6 @" \* h* a8 c) S6 ^
910678 SIG_INTEGRITY OTHER The Analyze> Model Assignment> Auto setup is not creating/assigning models to discrete components in 16.5
2 `$ q4 \ b2 G$ G. j910713 F2B DESIGNVARI Variant Editor crashes when you click web link under Physical Part Filter window.' n4 l8 E* q3 T, h
910936 F2B PACKAGERXL ConceptHDL subdesign net name is inconsistent
$ \' M% W) v6 Z4 w! T1 I1 Z911530 ALLEGRO_EDITOR SYMBOL Package Symbol Wizard does not create symbol with the name given, Z: b4 `" u: O
911631 CONCEPT_HDL CORE DEHDL crashes when opening a design
$ p, m' M, o. W+ @! c912001 ALLEGRO_EDITOR OTHER option_licenses entries are made in allegro.ini even when not set as default
! t. _( @: P/ {. a- m8 Y0 M- W912459 F2B BOM BOMHDL crashes before getting to a menu8 H: U5 \7 W! \, K' T4 F' k+ h
913359 APD MANUFACTURING Package Report shows incorrect data8 P8 ^+ x( W& O6 J
; p+ y: o; s; s6 S- hDATE: 06-24-2011 HOTFIX VERSION: 0014 M+ K: Z+ x) N1 d: F8 L/ L
===================================================================================================================================
! e* X1 [$ }1 T0 q, r: s, dCCRID PRODUCT PRODUCTLEVEL2 TITLE$ R+ G8 t ?( ^* i9 q* l1 X
===================================================================================================================================
+ \7 t& j6 Z- p( I9 G293005 ALLEGRO_EDITOR DATABASE Allegro crash when attempting to move mech. symbol. e' {: y8 M# s( n5 X" e( q9 `
298289 CIS EXPLORER CIS querry gives wrong results
0 i4 Y' ?7 F: l, e- u% q366939 ALLEGRO_EDITOR OTHER Cannot attach refdes on silk subclass with add text
H; U% j1 s b- S; m7 j. b( u432200 ALLEGRO_EDITOR MANUFACT Fillets with an arc are required for Flexi designs1 ~4 d. N3 o( R, y8 N
443447 APD SHAPE Shapes not following the acute angle trim control setting. ^( K4 `0 a9 F, [/ z
473308 PSPICE AA_SENS Passing variables to lower level blocks using subparam1 b' Y8 }( V0 M# l/ b# f" t
517556 PSPICE AA_SENS Advanced Analysis does not support variables being passed down the hierarchy' s7 N" s# |6 ^
548143 ALLEGRO_EDITOR SHAPE Dynamic shpe on Etch TOP will not void properly.. p8 B5 I2 q6 k4 s) y8 U0 G
606959 ADW COMPONENT_BROWSE Key properties with blank values are not getting read in shooping cart) ]! ~' x2 U' L* z P$ N) u
616466 ALLEGRO_EDITOR SHAPE Solid shapes are not getting filled3 e4 B) E/ B5 _2 z; b
641358 SIP_LAYOUT DIE_STACK_EDITOR Request for Via and Multi Layer Pin support for DIE stack Area (blue region)! m: ]% F' K l8 M
644122 SIP_LAYOUT OTHER SiP Layout - xsection - ERROR Adjacent conductive layers are not allowed, but these are diestack layers not conductor" p& A' p5 {( S$ S) ^4 o5 G
645816 ALLEGRO_EDITOR SHAPE Slide a cline all removes gnd shapes on board! q- Q3 p1 h0 G
725355 ALLEGRO_EDITOR SHAPE User can not voided Logo correctly. L: ^' y4 y. Q: w6 |& {
763569 CONCEPT_HDL CORE Display status of Hide/Show unconnected pins icon in DE HDL UI
& v4 `/ F6 ?: c- U; J: g770021 CAPTURE BACKANNOTATE Changing pin group property after pin swap resets pin numbers
7 _. z- P, H* {" O792126 CAPTURE PROPERTY_EDITOR Attempt to change display for occ prop resets
" C; W. v. E5 i! z4 n799014 CONCEPT_HDL CONSTRAINT_MGR concept2cm errors not shown in export physical after hier_write
9 y5 }0 B; P9 m8 U" T- F+ F803147 CIS LINK_DATABASE_PA Link DB part should not change RefDes of multi package part
' m* o$ v3 r' x804240 PSPICE DEHDL Problem in simulation result for a multi-section split part.1 h; @7 I% e& p% Z+ g
809118 CAPTURE NETLISTS ENH to compare two schematic Capture designs
8 ~; v) r4 O7 C' J1 ]: z% L816568 ALLEGRO_EDITOR SHAPE shape disappears when update to smooth.. State no etch4 k1 y1 Y% H5 y R* t
830053 CAPTURE STABILITY DXF export fails if schematic folder name as /6 @+ u# m& q6 w6 w0 c
832108 ALLEGRO_EDITOR SHAPE Shape void incorrectly.4 e7 @. p6 l5 t# c
833542 CONCEPT_HDL CORE PDF publisher font is NOT WYSIWIG with respect to what seen in DE HDL
0 g6 g9 R! W% V: G- G/ Z. s6 N835777 CIS DERIVE_NEW_DB_PA For XLS, donot display table as worksheetName$worksheetName to avoid 8012 error
* y( M* `+ } |' o$ w8 [837640 CIS GEN_BOM date format of CIS BOM has broken macros of 16.2 in 16.3 version
7 R% M" v" Q8 }. n" F844074 APD SPECCTRA_IF Export Router fails with memory errors.0 [6 m; A) Z& s4 o
851595 CONCEPT_HDL CORE Pin numbers overlap on the pin and increase in size
& v; ^8 e7 g9 k+ ^/ r2 V' ^: Z852832 CAPTURE BACKANNOTATE Why is Capture crashing with Mentor back annotation?
1 N9 t! t5 z$ g1 U855015 ALLEGRO_EDITOR OTHER The rats are NOT connecting to the ends of the clines like they should be.
$ t6 L- p5 E! f! `" V! U8 v# V859883 CAPTURE NETLISTS ENH to compare two schematic Capture designs) Y6 p4 o! N0 `* k! C
866009 SIG_INTEGRITY OTHER Net with Pull-up/down should not be used for Diff-pair.4 f4 j/ G: j; M: b7 _5 z* z) g
866830 SCM REPORTS Multiple lines added as separator between title block and report header instead of single line7 E; U7 S m; {' t1 u
866833 SCM REPORTS Extra indentation is left in the left side of the report when the Line Numbers are set to OFF
- \0 X4 l2 ^4 u868618 SCM IMPORTS Block re-import does not update the docsch and sch view; y( A( F: V2 v! e8 u
873402 SIP_LAYOUT LOGIC pin swap for co-design die in SiP
/ @3 G7 f; Z8 q( z- |- y z874010 SIG_INTEGRITY OTHER PCB SI crashes when the Xnet is extracted with VARIANT_TO_IGNORE property.5 w: D5 v5 G. _0 a
874400 ALLEGRO_EDITOR INTERACTIV Flip mode issue with move command
9 V1 }( V1 T& z6 R$ d1 u; i3 H( u874966 ALLEGRO_EDITOR INTERFACES Placed mechanical component do not get Ref Des or part number in IDF file/ ]) L$ R0 t- k: X( l! J& ^
875709 ALLEGRO_EDITOR REPORTS Film area report generated incorrect data at l1
. C5 X9 {& }' {2 h876275 CONCEPT_HDL CONSTRAINT_MGR Constraint Manager not retaining target net6 g, y6 S- R) z1 M* H9 O2 r
879361 SCM UI SCM crashes when opening project
2 o' ], m6 z+ D! ~- q0 d2 c879496 CONCEPT_HDL OTHER Customer wants to have the tabulation� key as separator in HDL BOM.: R9 g1 K/ V! ~2 S
879514 PSPICE AA_MC Monte Carlo to handle equation as comp VALUE.
K/ Z& o% i2 J8 O- Z! q881845 ALLEGRO_EDITOR SHAPE Delete island deletes complete shape# P, v9 R! E9 ^8 N8 ?2 w; F; v# R
882413 PDN_ANALYSIS PCB_PI PDN Analysis should support routed power nets
5 u% ]; U# t/ G F882427 PDN_ANALYSIS PCB_PI PDN Analysis target impedance should have a variable multiplier
- q/ h) a) _7 ` w$ b882567 SIG_INTEGRITY OTHER PCB SI crash if boolean type prop was specified to VARIANT env.
* a" {5 U$ I0 X# Z- }+ I882644 ALLEGRO_EDITOR PLACEMENT PCB Place Replicate Function automatically match Enhancement: U) n1 V- C; ~6 s! m
883164 ALLEGRO_EDITOR INTERACTIV Vias marked fanout moves away from position when moving component: B2 s$ r2 i6 U0 m% g7 N. S/ v
883224 SIG_INTEGRITY SIMULATION crash while reflection simulation from Constraint Manager( t. n6 C& u: L. l+ l
883760 PCB_LIBRARIAN METADATA Incorrectly formatted revision.dat file in the metadata folder
. A1 h _; C/ d- `7 Y; n885391 SIG_INTEGRITY SIMULATION RLGC data sampling algorithm and w-element interpolation.* L! c1 u b. {: k% P& z
885849 ALLEGRO_EDITOR MANUFACT Silkscreen Audit cannot find Solder mask for the text string
0 A6 |0 w1 F0 f! L( N' Q885996 SIG_INTEGRITY OTHER The effect of sn_maxwidthlimit user preference is not seen in cross section impedance calculations
$ Z3 O' U0 `) U' y" t0 O0 N' a886090 ALLEGRO_EDITOR INTERACTIV Add Arc w/Radius does not snap to grid
: _3 `/ n( U5 L, F887180 CAPTURE SCHEMATIC_EDITOR Signals Navigation window doesnt get updated for Buses9 w2 I) ^, r9 y0 i" z* d
887442 APD SHAPE Copper pour of Dynamic shapes on Top layer which contains many existing signal traces fails.& a( L- D8 R# @1 t6 V$ _9 R
887578 SCM AUTO_UI Component Replace pops-up the DSPANE-204 Message# m( W" [0 q$ S' q/ t# h7 t
887926 SIG_INTEGRITY GEOMETRY_EXTRACT Field solution failed if diff trace on bottom doesn't have reference plane.9 c% H, ~ v) p6 r
888414 SIG_EXPLORER OTHER View Trace Parameter display the thickness of dielectric incorrectly.
& g6 j2 l5 p9 E5 t* [888600 CONCEPT_HDL CREFER Cross References not added to Schegen schematic
% s) W x' v! C- R, U5 c888679 SIP_LAYOUT SHAPE Can't create the Dynamic shape on layer M1_sig without unwanted horizontal openings appearing.# ~1 ] Q# s \$ R) v
888804 ALLEGRO_EDITOR OTHER Fillet will become static shape after import from partition board.
! `1 W; l3 Q1 n( x888945 CONCEPT_HDL OTHER unplaced component after placing module
+ q7 C! H' ~9 t2 f% Q889222 ALLEGRO_EDITOR SHAPE Allegro freezes/hangs when adding shape as Polygon with OpenGL ON.7 \# z" u& o2 [( r- m
889365 SIG_INTEGRITY GEOMETRY_EXTRACT top/bottom trace impedances extracted to sigxp are wrong in 16.3) g1 T0 x. _% a+ |
889404 ALLEGRO_EDITOR OTHER Incorrect pad size for Top conductor padstack written to column 59-62.' v( \ }% r6 M/ H; A( D
889426 CONCEPT_HDL CHECKPLUS CheckPlus does not find single node net6 X' b7 J. E! `% e, s7 C
889636 ALLEGRO_EDITOR MANUFACT Incorrect spelling of "Visibility" in "Film Control" tab in the Artwork Control Form9 d! s5 d$ O! ?/ I2 S3 O( I5 G
891235 F2B PACKAGERXL Packager crashes without creating a pxl.log file) z2 a4 b4 Y& w. j4 Z
891292 ALLEGRO_EDITOR SHAPE arc routing causes weird undesireable shape fill performance
! {/ H" R: b. M$ g |891856 ALLEGRO_EDITOR EDIT_ETCH crash when sliding diff pairs# b$ l* a# L. z, b% L$ f/ Q
892375 ALLEGRO_EDITOR PLACEMENT Place Replicate Update disband other groups, irrespective Fixed property added or not.
" X" U- \" ^/ F& z892455 ALLEGRO_EDITOR SYMBOL Why the overlapping pins are not reported with DRC?6 o. e5 t' r& L$ Z) W
892541 SIG_EXPLORER OTHER Export/Import layerstack through the technology file is changing the layer thickness
: B. Y4 Q1 H' `892766 APD WIREBOND Excuting Finger moving cannot push aside finger to move with together by shove all mode" c6 K; J3 K2 }: O( o
892907 ALLEGRO_EDITOR DRC_CONSTR DRC not reported for etch_turn_under_pin violations
9 q3 P0 L2 j' N+ T4 m892963 ALLEGRO_EDITOR SKILL Bad shape boundary created after axlPolyOperation 'OR3 g# f$ E) D% }4 e& C0 Q
892964 SIP_LAYOUT LOGIC Request that Edit Parts List use Dashes "-".
3 x/ [0 p1 C/ G2 h: g: x U% A893295 APD WIREBOND Why move wirebond command does not shove wirebonds? This result in drcs.
' N+ Q) `' ^3 \$ T" H& V893706 CONSTRAINT_MGR OTHER On line DRC hangs on partitioned board
( c; d# T: k! M! m893743 APD EDIT_ETCH Route behavior when spanning pads not as expected.
5 B/ x3 h) ~1 v9 d, V. d0 @7 M893783 SIP_LAYOUT OTHER Padstack Design Editing update File menu with a Update to Design and Close instead of 2 operation( ? s' P, ~, a. o+ r& [
894456 ALLEGRO_EDITOR REPORTS Request Net names be added to Propagation delay lines of the DRC report.
4 e& G+ V4 m, M& [' Q& P" O5 W; u: }894499 SIG_INTEGRITY LIBRARY Tool crashes when moving a cline or selecting the Info icon with OpenGL on.
: A' K1 ~% Y# n894582 APD SHAPE When making a dynamic xhatch Via shapes surrounding are abnormal.0 g# w1 G) n0 s5 I% P: s' M
895542 SIP_LAYOUT WIREBOND SIP design crashing when moving bond finger using blur mode BLUR_BONDFINGER_PRESRV_CON
8 ~5 K2 h5 [3 a$ ~& ~! K895591 ALLEGRO_EDITOR PCAD_IN Importing PCAD file fails to get to the point where we can map layers" T. {$ k+ j3 a# c+ c9 f' {! E
895757 APD ARTWORK Import Gerber command could not be imported Gerber data+ e- C& E# m9 H, q; ?
895964 CONCEPT_HDL CHECKPLUS The CheckPlus command getFileSubstrings is not working correctly; E( N5 v3 Z. l+ i3 t& Q, O
896428 SCM UI Changed Ref Des value not maintained in DEHDL block when part is replaced
% D2 b& I. `& H, l; U- c) B6 r896655 CAPTURE EDIF Import/Export Design of Hierarcy design with OrCAD Capture3 [+ \0 H* N' u! n* H- ~
896846 CAPTURE IMPORT/EXPORT Import edif2cap and capture is crashing! ]% p5 |3 f! ~/ }5 ?6 e. Z. e
897155 ALLEGRO_EDITOR REPORTS Copper coverage in L2 and L7 looks like the same but film area report had large gap.$ T \! S; X& q1 c: K+ C6 |
897654 CAPTURE EE_INTERSHEET_RE Capture crashes on adding intersheet refernces in abbreviated format on attached design.
- A# V9 w! ^4 h& }- k$ I$ f899344 RF_PCB BE_IFF_EXPORT dlibx2iff does not provide the component boundary drawing& X, |+ Q& S- [: ~& ?6 _. Y
899629 CONSTRAINT_MGR OTHER ECset for Total Etch Lenght is not present in OrCAD Prof
9 u/ Q' T& k' x2 g% N' V" T900175 CONCEPT_HDL CONSTRAINT_MGR Few Xnets are lost from Match Group after packaging and importing the netlist to board file.
7 S9 d) O1 R' @* e B900481 CONCEPT_HDL CORE Genview creates a larger symbol without taking the no. of pin in consideration$ @' l/ K0 y$ ?+ j7 s, y: W" B: d
900813 ALLEGRO_EDITOR DRC_CONSTR With rotated pads, pad (pin - via) soldermask spacing DRC is unreasonable.* t' W9 { F. D: T* N( F l# t
900905 PSPICE STABILITY Simsrvr crash and RPC Server unavailable error while running simulation.# n4 p; j1 B& v$ v6 A
901783 CONCEPT_HDL CORE CDS_PART_NAME is annotated on the schematic canvas after running back annotation in 16.5
, G# J8 [/ u0 j" E4 {1 p901909 APD EXPORT_DATA The "package_pin_delay_length.rpt" with Z-axis delay turned on seems wrong
! V( p. Y+ i p8 Z/ V" G u901987 CONCEPT_HDL OTHER SPB16.5 zoom fit does not center the page while ploting the schematic page3 `, L0 p8 W; A4 p. U
902133 CIS OTHER The visible part property value are being shown very distant from part graphics on schematic
N% ~3 ]' J) v. X6 R; K- S902166 SPECCTRA ROUTE Specctra crashes when reading in "bestsave.w" file
: k u4 Y1 y- C+ y; b( v902170 ALLEGRO_EDITOR DATABASE Diffpair Issues with OrCad PCB Designer Professional6 ~- N3 u, Z( J
902177 CONSTRAINT_MGR CONCEPT_HDL Option to view the layer thickness in CM worksheet through worksheet customization
9 c2 C+ `* W$ \) v902463 ALLEGRO_EDITOR INTERACTIV APD crashes when we click ( show element ) on certain components
3 y) i' K( a' `7 g3 y902621 CONCEPT_HDL OTHER Design Differences (vdd) Crashes
, ?9 X& \9 q+ H/ ^- V902909 APD WIREBOND die to die wirebond crash
; f) i- d2 @6 J- N5 z7 ^" W902933 ALLEGRO_EDITOR PADS_IN Pads_in fails while reading PADS ASCII file body p# L/ c2 p" Q" a7 l; V: q1 Q, }
903284 PDN_ANALYSIS PCB_STATICIRDROP IRDrop voltage gradients are plotted outside of the PCB outline; {; \' S- }4 p9 s, A
903680 CONSTRAINT_MGR ECS_APPLY Constraint Manager not passing all hiearchical member objects to a custom measurement.
6 m `+ s: f. ~: ~2 Z6 r904403 ALLEGRO_EDITOR DATABASE Allegro crashes when refreshing module
0 ]( V0 ]. j- U* ^% T$ I8 s) }1 \4 Z" i
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发表于 2013-6-10 09:11
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支持！
反对！
楼主
這是原廠下載的~~自從115不提供之後~~就不知道能上傳到哪了??
