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http://pan.baidu.com/share/link?shareid=437717&uk=38260382947 u5 }! n* B$ |2 d+ t
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DATE: 05-24-2013 HOTFIX VERSION: 0102 _% Y1 B6 i5 Z9 O. ~
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0 a8 U9 I+ T' P5 ZCCRID PRODUCT PRODUCTLEVEL2 TITLE
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1084716 allegro_EDITOR OTHER Getting an MPS error when updating CM from SigXplorer
6 u3 I& p! V! p( ]9 B1111430 FSP CAPTURE_SCHEMATI Auto-resize the schematic sheet so that hierarchical block fits within border
j0 c+ C: R2 [1119007 concept_HDL CORE PDF Publish of schematic creates extremely large PDF files+ Q$ l) x! ?$ \+ c
1121020 FSP MODEL_EDITOR Cut-Paste from Excel causes empty cell in Rule Editor
( ~* g# P9 p+ U4 D" L* W; G1124610 Pspice SIMULATOR Attached design gives "INTERNAL ERROR -- OveRFlow" in SPB116.6
, i1 U2 c& k6 \* d( U: S1125330 FSP CAPTURE_SCHEMATI FSP generates orcad schematics with components (Resistors) outside page border" l5 {2 i' J( |1 T. j3 z" s
1131775 ADW LRM LRM error with local libs & TDA5 O H- A+ p- v
1131868 CONCEPT_HDL CONSTRAINT_MGR Many net-class constraints "fell off" the design after uprev and Import Design of GEP40 a8 z' M0 Y, t8 `/ r) M. {
1132080 ALLEGRO_EDITOR PLOTTING Size of the logo changes after File > Import > Logo& b+ x8 D$ x1 A! f: @, p) e
1134956 SPECCTRA HIGHSPEED Route Automatic fails with error when Impedance rules are turned ON in Allegro CM.% l: W3 n4 K: s8 P6 {* g
1135548 SIP_LAYOUT SHAPE This design shows two areas with shape shorting errors that should not occur2 I& Q# d9 L I# l0 O& B
1138312 ALLEGRO_EDITOR MANUFACT NCROUTE is not generated for filled rectangle slot ?) {/ y' `2 W c+ d$ d; f/ Y5 x
1139433 ALLEGRO_EDITOR GRAPHICS embedded netnames not displayed or getting very small upon panning after exiting 3D Viewer.
) F" q/ X P: A' I1139509 CONCEPT_HDL CORE The LRM update changes npn device to resistor
1 J. p# v0 q4 R" v4 v5 E- y0 r+ b1140752 ALLEGRO_EDITOR PLACEMENT Moving a place replicate module crashes allegro% Y5 h; U! F' m7 D6 P
1141314 SIP_LAYOUT SYMB_EDIT_APPMOD Design will lock up after changing the border using Edit Boundary in Symbol edior mode.* U4 m( h3 g: y: J0 W3 _1 _1 A& s) _
1141751 ALLEGRO_EDITOR INTERFACES Allegro Crashes with Export IPC2581.
6 D) n/ m/ }0 s, w1142478 CONSTRAINT_MGR INTERFACE_MAPPER adding constraint to netgroup causes CM & PCB SI to crash
! T% Y3 c8 E9 n% |3 @" ~% ?4 J5 ]1142884 ALLEGRO_EDITOR OTHER Boolean type user defined property doesn't export to the PDF5 t+ s8 g% K8 K, f: U/ k6 Z
1143199 SIP_LAYOUT DIE_EDITOR Enable bump remastering
3 }/ q3 ^* z# g7 D! Q7 b4 F1143654 SIP_LAYOUT DIE_EDITOR Add X&Y offset when adding or moving a pin in die editor
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发表于 2013-5-25 09:24
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支持！
反对！
发表于 2013-5-25 10:29
