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DATE: 05-24-2013 HOTFIX VERSION: 010( Q, g- M- D9 r, Z5 I2 O" B) M
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CCRID PRODUCT PRODUCTLEVEL2 TITLE
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1084716 allegro_EDITOR OTHER Getting an MPS error when updating CM from SigXplorer
- d/ Y( V0 B. z1111430 FSP CAPTURE_SCHEMATI Auto-resize the schematic sheet so that hierarchical block fits within border) }( y4 c* @ s' e
1119007 concept_HDL CORE PDF Publish of schematic creates extremely large PDF files" j2 H- c5 C) @; x
1121020 FSP MODEL_EDITOR Cut-Paste from Excel causes empty cell in Rule Editor) |. B( M3 S) s$ p7 E. ~+ x
1124610 Pspice SIMULATOR Attached design gives "INTERNAL ERROR -- OveRFlow" in SPB116.6
6 Z8 ?; w1 g, G: M1125330 FSP CAPTURE_SCHEMATI FSP generates orcad schematics with components (Resistors) outside page border% k3 n2 s9 w& X) v; S2 T4 _
1131775 ADW LRM LRM error with local libs & TDA
' P3 g2 j3 G) `7 `1131868 CONCEPT_HDL CONSTRAINT_MGR Many net-class constraints "fell off" the design after uprev and Import Design of GEP4) B1 e9 m& H6 t" L0 w* Y
1132080 ALLEGRO_EDITOR PLOTTING Size of the logo changes after File > Import > Logo
. C! j7 n3 y$ R7 I( |; j$ }1134956 SPECCTRA HIGHSPEED Route Automatic fails with error when Impedance rules are turned ON in Allegro CM.
+ f+ X; h4 D- ]( p' r2 ^, o/ m! ~5 _1135548 SIP_LAYOUT SHAPE This design shows two areas with shape shorting errors that should not occur! D, g) @! s8 k/ o/ a% H
1138312 ALLEGRO_EDITOR MANUFACT NCROUTE is not generated for filled rectangle slot ?
- K- U p% T$ ]2 S3 x; G1139433 ALLEGRO_EDITOR GRAPHICS embedded netnames not displayed or getting very small upon panning after exiting 3D Viewer.+ ^! y9 \1 z6 a( @9 C
1139509 CONCEPT_HDL CORE The LRM update changes npn device to resistor' `7 ]0 G$ E% j% n& K
1140752 ALLEGRO_EDITOR PLACEMENT Moving a place replicate module crashes allegro& M, v( ?4 {4 | z# |
1141314 SIP_LAYOUT SYMB_EDIT_APPMOD Design will lock up after changing the border using Edit Boundary in Symbol edior mode.
& e0 i* J" e% R1141751 ALLEGRO_EDITOR INTERFACES Allegro Crashes with Export IPC2581.
- G9 N9 K( v; _/ i" P7 C9 X6 o& h# \1142478 CONSTRAINT_MGR INTERFACE_MAPPER adding constraint to netgroup causes CM & PCB SI to crash. g# P& R2 T! l0 c/ F6 G) N, x
1142884 ALLEGRO_EDITOR OTHER Boolean type user defined property doesn't export to the PDF2 T# N* c0 c( O
1143199 SIP_LAYOUT DIE_EDITOR Enable bump remastering. E* [+ B( } b9 A
1143654 SIP_LAYOUT DIE_EDITOR Add X&Y offset when adding or moving a pin in die editor3 A0 F+ p7 I2 n$ I L
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发表于 2013-5-25 09:24
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支持！
反对！
发表于 2013-5-25 10:29
