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http://pan.baidu.com/share/link?shareid=437717&uk=38260382946 f2 v+ p, V. g& _" @
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{:soso_e102:}
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DATE: 05-24-2013 HOTFIX VERSION: 0106 B* h4 u1 W" G7 O
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CCRID PRODUCT PRODUCTLEVEL2 TITLE6 P" `: M- H2 h( |
===================================================================================================================================
- p8 i1 A! ^1 i$ \- m1084716 allegro_EDITOR OTHER Getting an MPS error when updating CM from SigXplorer1 N+ g1 h, V7 v
1111430 FSP CAPTURE_SCHEMATI Auto-resize the schematic sheet so that hierarchical block fits within border! J( o9 [3 G1 Q& R
1119007 concept_HDL CORE PDF Publish of schematic creates extremely large PDF files
# r* b1 ~$ @3 n! M. Z; \1121020 FSP MODEL_EDITOR Cut-Paste from Excel causes empty cell in Rule Editor7 ~" x0 d3 p- ^$ n3 l4 X% B
1124610 Pspice SIMULATOR Attached design gives "INTERNAL ERROR -- OveRFlow" in SPB116.6* }% P( j0 w- f' ^: U4 q# B+ C
1125330 FSP CAPTURE_SCHEMATI FSP generates orcad schematics with components (Resistors) outside page border- m2 [. { h5 l, |
1131775 ADW LRM LRM error with local libs & TDA! ?/ X4 d: W+ R! p8 q4 Q% L
1131868 CONCEPT_HDL CONSTRAINT_MGR Many net-class constraints "fell off" the design after uprev and Import Design of GEP4
$ Z: d- P4 e# a7 b$ N1132080 ALLEGRO_EDITOR PLOTTING Size of the logo changes after File > Import > Logo
6 J. M6 Y( L( Y: H" s6 a+ t1134956 SPECCTRA HIGHSPEED Route Automatic fails with error when Impedance rules are turned ON in Allegro CM.
2 r6 ^5 Z B4 g. d7 F( B3 |0 k! R% r1135548 SIP_LAYOUT SHAPE This design shows two areas with shape shorting errors that should not occur9 M& V9 g+ B8 U# f8 j c
1138312 ALLEGRO_EDITOR MANUFACT NCROUTE is not generated for filled rectangle slot ?2 x+ \" J" Q+ \1 Q/ Q, ]
1139433 ALLEGRO_EDITOR GRAPHICS embedded netnames not displayed or getting very small upon panning after exiting 3D Viewer.
. B( q `# v8 X( H4 E: _1139509 CONCEPT_HDL CORE The LRM update changes npn device to resistor
7 {1 ?% k( _4 e. N& z+ f1140752 ALLEGRO_EDITOR PLACEMENT Moving a place replicate module crashes allegro* Q% {& z6 c' w
1141314 SIP_LAYOUT SYMB_EDIT_APPMOD Design will lock up after changing the border using Edit Boundary in Symbol edior mode.5 n! `- M/ D% {* I- Y0 _9 j
1141751 ALLEGRO_EDITOR INTERFACES Allegro Crashes with Export IPC2581.
3 A: W' C4 f8 p" f8 y* G5 R1142478 CONSTRAINT_MGR INTERFACE_MAPPER adding constraint to netgroup causes CM & PCB SI to crash
* X: E* g* h9 r( F+ ?/ k+ {1142884 ALLEGRO_EDITOR OTHER Boolean type user defined property doesn't export to the PDF
% @5 U" B2 C( f5 h3 y% P' g9 ]( J' m1143199 SIP_LAYOUT DIE_EDITOR Enable bump remastering+ q) {3 H8 _+ g+ u( h2 a# H# x" [
1143654 SIP_LAYOUT DIE_EDITOR Add X&Y offset when adding or moving a pin in die editor% y+ ]- z1 X* w7 a% ?
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发表于 2013-5-25 09:24
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支持！
反对！
发表于 2013-5-25 10:29
