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http://pan.baidu.com/share/link?shareid=437717&uk=3826038294
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DATE: 05-24-2013 HOTFIX VERSION: 010' o/ i( |* b7 ~; X/ V# x- E
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CCRID PRODUCT PRODUCTLEVEL2 TITLE) E# ]$ |0 ^4 ^7 G" s
===================================================================================================================================
3 X8 q; l s6 { j1084716 allegro_EDITOR OTHER Getting an MPS error when updating CM from SigXplorer; P* E0 Q2 g- B
1111430 FSP CAPTURE_SCHEMATI Auto-resize the schematic sheet so that hierarchical block fits within border
8 _! {; p$ X# I9 ~1119007 concept_HDL CORE PDF Publish of schematic creates extremely large PDF files
7 ?; |- n. m( P G$ M' f$ ~1121020 FSP MODEL_EDITOR Cut-Paste from Excel causes empty cell in Rule Editor
) v. ^) s0 v' V! k. R$ X3 I' i6 k1124610 Pspice SIMULATOR Attached design gives "INTERNAL ERROR -- OveRFlow" in SPB116.6
! h+ H" t, P3 B5 O( k1125330 FSP CAPTURE_SCHEMATI FSP generates orcad schematics with components (Resistors) outside page border
; u! g% x% v# K( {1131775 ADW LRM LRM error with local libs & TDA0 ^2 A1 `: j5 f
1131868 CONCEPT_HDL CONSTRAINT_MGR Many net-class constraints "fell off" the design after uprev and Import Design of GEP4& X1 u% j2 N1 P. C, P7 q
1132080 ALLEGRO_EDITOR PLOTTING Size of the logo changes after File > Import > Logo- }/ o W3 d5 K7 _1 k# l( l! L
1134956 SPECCTRA HIGHSPEED Route Automatic fails with error when Impedance rules are turned ON in Allegro CM.( F: ?2 I) ~* [( M' P1 y+ S7 S8 s. o
1135548 SIP_LAYOUT SHAPE This design shows two areas with shape shorting errors that should not occur3 Q. H6 H! B: O8 _
1138312 ALLEGRO_EDITOR MANUFACT NCROUTE is not generated for filled rectangle slot ? P# Z. T! X2 p$ B0 `$ X
1139433 ALLEGRO_EDITOR GRAPHICS embedded netnames not displayed or getting very small upon panning after exiting 3D Viewer.
6 u% B( F4 l H( c1139509 CONCEPT_HDL CORE The LRM update changes npn device to resistor
" O/ n/ H! L5 w& n1 a1140752 ALLEGRO_EDITOR PLACEMENT Moving a place replicate module crashes allegro
h+ v+ [$ N5 P8 M4 i1141314 SIP_LAYOUT SYMB_EDIT_APPMOD Design will lock up after changing the border using Edit Boundary in Symbol edior mode.
! {9 ^4 |( q. C% D1 K1141751 ALLEGRO_EDITOR INTERFACES Allegro Crashes with Export IPC2581.
$ J& ?0 o9 l" ?. ^9 B. d1142478 CONSTRAINT_MGR INTERFACE_MAPPER adding constraint to netgroup causes CM & PCB SI to crash2 ]. c q, N, v/ T; m
1142884 ALLEGRO_EDITOR OTHER Boolean type user defined property doesn't export to the PDF2 o5 t# M# j$ M: ~
1143199 SIP_LAYOUT DIE_EDITOR Enable bump remastering
1 p9 `, R# g' W1143654 SIP_LAYOUT DIE_EDITOR Add X&Y offset when adding or moving a pin in die editor) d7 J' P# g) s) k
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发表于 2013-5-25 09:24
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反对！
发表于 2013-5-25 10:29
