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http://pan.baidu.com/share/link?shareid=437717&uk=38260382947 u/ i; z& D3 y0 }) j9 k+ T" B
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DATE: 05-24-2013 HOTFIX VERSION: 0109 S8 }+ y! y# w$ [9 p3 W9 k
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CCRID PRODUCT PRODUCTLEVEL2 TITLE( y8 X. S6 F) F! A5 }
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[* e/ g: o) Y/ f; t+ T# m1084716 allegro_EDITOR OTHER Getting an MPS error when updating CM from SigXplorer
; w* g0 H: X# V7 p2 A1111430 FSP CAPTURE_SCHEMATI Auto-resize the schematic sheet so that hierarchical block fits within border7 \; q# I& s, ^$ G/ e7 M
1119007 concept_HDL CORE PDF Publish of schematic creates extremely large PDF files; ~6 K" @9 ?( q9 c K- G0 U0 d
1121020 FSP MODEL_EDITOR Cut-Paste from Excel causes empty cell in Rule Editor$ i3 b7 H$ g$ W7 F0 a
1124610 Pspice SIMULATOR Attached design gives "INTERNAL ERROR -- OveRFlow" in SPB116.6& Y5 _3 l9 V! H A& ?2 s
1125330 FSP CAPTURE_SCHEMATI FSP generates orcad schematics with components (Resistors) outside page border
/ N7 [, u4 t2 o6 r1131775 ADW LRM LRM error with local libs & TDA6 E7 s8 [/ }8 j/ T4 p. l
1131868 CONCEPT_HDL CONSTRAINT_MGR Many net-class constraints "fell off" the design after uprev and Import Design of GEP4( m7 d& p* \- D" f+ k
1132080 ALLEGRO_EDITOR PLOTTING Size of the logo changes after File > Import > Logo
6 i6 }; s+ U- X5 k1134956 SPECCTRA HIGHSPEED Route Automatic fails with error when Impedance rules are turned ON in Allegro CM.
5 r4 k& w" g/ t% U1135548 SIP_LAYOUT SHAPE This design shows two areas with shape shorting errors that should not occur
C+ `0 K: }, m* }7 F3 c; t2 G1138312 ALLEGRO_EDITOR MANUFACT NCROUTE is not generated for filled rectangle slot ?
O! f/ J2 \7 U) H+ v- N" i1139433 ALLEGRO_EDITOR GRAPHICS embedded netnames not displayed or getting very small upon panning after exiting 3D Viewer.
2 h% M" E1 @/ d7 ^ `1139509 CONCEPT_HDL CORE The LRM update changes npn device to resistor8 E- l2 ?, I7 q. g( ]5 D9 \
1140752 ALLEGRO_EDITOR PLACEMENT Moving a place replicate module crashes allegro
, p) b: }# G/ @7 b1141314 SIP_LAYOUT SYMB_EDIT_APPMOD Design will lock up after changing the border using Edit Boundary in Symbol edior mode.1 ^+ t4 X6 \% r8 m6 G4 g/ G
1141751 ALLEGRO_EDITOR INTERFACES Allegro Crashes with Export IPC2581.$ e- b* `0 S1 l
1142478 CONSTRAINT_MGR INTERFACE_MAPPER adding constraint to netgroup causes CM & PCB SI to crash
# R/ V7 ]9 ^! U' t0 X0 z# }: X1142884 ALLEGRO_EDITOR OTHER Boolean type user defined property doesn't export to the PDF7 @% D' w% z% t' ~
1143199 SIP_LAYOUT DIE_EDITOR Enable bump remastering
# ~# W5 P c5 b* _ q1143654 SIP_LAYOUT DIE_EDITOR Add X&Y offset when adding or moving a pin in die editor; }5 ?* B$ p& v- j l
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发表于 2013-5-25 09:24
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反对！
发表于 2013-5-25 10:29
