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http://pan.baidu.com/share/link?shareid=437717&uk=3826038294
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{:soso_e102:}
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DATE: 05-24-2013 HOTFIX VERSION: 010
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CCRID PRODUCT PRODUCTLEVEL2 TITLE4 D5 q( a; ~3 q* `$ K$ e6 @
===================================================================================================================================4 h8 ?) p8 h: Z+ h7 X% Z
1084716 allegro_EDITOR OTHER Getting an MPS error when updating CM from SigXplorer3 A" f8 t0 Z5 `
1111430 FSP CAPTURE_SCHEMATI Auto-resize the schematic sheet so that hierarchical block fits within border8 |0 q5 n! \6 h1 A1 i
1119007 concept_HDL CORE PDF Publish of schematic creates extremely large PDF files
8 B6 y4 E3 A* g1 E( b* |1121020 FSP MODEL_EDITOR Cut-Paste from Excel causes empty cell in Rule Editor
% R& T0 ?$ V/ L% P7 C1124610 Pspice SIMULATOR Attached design gives "INTERNAL ERROR -- OveRFlow" in SPB116.6
& P) j- s9 t8 }5 G1125330 FSP CAPTURE_SCHEMATI FSP generates orcad schematics with components (Resistors) outside page border% a0 x3 a9 D' F: {1 j9 l2 x. X' h+ E% b
1131775 ADW LRM LRM error with local libs & TDA
4 b1 Q" I3 L: L3 r" B; L* M1131868 CONCEPT_HDL CONSTRAINT_MGR Many net-class constraints "fell off" the design after uprev and Import Design of GEP4
- f e. Z2 F# @# _* p" x. H, U1132080 ALLEGRO_EDITOR PLOTTING Size of the logo changes after File > Import > Logo
1 q2 N9 `* Q9 e8 k# D1134956 SPECCTRA HIGHSPEED Route Automatic fails with error when Impedance rules are turned ON in Allegro CM.+ R' i/ a; w; x/ ?4 u: o
1135548 SIP_LAYOUT SHAPE This design shows two areas with shape shorting errors that should not occur
. C/ W4 C, J/ l t7 x; r1138312 ALLEGRO_EDITOR MANUFACT NCROUTE is not generated for filled rectangle slot ?9 y- V: o7 w0 ^7 ^7 X% G
1139433 ALLEGRO_EDITOR GRAPHICS embedded netnames not displayed or getting very small upon panning after exiting 3D Viewer.# Q5 p y7 @2 U2 f0 Z+ O# R3 B: m" n
1139509 CONCEPT_HDL CORE The LRM update changes npn device to resistor8 j! w+ D' B$ r q4 E- _# f
1140752 ALLEGRO_EDITOR PLACEMENT Moving a place replicate module crashes allegro
8 k$ l$ i9 t& P9 f8 C: W: H1141314 SIP_LAYOUT SYMB_EDIT_APPMOD Design will lock up after changing the border using Edit Boundary in Symbol edior mode.! b w P( @3 K H4 Q
1141751 ALLEGRO_EDITOR INTERFACES Allegro Crashes with Export IPC2581.& a( H; {0 ~* @) N3 i
1142478 CONSTRAINT_MGR INTERFACE_MAPPER adding constraint to netgroup causes CM & PCB SI to crash* M! l% w4 i) D6 m9 ?$ a( K
1142884 ALLEGRO_EDITOR OTHER Boolean type user defined property doesn't export to the PDF
7 W& Y+ o, Y" \5 o9 p4 s1 A1143199 SIP_LAYOUT DIE_EDITOR Enable bump remastering; X* e+ u6 l+ g6 T C
1143654 SIP_LAYOUT DIE_EDITOR Add X&Y offset when adding or moving a pin in die editor
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发表于 2013-5-25 09:24
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支持！
反对！
发表于 2013-5-25 10:29
