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本帖最后由 stupid 于 2013-4-30 23:17 编辑
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* w4 i* k/ ~4 \7 K7 I4 D2 W0 e某一天，一个叫马克的人发起了帖子，采用了滚动刷屏的方法，4个帖子，一个内容：招人
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首帖Date: Mon, 7 Jan 2013 17:36:56 +00003 w l' K2 w9 v7 o% a. F8 s& a
2贴 Date: Fri, 15 Feb 2013 00:22:29 +0000" a& B3 H# a+ l# s) a/ P0 G1 n6 n ^
3贴 Date: Thu, 14 Mar 2013 04:49:58 +0000
2 x* Q9 a0 T8 k" K2 D, U9 U4贴Date: Thu, 25 Apr 2013 18:37:34 +0000" M8 c7 Z2 v- x" I6 w
2 p: q* ]/ q9 uMy Team is looking for a Senior Staff Engineer(Backplane Architect)/Principle ( ^9 a% }7 S1 P) c G% |
Engineer;
. Q8 U$ e( @& @& `$ OResponsibilities/Description;
# Y! d/ H0 d: A" QResponsible for providing the backplane architecture and 10G+ High Speed SI
1 F2 S/ m" X2 K5 jsolutions for Next Generation telecommunications equipment in the router,
- x5 }, ^% d" e6 t! cswitch and transmission product lines to meet system design requirements.
" b7 w( v3 [/ d7 B6 U3 sExperience in co-designing of ASIC, Package, PCB and System interconnects+ c8 L4 t. A+ ^% H$ p' |. K H
desired. including:- |6 l% t# j2 _9 M6 [
0 A2 u! Q* ]: n/ G! X0 p- Design and analysis of multi-gigabit serial links for Backplane and5 Y9 y2 K6 Z4 ?0 V2 ^$ B% ~
chip-to-chip interfaces meeting CEI, XFI, XLAUI, SFI, 10Gbase-KR, PCIe, and- B! \' x. c/ q& b
other standards.
7 Y' h2 L1 Z) [ {* U1 }6 N% }7 Z7 B- Familiar with ASIC, Hardware, interconnect teams to evaluate design+ N y4 B7 D, |$ d
tradeoffs and optimize design performance / risk / cost /manufacturability.4 J# G( @8 M6 I* w
- To evaluate package designs, characterization of SerDes, and design% {2 r3 Z! s0 ^2 `/ k/ a, H
experiments to do the same.
" L* a3 f( }- `' S6 H1 q4 [' W- Modeling of electromagnetic 3-D structures.2 U6 P8 z3 p, |7 \- r; |. L5 P) y
- Modeling and analyzing power delivery networks (PDN).
7 b0 z! b3 ^* a4 f% T( _3 h# B/ q2 a- Familiar with memory technologies such as DDR2/DDR3 is preferred.
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/ b3 i2 v1 o& u: X$ xQualifications/Requirements:
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% {# y4 H/ ^6 c6 V% f \: }0 \0 q- Performing physical measurements to collect data for design
% O' \( s1 c1 {* b validation and simulation correlations./ w! {0 V0 ^8 d+ o+ a
- Knowledgeable in using most major SI/PI tools: HFSS, CST, HSPICE,2 } k3 L+ Z. L `, z
Sigrity Tools, StatEye, ADS, Matlab, Cadence Allegro and APD, HSPICE, and
3 r) `( W8 V: p7 T& c5 Y other tools.
+ v Q2 G- T+ ]/ P7 }( p: y5 W) P- Experience in correlating simulation results with lab measurements
p1 D/ \+ F4 E9 y6 u using oscilloscopes, TDRs, VNAs, BertScope is a plus. Must be self
6 x# _3 ]8 B' W+ Y5 O2 H6 o0 u motivated with strong communication and teamwork skills.( Z1 r+ i# @. B: i/ H
- The working experience in Core router or Edge router similar product
1 {0 R3 Q# D! j# A/ H" O8 t in large telecomm infrastructure company.& C/ l M6 J0 E" K5 B1 o2 P" g
A MSEE, or a PhD is preferred, with 10years of experience.
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5 S2 n/ k9 \: Y" E/ tSome portion of time will be spent in Shenzhen working with the HQ SI team.
! D5 H" F# y) ?% VTravel will be about 30-60% to China.% O3 u# Q. \; ~/ A. l
4 o" O6 {/ `, }5 ~1 i3 `Please contact mark.apton@xxxxxxxxxx
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插个广告，有符合以上条件，又愿意在深圳工作的人速速联系我 dbm@chinafastprint.com |
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发表于 2013-4-26 22:19
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发表于 2013-4-30 23:10