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本帖最后由 hzqydq 于 2013-4-9 15:11 编辑
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+ a5 R6 v) Q" w2 ~) c7 ? dHotfix_SPB16.50.041_wint_1of1.exe6 ?/ g8 y# W& H5 M. w; `- G8 E
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; M9 F0 G7 p0 ~) W0 J8 [下载地址
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http://dl.vmall.com/c0kgf7xkaj6 }2 t7 |4 s9 F5 [3 F, m/ N, B6 V, N
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Hotfix中只需要安装最新的版本即可。& k; M% Z y* N, r
DATE: 04-4-2013 HOTFIX VERSION: 041
3 |; ~' z0 k$ w! x2 T% a6 ~===================================================================================================================================
& N1 {$ x& r+ J2 \CCRID PRODUCT PRODUCTLEVEL2 TITLE
& e7 I& x! G+ H' [===================================================================================================================================
4 l1 r! Z2 z& R& n: w8 L835944 allegro_EDITOR OTHER Customer want to change for Jumper symbol by other Alt symbol.7 m6 ~7 ~- f# S6 v3 j" |
988019 ALLEGRO_EDITOR PLACEMENT Allegro hangs when doing place replicate create
1 z+ B; K+ L# t' \/ [7 w/ p( E1065641 PCB_LIBRARIAN CORE PDV symbol editor is crashing when deleting a group using delete or CTRL+X
y3 r# m7 K8 k, V3 p5 I1073152 concept_HDL OTHER Printing Published PDF schematic has missing lines2 z, h: Z e$ r% W
1082587 FSP FPGA_SUPPORT Support of Xilinx's Zync device; x9 C- O( J7 u- }0 S
1100945 SCM SCHGEN SCM generated DE-HDL has $PN placement issue/ Q. E7 a0 ~( c+ `; p; i
1107172 CONCEPT_HDL OTHER Project Manager Packager does not report errors on missing symbol- w; c1 p" e: d5 ?" I* A; n; n
1107397 SIP_LAYOUT PLACEMENT Place Manual-H rotates die* P: f: s+ q, n; d3 ?3 o x1 A* Z
1108603 PCB_LIBRARIAN VERIFICATION PDV Tools Verification > View Verification (CheckPlus) leaves <project>.cpm_tmp.cpm6 h2 W Y. ^! l! T. B. y7 ^ v. N
1109466 ALLEGRO_EDITOR ARTWORK Artwork create some strange gerber lines for fillet.
% K+ z% O" u- d: A) a1109926 CONCEPT_HDL CORE viewing a design disables console window1 S" [& F+ b) a a0 F, s0 F) `1 j9 `
1110077 ALLEGRO_EDITOR DRC_CONSTR Duplicate Drill Hole DRC's are not shown for Pins overlapped in same symbol unless "Min metal to metal" DRC is turned ON% w+ m; g! [' Y ~" Y5 E# N# i+ U( X9 l
1110264 RF_PCB FE_IFF_IMPORT IFF Import in DEHDL has component offset
1 t0 c8 u: X! [2 H8 l) [& p1112295 APD DXF_IF padstacks offset Y cannot be caught by DXF.
' I9 y: j2 l% \+ u6 E1112395 CONCEPT_HDL CORE BASE\G for global signal is not obeyed after upreving the design to 1650.& c/ u6 Z/ w9 u" D( O% b
1112774 GRE CORE Allegro GRE not able to commit plan after topological plan
+ a% _1 u9 f/ K7 `$ o8 f1113317 CONCEPT_HDL skill skill code to traverse design not working properly
( T1 S# p+ V: @0 K; ~) L1114630 CONCEPT_HDL ARCHIVER Archcore fails because the project directory on Linux has a space in the name
- ?- p4 ~) W b; }9 J1114689 CONCEPT_HDL CORE Unknown project directive : text_editor1 {) t* k; ^7 R. d; h3 R
1114928 F2B PACKAGERXL error (SPCODD - 5) while Export Physical even after change pin from A<0> to A
. ~ g% x/ F( b1 { T1 ~8 E1115625 ALLEGRO_EDITOR SKILL Design extents corrupted when axlTrigger is used.
c) R {+ j' T1115708 ALLEGRO_EDITOR INTERFACES Export DXF is outputting corrupt data on one layer. |
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发表于 2013-4-9 15:08
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