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本帖最后由 hzqydq 于 2013-4-9 15:11 编辑
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Hotfix_SPB16.50.041_wint_1of1.exe
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7 l1 C& i k3 c# @; j" _' S3 N5 A下载地址3 f- N- w; x" t. Z1 X, K9 J
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http://dl.vmall.com/c0kgf7xkaj% r+ F8 p j. O6 k% M! w
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+ h' X- ^ @6 W1 L1 a/ g) C; H% tHotfix中只需要安装最新的版本即可。- e# `6 I4 p. w; j K
DATE: 04-4-2013 HOTFIX VERSION: 041! m, `" A+ ~9 C5 f
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CCRID PRODUCT PRODUCTLEVEL2 TITLE! p: M4 f; ~* @. g) s% X
===================================================================================================================================8 M* v. _' J0 N
835944 allegro_EDITOR OTHER Customer want to change for Jumper symbol by other Alt symbol.; h( J8 Q8 p0 g& O* A
988019 ALLEGRO_EDITOR PLACEMENT Allegro hangs when doing place replicate create- `/ [, l* T5 b1 \
1065641 PCB_LIBRARIAN CORE PDV symbol editor is crashing when deleting a group using delete or CTRL+X/ ~2 T5 m1 E1 A5 D& t
1073152 concept_HDL OTHER Printing Published PDF schematic has missing lines
% [/ o, @9 C/ N4 y, c* `& E1 J4 F1082587 FSP FPGA_SUPPORT Support of Xilinx's Zync device. Z8 a- g" ?& |* k; R, [
1100945 SCM SCHGEN SCM generated DE-HDL has $PN placement issue; F. [: ]) r7 d6 H* h1 L% c
1107172 CONCEPT_HDL OTHER Project Manager Packager does not report errors on missing symbol4 R5 r" |/ Y5 n c$ E7 K, m! s0 k
1107397 SIP_LAYOUT PLACEMENT Place Manual-H rotates die
2 e; j: @7 u0 B: T4 \1108603 PCB_LIBRARIAN VERIFICATION PDV Tools Verification > View Verification (CheckPlus) leaves <project>.cpm_tmp.cpm
+ u! z3 W0 T: f% d. e7 b1109466 ALLEGRO_EDITOR ARTWORK Artwork create some strange gerber lines for fillet., L) B i# ]1 X5 D# ]! N9 a
1109926 CONCEPT_HDL CORE viewing a design disables console window1 B2 }% w/ ~+ q B2 B! a2 e
1110077 ALLEGRO_EDITOR DRC_CONSTR Duplicate Drill Hole DRC's are not shown for Pins overlapped in same symbol unless "Min metal to metal" DRC is turned ON
) H+ ?1 V% q( K0 O" F& s1110264 RF_PCB FE_IFF_IMPORT IFF Import in DEHDL has component offset8 |5 O$ M* @, \- z
1112295 APD DXF_IF padstacks offset Y cannot be caught by DXF.
9 v0 n' J. |" x1112395 CONCEPT_HDL CORE BASE\G for global signal is not obeyed after upreving the design to 1650.! G0 m4 ? p. L5 J6 n: l
1112774 GRE CORE Allegro GRE not able to commit plan after topological plan' M6 T0 y; J! ?+ |
1113317 CONCEPT_HDL skill skill code to traverse design not working properly9 s1 x) A1 t v% q
1114630 CONCEPT_HDL ARCHIVER Archcore fails because the project directory on Linux has a space in the name8 L5 H* l; n1 S3 j8 `+ S
1114689 CONCEPT_HDL CORE Unknown project directive : text_editor/ ^6 z# A% g$ r3 M
1114928 F2B PACKAGERXL error (SPCODD - 5) while Export Physical even after change pin from A<0> to A2 o# B, e8 W s
1115625 ALLEGRO_EDITOR SKILL Design extents corrupted when axlTrigger is used.2 d- i. y! T- q6 d& T: F% K7 t
1115708 ALLEGRO_EDITOR INTERFACES Export DXF is outputting corrupt data on one layer. |
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发表于 2013-4-9 15:08
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