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4 }- W) f5 V" J5 N* rDATE: 03-29-2013 HOTFIX VERSION: 006
4 M @/ L3 e" S===================================================================================================================================: P$ d' @- k# z; B1 O
CCRID PRODUCT PRODUCTLEVEL2 TITLE
8 `+ Z( J0 p( p; P===================================================================================================================================5 F$ s5 `2 k! E
110139 FIRST_ENCOUNTE GUI Error in Save OA Design form
) B0 }& C8 w7 A2 D- z- R( |; M625821 concept_HDL CORE publishpdf from command line doen not work if temp directory does not exist.2 h2 z8 s( l, |+ W4 K, w5 C
642837 Pspice SIMULATOR Option to disable Bias Points when Primary Analysis in Active Simulation Profile is DC Sweep5 ?$ j7 v7 V7 [& X, @
650578 allegro_EDITOR SHAPE Allegro should do void only selected Shape without "Update Shape".8 W0 e9 m' z' F9 J7 M/ \4 y
653835 ALLEGRO_EDITOR MANUFACT Double character drill code overlaps with "cross" in NC drill legend
9 @, x4 v. y- v5 u/ K2 H7 m/ A: v687170 SIP_LAYOUT DRC_CONSTRAINTS Shape to Route Keepout spacing DRC display incorrect9 i$ l2 U0 F4 ]& b4 g c% S3 f, t, u2 m
787041 FSP DE-HDL_SCHEMATIC FSP Refdes inconsistency when gen schematics# ?# Z) a2 j$ n5 w
825813 CONCEPT_HDL CORE HDL crashes when copying a property from one H block to other( T' w6 C# E' T/ ~
834211 ALLEGRO_EDITOR SHAPE Constant tweaking of shape oversize values is time consuming% I7 d0 A* ?0 r4 @, U
835944 ALLEGRO_EDITOR OTHER Customer want to change for Jumper symbol by other Alt symbol.
: x, h p: I2 L' ~' k; Q8 z( B868981 SCM SETUP SCM responds slow when trying to browse signal integrity) ~6 a# Y) C2 Z6 F: J. T4 a: P' O
871899 CONCEPT_HDL CORE 'Multiple:' column of Grid window in DE-HDL option is too wide
8 k! i) n: @* q1 e5 r7 f. @5 O873917 CONCEPT_HDL CORE Markers dialog is not refreshed
& W' b2 C9 ^7 |+ c887887 CONCEPT_HDL CORE Option to find unconnected Pins/Nets with DEHDL L License
. J, D3 y$ ?6 |. |1 r8 v, c888290 APD DIE_GENERATOR Die Generation Improvement
2 k8 @9 a4 I+ M: Q# N892857 CONCEPT_HDL CORE packager treats R? as a unique reference designator
- Y+ U( y" S, R1 ^; M: F902908 PSPICE SIMULATOR Support of CSHUNT Option in Pspice
; J: Y, |9 ?: K4 m% o908254 ALLEGRO_EDITOR INTERACTIV Enhancement request for DRC marker to have a link to CM, O0 a. W3 J* D, N
922422 CAPTURE NETLIST_ALLEGRO Netlist errors when using mix of convert and normal symbols, U0 I) Y& z8 Y8 `2 N2 {
923361 ALLEGRO_EDITOR INTERACTIV Stop writting PATH variables in env file if no modifications are done using User Preferences- C7 R5 M' W( o2 }
935155 CAPTURE DRC No any warning messages listed in the On line DRC window even executed "Check & Save" to on line DRC
- `5 a/ R* w) t1 K7 E2 i% [) U# s945393 FSP OTHER group contigous pin support enhancement, J$ |5 m% \" a
969342 ALLEGRO_EDITOR DATABASE Enhanced password security for Allegro database
S8 L: }( t& e/ Z1005078 CAPTURE ANNOTATE Copy paste operation does not fill the missing refdes
6 k U4 C7 }/ \8 I1 S \, N1005812 F2B BOM bomhdl fails on bigger SCM Projects
X4 k5 V4 [* P6 b1010988 CAPTURE OPTIONS ENH: ADD ISO 8601 Date Time format to Capture8 ?# @- G# e: `% _/ O( u$ G) m2 P
1011325 ALLEGRO_EDITOR PLACEMENT Placement replication creates modules with duplicate names9 k- G, m% L3 v
1016640 ALLEGRO_EDITOR PLACEMENT Error/Warning Message for not finding or unmatched mechanical symbol or fiducials or which are not on a net# d- D8 ~2 ^. i/ q2 M# v, Z
1018756 CONCEPT_HDL CONSTRAINT_MGR Match Groups with Pin Pairs are not getting imported into the schematic CM during Import Physical- i: i# a1 q: t2 g/ A6 T' @
1032387 FSP OTHER Pointer to set Mapping file for project based library.# T. F" n6 p% O7 a2 \) y
1032609 FSP IMPORT_CONSTRAIN Import qsf into FSP fails with 縋LL PLL_3 does not exist in device instance�
1 c! h' J* [& b" ^$ ?" z; G! g! i4 I1040678 ALLEGRO_EDITOR MANUFACT Text spacing is inconsistant for top and bottom SM layer in xsection chart8 f- j0 k# s2 L: m" t3 Y5 ~2 d# D" G
1042025 APD WIREBOND Order placement of power rings for power/ground rings generation with using PeRForm Auto Bonding
$ O7 U% B2 M! B t7 P- K1045500 CONCEPT_HDL CORE Why Search results does not display the correct Physical Pages.( i% r4 S! F3 m, N# z; L
1047259 CIS EXPLORER Sorting in CIS Explorer is not Numeric even for columns which are of Numeric data type
" B: d: v% U8 O1047756 CAPTURE NETLISTS Not adding user defined properties in netlist generated by orDump.dll7 g4 z/ O* _1 f
1052455 RF_PCB DISCRETE_LIBX_2A RFPCB IFF Export to fix port direction for ADS for footprint having the same pin rotation
) z- Z! K0 V3 i' f2 u1 S. f1054314 CONCEPT_HDL CORE Zoom of custom text is different from other schematic objects2 \ z8 f2 k6 h! z" _
1061529 CONCEPT_HDL CORE Space can be included in LOCATION value and cannot be checked by checkplus* u; y! B, s, W0 k; s$ s. Y9 E3 g! N
1064035 CONCEPT_HDL COMP_BROWSER Component Browser crashes on part number search using a library containing >23K parts
d4 y" I$ ]& G; ?: [& U7 ~* `1064604 ALLEGRO_EDITOR MANUFACT Enh - Include ability to add slot notes to designs1 r& P% e3 O0 e6 V1 T/ e( c9 g, I
1065636 CONCEPT_HDL OTHER Text not visible in published pdf3 L# G6 ?6 f1 T% n, F# m
1065843 CIS PART_MANAGER time stamp on library from different time zones triggers part manager lib out of date warnings
2 C1 t- g3 h- M, U+ g2 y1066701 ALLEGRO_EDITOR OTHER Missing padstack warnings not in Symbol refresh log summary
) }) i* H, m$ w1067283 SCM PACKAGER ALLOW_CONN_SWAP does not work for lower level schematic parts
, t6 [0 |$ A4 b3 Z* l. q# n1067400 CONCEPT_HDL CORE ERROR(SPCOCD-171): Port exists in symbol but not in the schematic
/ e& a- Z8 N: y2 B# L! Q7 D* I) ?+ q1068878 CONCEPT_HDL CORE Rotating symbol causes the pin name to be upside down2 W2 }* ?1 t$ k6 _3 V3 v: f2 {: r
1069896 ALLEGRO_EDITOR EDIT_ETCH Cline changes to arc when routing even when Line lock is set to Line 45
. Z o4 q8 c9 A% ~/ U1070465 CONCEPT_HDL CORE Why does ConceptHDL crash on renaming a Port Signal2 |' D0 m) E& P6 U
1071037 PSPICE SIMULATOR Provide option to disable Index Files Time Stamp Check
. N% h" k; X/ r8 [. {! ^1072311 CONCEPT_HDL OTHER Schematics are incorrect after importing design.: A3 ~: h' X' y
1072691 CONCEPT_HDL CORE Customer has the crash from Run Script of DE-HDL 16.51 again(#3)3 o3 F- k3 ^3 B3 T
1072859 SIP_LAYOUT DIE_EDITOR padstack selection window crash from Die Editing: Component editing of Co-Design Die
" t! H6 \# B5 {+ V/ n' w0 ?1073354 CONCEPT_HDL CORE Bubble defined on symbol pin is not visible on the schematic. h1 w/ x# U3 j" h: B7 }
1073837 ALLEGRO_EDITOR GRAPHICS Some objects disappear on ZoomIn ZoomOut
2 K) p5 _( d6 c6 F9 E; o1074243 ALLEGRO_EDITOR GRAPHICS Allegro WorldView window does not always refresh after dehighlight of objects
' s P2 u% _7 }2 f0 k( Q s1074606 ALLEGRO_EDITOR INTERACTIV Enh - Cosmetic change in Filter Option UI of Replace padstack to indicate multiple pin entry format3 Z2 W8 B; I* b' J+ i ^, r1 D
1074794 ALLEGRO_EDITOR REPORTS add commonly reguested via reports to Allegro and ICP reports. Via per net, via per layer per net
' L8 `+ F6 p0 [% w/ E1 N' o( [1075587 CONCEPT_HDL PAGE_MGMT Unable to insert page in schematic. o6 g$ q" h! X9 K& p
1076117 PSPICE PROBE Copy & Paste text/label in probe window changes font size and later gets invisible
$ q& z/ {( }" v3 l4 ~3 a1076145 SIP_LAYOUT DIE_ABSTRACT_IF Issue message in Add Codesign and Refresh Die Abstract if Pin Numbers from Die Abstract exceed 31 chars.) o3 m: j, r4 a, F4 Y$ e! ?
1076566 ALLEGRO_EDITOR EDIT_ETCH Sliding diff pair cline that has a min/max prop rule displays the HUD meter inconsistently.; o7 c$ U7 b, [8 O% d A* B7 g: u
1076604 ALLEGRO_EDITOR SHAPE Sliding via in pad corrupts surrounding shape and generates false DRC Errors# ~( h }# Q- W
1076820 SPECCTRA FANOUT Fanout fails to stack vias in bga pads.
: Y* m5 p9 p% _. ]0 o1076868 ALLEGRO_EDITOR PARTITION Symbols become 'read only' inside a design partition
! H; G9 R! w9 F/ Y4 K- V/ ?( R1076879 GRE IFP_INTERACTIVE Plan Column should not be present in Visibility tab for Symbol Editor
. r B) i6 G2 |5 u+ Z1076898 CONCEPT_HDL CORE User can not increase logic grid size value continuously using Up button on Design Entry HDL Options% Z) {& A5 H h3 _% V# \& H
1077026 CIS LINK_DATABASE_PA fonts changes while linking db part in 16.5
S- z, G3 U) Y1 k* H% y1077187 ALLEGRO_EDITOR DATABASE DBDoctor appears to fix database but nothing is listed in the log file.
, o/ f9 O1 Q+ q' N' `: B* s' F; ~6 q1077527 CONCEPT_HDL CORE ConceptHDL net with name U cannot be found using Global navigate
v% z* K/ ~/ a$ F3 v1077621 CONCEPT_HDL CORE DEHDL crashes when saving page 30 d# `; t3 h+ b
1078270 SCM UI Physical net is not unique or not valid7 z7 J" P" N" _
1079616 CONSTRAINT_MGR CONCEPT_HDL Packager error in 16.5 which is resolved when system is re-booted
/ L8 ^; m# p# @% X& n1 y7 j8 @1079821 CONCEPT_HDL CORE Project Setup does not respect $TEMP variable for temp_dir and creates a directory in project calle
+ b Z% E4 s: v- K6 x1080142 CIS CONFIGURATION peated entries in Allowed Part Ref Prefs: z/ x; E3 ^( d/ R0 f
1080207 ALLEGRO_EDITOR INTERACTIV Separate the 2 types of SOV violations."Segments over voids & Segments with missing plane coverage"
; h, l4 a* [) q; ^7 M6 Y5 l1080261 PSPICE SIMULATOR Encryption support for lines longer than 125 characters
5 Z i! ^) @( W1080336 CONCEPT_HDL CORE Backannotation error message ehnancement
3 ~* p# P2 T( y" x4 @1081001 ALLEGRO_EDITOR PLACEMENT Package boundary is not visible while manually placing a component when using orcad license
" x" g- C# T9 D+ n8 q1081237 ALLEGRO_EDITOR PLACEMENT Place replicate > apply does not apply component pin properties stored in .mdd
: H4 y5 d* o9 C% j+ |( h1 {$ F' ?: p1081284 MODEL_INTEGRIT TRANSLATION Space in the file path will create a bogus error
5 X/ |9 g( |: ?. k- K/ c) ?: p1081346 ALLEGRO_EDITOR INTERACTIV With Place manual, rotation of the symbol is not updated.
2 M! Q# Q: s3 k9 E: I1081760 FSP CONFIG_SETTINGS Content of �FPGA Input/Output Onchip termination� columns resets after update csv command
- H) A8 i% x. @. z( \3 s1082220 FLOWS OTHER Error SPCOCV-353
& D. z: M9 y6 W0 Y3 C1 [9 [) n1082492 ALLEGRO_EDITOR PLACEMENT Place replicate create does not highlight symbols.
# d5 Q6 m5 Y! f1082676 ALLEGRO_EDITOR EDIT_ETCH HUD meter doesnot display while sliding / add command
# R M- m+ k8 v) b% } L1082737 CAPTURE GENERAL The 緼rea select� icon shows wrong icon in Capture canvas.
* h" ?" p- h7 Q1082739 CAPTURE OTHER The product choices dialogue box shows incorrect name( p/ E s2 }& n8 M1 w5 {
1082785 CONCEPT_HDL CORE DE HDL should clean the design with non sync properties in some automated way
. v2 S" Z1 }" _. L* f( d1083761 CONCEPT_HDL OTHER AGND text missing from PDF Publisher+ E* g# V3 p9 l/ f) q a# s
1083964 CONCEPT_HDL OTHER Do not display Value and other attributes on variant parts which are DNI
! Q% ] V0 n. l5 \1084023 PSPICE MODELEDITOR Model Editor is slow/unresponsive while opening a Model by double-clicking on .lib file' F" g6 R; {2 B1 k" K0 O/ s9 H% H
1084178 ALLEGRO_EDITOR SHAPE Spike create on dynamic void.+ m' F* K. n5 F% a
1084637 ALLEGRO_EDITOR INTERACTIV Enhancement: Pick dialog should automatically be set to enter coordinates( n8 v0 Z7 C( I
1085010 CONCEPT_HDL CREFER Crefer crashes if the property value in the dcf file has more than 255 characters
! N: z7 c6 B" {5 ]1 f1085347 CAPTURE SCHEMATIC_EDITOR Replace cache results is loss of net graphic changes.
* P6 M, t* m* C1085522 ALLEGRO_EDITOR INTERACTIV Allegro add angle to Display->Measure results
* v7 }, k$ o# M( m1085791 CONCEPT_HDL CORE Publish PDF can not output Constraint Manager properties into PDF file.
% G6 T2 `# q* M: `1085891 ALLEGRO_EDITOR INTERACTIV about DRC update/ @2 J8 e+ \3 ]8 w1 a( A
1085990 CAPTURE DRC B1: "ERROR(ORCAP-2207) Check Bus Width Mismatch" should be INFO
1 x I% {9 m- D, `2 \1086514 CONCEPT_HDL COMP_BROWSER Component Browser placement restrictions not working
: _' U' v" z8 Z3 U; U1086576 CONCEPT_HDL CHECKPLUS CheckPlus hangs when running Graphic rules.
6 s3 P0 |# n4 ]* b3 @1086671 PSPICE SIMULATOR SPB16.6 pspice crashes with attached design2 q, {, |# X- |; \, [. B
1086749 ALLEGRO_EDITOR mentor mbs2brd: DEFAULT_NET_TYPE rule is not translated7 D- Q+ a5 p2 r
1086886 CAPTURE PROPERTY_EDITOR "Is No Connect" check box in property editor doesn't work for power pins* _; w3 G- j; }) [3 h& ~
1086902 CONCEPT_HDL INFRA Problems occurred while loading design connectivity) a4 f% [% r& ?6 G
1086937 PSPICE ENVIRONMENT PSpice Color map getting doubled leading to crash after colors are modified number of times.
6 ~2 v3 C; [5 Y- }' ?, ]1087221 CONCEPT_HDL OTHER Part manager could not update any parts.; G3 z. y$ L6 X' D8 @; o, B) F
1087223 CAPTURE CROSSREF Cross Probing issue when login into system with user name containing white space
: z; ~( j5 X; L% T* j) h+ h1087295 SIP_LAYOUT EXPORT_DATA Enable "Package Overlay File for IC" for concurrent co-design dies too7 Z! _' L* R8 f6 p, n4 i3 \
1087658 CAPTURE PRINT/PLOT/OUTPU Lower level design pages are getting print twice* q2 u, ]' {& |
1088231 F2B PACKAGERXL Design fails to package in 16.5% x6 I0 S: U# x
1088252 CONCEPT_HDL CORE Menu commands grayed out after Save (with 16.5-s035) when launched from ASA.# k% @2 M5 E+ ?% x/ X
1088606 ALLEGRO_EDITOR INTERACTIV Pin Number field do not support Pin Range for Symbol Editor
+ b: X! C- e" z3 h0 W2 W1088983 CONSTRAINT_MGR CONCEPT_HDL Units resolution changed in 16.6 Constraint Manager7 }9 V( A1 X$ P7 w/ d9 d( t( ~) F3 t; O
1089017 ALLEGRO_EDITOR SHAPE What is the cause of the shape not filling?
* f' L+ }+ g3 Q" M) j/ j1089259 SCM IMPORTS Cannot import block into ASA design
' n1 _5 K6 W/ G2 S+ |' }: A( T; j1089356 SIP_LAYOUT DIE_EDITOR Distributed co-design : launching die editor taking more than an hour to bring up edit form
& \- M7 Y$ J0 @1 x1089362 PSPICE STABILITY Pspice crash on pspice > view simulation result on attached project
! q, a, E+ _ T5 ?/ t7 W$ i1089368 SCM OTHER Can't do Save - cp: cannot stat ... No such file or directory, I! C/ s u, o4 p: S
1089605 CONCEPT_HDL CONSTRAINT_MGR Power net missing from the CM opened from DEHDL Schematic editor.3 f8 l) w' y- G8 w7 ?
1090068 ALLEGRO_EDITOR SHAPE shape priority issue in SPB165
% N4 H3 a! s4 g2 {2 h1090125 ALLEGRO_EDITOR DATABASE Q- The rename resequence log file is not giving correct message.) I' m- T) k7 e z6 V( P( v3 V' n
1090181 GRE CORE AiDT fails for the nets with errors SPGRE-21 & SPGRE-22
5 w( _: Z h% Y4 y1 E3 }: z3 [ N1090930 CONSTRAINT_MGR CONCEPT_HDL DEHDL-CM does not retain customized worksheet.: Z& v) W4 v$ m1 m
1091335 CONCEPT_HDL OTHER Color change cannot remain in some situation.
2 h7 C) h: y2 A% u1 ^7 p1 p1091347 CAPTURE TCL_INTERFACE The Project New link on Start Page doesn't work when Journaling is enabled
; B7 C- k0 h. P& @& e6 [4 J4 q8 B5 L4 {8 Q1091359 CAPTURE GENERAL Toolbar Customization missing description
6 {. g% e0 s/ b0 [1091662 CONCEPT_HDL CORE Incorrect behavior with the SHOW_PNN_SIGNAME directive
7 d R# ^. a) p3 {1 u1091714 CAPTURE PART_EDITOR More than one icons gets selected in part editor at the same time0 ~3 m& X# |/ Q- M4 o9 V" z1 F
1092411 CONSTRAINT_MGR INTERACTIV In v16.6 CM multiple net name selection under net column is not working as in v16.53 O% [% o* _+ }6 O' P4 C0 [
1092426 CONCEPT_HDL CORE Getting ERROR(SPCOCN-1993) while saving a Hierarchical Design! T5 q0 w5 z, n; s9 c1 \; L
1092874 CONCEPT_HDL CORE DEHDL wire short during move not detected with check enabled8 n+ x w1 t- Q: J1 ~ v+ Q: X, O: M
1092882 ALLEGRO_EDITOR EDIT_ETCH AICC should be removed from orcad PCB Designers design parameters, E6 V3 G( X) ]7 F$ q% X# `9 {% a# F
1092918 CAPTURE GENERATE_PART Generate part functionality gives no/misleading information in sesison log in case of error7 E9 o$ X3 z7 Z- L- Z4 K+ L
1092933 CONCEPT_HDL OTHER PDF Publisher saves the pdf generated in the previous project folder5 c; {! W. Z4 b8 q4 O% y( |% W
1093327 CONCEPT_HDL OTHER Getting error SPCODD � 369 Unable to load physical part in variant editor
3 f& Z) z" ^) H( |/ V) a1093391 CONSTRAINT_MGR OTHER Setup > Constraints > (domain), doesn't open correct worksheet with OrCAD PCB Editor Professional license.
& [, E+ r0 a7 E: n8 U5 {! o1093886 SPECCTRA HIGHSPEED Pin delay does not work in PCB Router when specified in time! @4 q8 d8 f6 N7 _; |9 A
1094223 CAPTURE PROPERTY_EDITOR CTRL+S does not work in Property Editor but RMB > Save.1 Y% v+ g5 h! U0 b+ y+ i5 S
1094513 CONCEPT_HDL CORE How to display $PNN for which SIG_NAME is not visible?
7 m* \2 J0 V2 |5 e) R1094611 CAPTURE PROPERTY_EDITOR E1: 'Tools->Update Properties' should list parts which are present in .UPD, but not schematic
( o3 x7 X% C6 l% P# n' B1094618 CONCEPT_HDL INFRA Unable to uprev the design in 16.5
: h; B% g( Q3 v3 j) q1094867 CONCEPT_HDL CORE Page Up / Down Keys are hard-coded assigned to Next /Previous Sheet
, T( B% i+ O( S1 M( h- R1095449 SIP_LAYOUT LOGIC Allow netlist-in wizard to work on a co-design die
0 d% x5 L/ B: Y% C% q0 y1095701 CONCEPT_HDL CORE Replace part in replicated block only preserves the Refdes in 1st instance of the replicated block
9 J' n3 G9 p$ Y1 Z4 c4 @4 u C1095705 CONCEPT_HDL CREFER Cref_to_list not updated on repl icated blocks in 16.5 release worked fine in 16.3# d9 g$ S, Z* J. H. |
1095861 F2B BOM Using Upper-case Input produces incorrect BOM results
$ F- W7 d Q+ e1 \# M1096318 ALLEGRO_EDITOR INTERFACES IDF import not removing MCAD tagged objects during import
6 m5 c! t3 ?+ i- h$ h$ m; T' s1097241 CONCEPT_HDL CORE Concepthdl - zoom in to first object in Find result automatically
1 G$ G6 \6 y+ R) ?* ~' A- _5 m1097468 ALLEGRO_EDITOR INTERACTIV Need ability to hilight and assign color to vias
* k0 G' t. x, x. \1097675 CAPTURE ANNOTATE Enhancement:Option to have Incremental reference Update to be checked at all times when we click on Tool>Annotate4 ~/ }5 H$ Z9 I
1099151 SIG_INTEGRITY SIMULATION All Neighbor crosstalk numbers reported when there are no aggressors
$ ^6 m. `- c& U1099175 CONCEPT_HDL CORE CPM directive that enables the Command Console Window in DE-HDL8 ~4 O* I/ R6 g) m0 L. R/ j# E
1099838 CAPTURE TCL_INTERFACE TCL library correction utility is not working correctly.
" a ~& N* K% r% _7 I3 K/ a* z, Y1099903 ALLEGRO_EDITOR PLACEMENT Mirror and rotating component places component mirror side1 N, I2 O6 o) `* L9 a8 w7 A5 h
1099941 ALLEGRO_EDITOR PLACEMENT Problem in rotating bottom components when using Place Manual or place manual -h command0 `# F$ O6 o8 n/ D
1099998 CONCEPT_HDL CHECKPLUS CheckPlus marker file not locating signal when signal name includes the # character.
" J" s4 A3 t- A' D1100018 CONCEPT_HDL COPY_PROJECT CopyProject gives errors about locked directives8 Q b1 K7 M5 J
1100449 ALLEGRO_EDITOR ARTWORK Pad with Net_short property and shorted to shape supressed wrongly with Pad Supression in Artwork# c2 Q2 ^' N* W1 T* Q2 b
1100758 CAPTURE LIBRARY Import properties does not update pin numbers of multi section parts
- ^+ V; ]( A2 W6 J% i# c1101009 CONCEPT_HDL CORE Cursor stays as arrow after performing File > Save Hierarchy! N5 @; S9 v# U, K
1101497 ALLEGRO_EDITOR UI_FORMS Allegro PCB Editor crashes using attached script when working with RF PCB Clearances.
$ M# ?: l* r+ l3 z$ K7 x3 J1101813 SIP_LAYOUT DIE_ABSTRACT_IF Support die abstract properties# J0 `9 n; r4 t
1102531 ALLEGRO_EDITOR GRAPHICS Allegro graphics distortion infinite cursor 16.6
/ a5 P5 @& N5 w% n" @* D1102623 ALLEGRO_EDITOR SHAPE Strange void around the pad
! d' A1 q% |1 F3 @1103246 FSP FPGA_SUPPORT New FPGA request - Arria V - 5AGXMA1D6F31 - IN2P3' s6 j3 u" M! f( [8 Y; u2 p
1103631 MODEL_INTEGRIT OTHER Model Integrity license when using orcad" ]8 Y0 a1 C% |% V3 G
1103703 F2B DESIGNSYNC Toolcrash with Design Differences# ?% Z4 a# C1 m* M* {8 u
1103712 CONCEPT_HDL COPY_PROJECT Copy Project crashes on customer design attempting to update symbol view" S# B5 c2 u' z: l5 p. Z
1104068 CAPTURE DRC "Check single node connection" DRC gets reset in 16.6 O( | r3 T$ w( _
1104121 PSPICE AA_OPT 縋arameter Selection� window not showing all the components : on WinXP
2 ~3 b3 |4 ?( i% A2 n# X) t0 X1104575 CONCEPT_HDL CORE Allign does not allign offgrid symbols correctly9 H9 I3 u8 S# P; K) { C: e( G+ l3 C
1104727 CONSTRAINT_MGR SCM Net Group created in sip does not transfer to SCM/ B$ c5 m) A( e* U% b" _
1105128 CONSTRAINT_MGR DATABASE Import dcf does not clear out user defined schedule.9 f) X. }9 E& E& m8 |) |0 k. k
1105195 SIP_LAYOUT WIREBOND Request that Tack points default to a "fixed" position after Generate Bond Wires.6 q, _: X8 n. i7 D( |3 s& r
1105249 ALLEGRO_EDITOR OTHER PDF out--- component user defined prop doesn't list the prop selection form2 u; x' U0 T' p! `1 Z: v) X. [: v
1105443 PSPICE AA_OPT Parameter selection window in optimizer does not list param part
9 G. R8 B- v" S( ~1105818 ALLEGRO_EDITOR INTERACTIV Menu-items seperators are clickable and menu goes away when clicked0 h# d4 l9 w; H8 ^, v+ C3 h
1105822 ALLEGRO_EDITOR SCHEM_FTB Netrev failing with compact pin syntax
( o" z. K& a" C& c6 R4 O& f, b1105993 SIP_LAYOUT LOGIC Import netlist no longer works with co-design die in SiP 16.6+ ^; @; \3 ~* y6 d
1106332 SIP_LAYOUT OTHER sprintf for axlSpreadsheetDefineCell writes characters in upper case only
9 m! q( j* D7 } ^8 o1106786 CAPTURE SCHEMATICS Bug: Pointer snap to grid
! F! E9 v5 ]$ ?/ j, D% R: U6 D0 R1107132 FSP OTHER Altera ArriaV (5AGXMA5GF31C4) support.4 ] M% s: [! u/ a Z5 |
1107151 ALLEGRO_EDITOR ARTWORK Shape filling removed when changing artwork format to RS274X in Global Dynamic Param
. h( e4 K" s! e, ]' x1107237 SIP_LAYOUT WIZARDS Updating a Die using the Die Text In Wizard will error out and not finish
; R* s4 w) F' H% q1107371 ADW COMPONENT_BROWSE ADW preset Warning filter is spelt incorrectly. (Wraning).
8 Z; A7 C. F8 x% E: U% J. D1107599 CAPTURE STABILITY Capture 16.6 crash when trying to invoke% C0 Z: n3 E& a+ o, c
1108118 ALLEGRO_EDITOR OTHER PDF Publisher pad rotation messed up with flashed pad.+ n' S' g! q# E) Y) i1 h
1108574 ADW COMPONENT_BROWSE LifecycleStatus functionality does not work when in Metadata mode. Work correctly in PPT Mode1 T3 ~, S0 F4 C. _- k
1109095 SIP_LAYOUT WIREBOND Bondfinger move in hug mode create drcs3 o+ {+ L* ^) M/ ?# w* a8 F( b8 j& R
1109113 ALLEGRO_EDITOR DATABASE Allegro Netrev crash with SPB 16.66 E9 c1 [. m. F( ~
1109622 SIP_LAYOUT DATABASE In a wirebond design, the ratsnests with 'Closest Endpoint' should not point to the die pins.
+ I3 n( b/ {6 ]4 E1110077 ALLEGRO_EDITOR DRC_CONSTR Duplicate Drill Hole DRC's are not shown for Pins overlapped in same symbol unless "Min metal to metal" DRC is turned ON- ^, L6 ?5 J& Q& u
1110256 ALLEGRO_EDITOR SHAPE Auto void on dynamic shape is not correct in 16.6( `, f( R1 r; Z6 B
1110264 RF_PCB FE_IFF_IMPORT IFF Import in DEHDL has component offset; z2 D7 j' s# y6 o: l
1111226 ALLEGRO_EDITOR DATABASE Name too long error with Uprev command when output file name exceeds 31 characters6 H% K$ G6 T7 L( r* _
1111234 ALLEGRO_EDITOR MANUFACT Double digit drill character overlaps with figures triangle, hexagon and octagon in NC drill legend
) x7 _3 O* I+ o5 m1112431 SIP_LAYOUT COLOR Frequent crash while working with latest version of CDNSIP
) }, @# \* M7 [2 \2 n0 q1112493 ALLEGRO_EDITOR DATABASE Customer does not like 16.6 Ratsnest points Closest Endpoint
8 F& g- B1 Y& c) i+ E0 V" l2 [1112774 GRE CORE Allegro GRE not able to commit plan after topological plan9 l7 T% y3 k, W* q
1113908 ALLEGRO_EDITOR COLOR Dehilight command fails to remove highlight pattern on a cline, without removing net custom color.
( K; b. e; Z" ?9 Z+ l" n0 n1114815 ALLEGRO_EDITOR OTHER Q1: Switchversion error when reading -fa file3 {% V# ~; h9 L/ E% h
1114994 ALLEGRO_EDITOR DATABASE Getting an error after upreving components to 16.6$ N" {$ x/ D/ g! ]" g' m4 L
& \, L+ D1 f3 I# p4 w4 ODATE: 03-7-2013 HOTFIX VERSION: 005, \% i3 P' n* r
===================================================================================================================================9 ]; ]6 L2 S" h/ ?$ [
CCRID PRODUCT PRODUCTLEVEL2 TITLE6 |9 t, S8 ^; o9 \
===================================================================================================================================) o& F! p4 s" G$ P' l' C! e
1067770 IXCOM-COMPILE COVERAGE Assertion failed: file ../covToggleCoverageXform.cpp, line 1102
4 I8 c0 n% r. x$ r* C, d1100442 ALLEGRO_EDITOR PLACEMENT Placement queue shows components whichs are already placed* o- r: B& \% S; s
1101555 ALLEGRO_EDITOR DATABASE Allegro Crash frequently
8 p9 o% O5 S& } B( _1 M1104011 ALLEGRO_EDITOR DATABASE Place replicate move group of a modules leaves traces behind& ?% l" B+ v9 Z9 }
1104065 SCM NETLISTER SCM 16.6 has problem generating Verilog with existing sym_1 view( M8 |$ f! S2 `0 q& U2 m+ m
1104605 F2B PACKAGERXL Pins of function swapped part in block not displayed
2 q7 g4 N4 G( K% Q5 B1104790 SCM IMPORTS Corrupt data once SiP file is imported into SCM
. O y( m4 u5 p. x, X4 z0 `1105066 APD IMPORT_DATA Import NA2 worked in 16.5 "035" but fails in 037 and 16.6
, A( E5 @' O) ^% C5 B' `7 T; j" V1106323 ALLEGRO_EDITOR PLACEMENT Unable to locate specific placed symbol on this board as it becomes invisible after placement.
3 e/ {1 H4 K( h8 H1 Q1108032 CONCEPT_HDL CORE 'Find' option does not list all Components in the Design! ]1 Z9 J( u* w4 f8 F
1109080 ALLEGRO_EDITOR OTHER Window DRC is not working in OrCAD PCB Editor Professional
" \ g: N' h5 _' X9 n; V" _; t. J" _0 |( L
DATE: 02-22-2013 HOTFIX VERSION: 004
% _4 f) e9 K/ m3 s===================================================================================================================================* d6 q g3 g1 B+ u* d
CCRID PRODUCT PRODUCTLEVEL2 TITLE
: o5 \- O3 u9 m& r2 S, ~===================================================================================================================================/ W- U6 y$ ]2 ^* @7 A) R
1081026 ALLEGRO_EDITOR GRAPHICS 3D Viewer do not show the height for the embedded component correctly
7 i* V% I0 U" v1 G: f1095225 ALLEGRO_EDITOR EDIT_ETCH The Constraint option does not work from right mouse click>Options>Line Width > constraint during interactive routing
$ B4 x" w+ J' ]7 J1096356 ALLEGRO_EDITOR DATABASE Cannot Analyze a Matched Group in CM/ c- R |, M) H. t
1097481 ALLEGRO_EDITOR INTERACTIV Allow replace padstack command in design partition
- j2 b! J: G' N% G1098252 ALLEGRO_EDITOR MANUFACT Double digit drill character overlaps with figure "circle" in NC drill legend& b: s. M5 _ N# F8 b5 H
1099958 ALLEGRO_EDITOR PAD_EDITOR Library Drill Report producing an empty report; M- e9 t+ _, q6 Y/ {
1100401 ALLEGRO_EDITOR OTHER Invalid switch message for "m" for a2dxf command5 J+ U" `3 v2 ]) [, u: M$ c3 S
1101026 ALLEGRO_EDITOR OTHER utl_perftune hanging in fpoly_RemoveVerySmallSegments(), causing shape degassing never to exit.
1 d3 m7 I2 K) M1101064 SIP_LAYOUT SHAPE 'Shape force update creates a rat& k/ o5 ]5 ?8 U9 Z; G
1102798 SIP_LAYOUT OTHER Stream out puts offset pad in wrong position if pad is mirrored but not rotated.* z( E9 P! K2 `; m* {* T
) t5 q8 f$ K- L2 T$ K& gDATE: 02-8-2013 HOTFIX VERSION: 0034 x; G% f- _9 ]( p
===================================================================================================================================
3 d* \3 b/ W+ }2 k" `CCRID PRODUCT PRODUCTLEVEL2 TITLE0 K, Z1 _) ^5 {) P4 F2 U; t3 z+ V
===================================================================================================================================* q- N3 f+ L! y! g7 r
1077728 APD EXTRACT Extracta.exe generate the incorrect result
* N: O+ d7 K, H+ X; `: b1084711 APD DXF_IF Padstacks with offsets cause violations in Export > DXF
+ l( Z) c% |% s1090369 SIG_INTEGRITY LICENSING Impedance value not updating in OrCAD PCB Designer
& a2 f& s' A5 W# e% N1093050 ALLEGRO_EDITOR DRC_CONSTR Taper trace on diff pairs not checking to min line spacing.
$ m8 C: M1 M& f }7 ]4 ]1093563 SPECCTRA ROUTE PCB Router crashes with reduce_padstack set to on; l, T) F' v8 w
1093717 APD DATABASE Design is crashing in Tools > Update DRC and in Dbcheck but seems inconsistent
6 z- a& K& N5 y1 [1094788 SIP_LAYOUT WIREBOND Wirebond edit move command2 o. H r* Q; O# q2 ^
1095786 ALLEGRO_EDITOR DRC_TIMING_CHK Allegro PCB crashes when running DBDoctor9 C) f) y4 Z' k& X* x
1096234 ALLEGRO_EDITOR DFA Via pad connected to shape didn縯 show up after 縎uppress unconnected pads� option.* G# X$ I2 k& f- a, N( d" S
1096313 RF_PCB LIB_TRANSLATOR Allegro Discrete Library to Agilent ADS Translator offsets in the CDNSsymbo.iff7 Y* U8 F+ k* N& X+ P: E5 B, P
1096613 ALLEGRO_EDITOR INTERACTIV Enh-While moving parts silk ref des should remain visible
8 V: Q7 k2 n0 V1096676 CONCEPT_HDL CORE SPB 16.5 HF36 breaks designs that workded fine in HF35
5 m# X/ \; W& W F; U: k1096913 APD IMPORT_DATA Import > NA2 fails to bring in the Y1 component.
' _1 L2 G- C' v8 M1097751 ALLEGRO_EDITOR DATABASE Import CIS netlist crashes./ i& K \; d; T+ h! g5 n3 v
1097889 ALLEGRO_EDITOR DRC_TIMING_CHK Allegro crashes when routing from a via to a pin using High Speed option license.9 }; K. b _3 x7 s' `( @* W) L4 x
" @: ~2 j$ q2 g) tDATE: 1-25-2013 HOTFIX VERSION: 002
9 }9 L P8 e/ E===================================================================================================================================0 `0 `1 A/ K0 F
CCRID PRODUCT PRODUCTLEVEL2 TITLE
, k* a! G2 i6 d/ F5 l$ j===================================================================================================================================* o1 ~3 G2 O7 y0 V# J2 Z) O+ g
491042 CONCEPT_HDL SECTION Prevent PackagerXL from changing visibility on SEC attribute+ ?1 b$ h2 O5 J# ^! [
863928 ALLEGRO_EDITOR INTERACTIV Segment over void higlights false "nets with arc"6 T6 y) U: b: j- S7 N) m; o
1067272 PCB_LIBRARIAN CORE Unable to retain the symbol outline changes4 j C' {' z" [& P1 O
1074820 ALLEGRO_EDITOR GRAPHICS losing infinite cursor tracking after selecting the add text command with opengl enable0 z* U" n6 Q: r4 f' j8 i" E
1075622 CONCEPT_HDL CORE PDV Edit Symbol in DE-HDL all editing functions disabled since Hotfix 33
0 s% I8 K( z' S% ^1076986 APD WIREBOND Wirebond Adjust Min DRC does not maintain the finger position in the same sequence
( z+ s2 g' E: T; J1 D* Z1078031 SIG_INTEGRITY REPORTS Requesting improvement to progress indicator for report generator
4 Z$ l+ h! _& N* _8 x1080213 SIP_LAYOUT WIREBOND Wrong behavior of Redistribute Fingers Command1 }) O P, ?! ~& F) a9 x
1080667 ALLEGRO_EDITOR GRAPHICS Allegro lines with fonts not displayed correctly in 16.6
0 t9 y" v1 M2 K c1080982 CONCEPT_HDL CORE Crash of Allegro Design Entry during a copy of a note.
" \# O9 u; A/ A' ^: Q" n/ j1081200 CONSTRAINT_MGR OTHER In the DIFF_PAIR worksheets various Analysis seem to take a long time to complete.
& |6 Y& m* H1 h! A( ~ e: M T1081553 CONCEPT_HDL OTHER Model Assignment can not translate M (Milli-ohm) property value of DE HDL.( i" A1 [' w5 }1 f9 B, m; O
1081696 ALLEGRO_EDITOR INTERACTIV Compose shape not working when radius is set to 1.0% z9 R: r, h" y$ ?
1082595 ALLEGRO_EDITOR COLOR Infinite cursor remains white even we change background to white$ J% {- [7 _$ |& e
1082704 ALLEGRO_EDITOR GRAPHICS infinite cursor disappears when using Display>Measure
2 v0 {, m) b& o: H1082715 SIG_EXPLORER INTERACTIV Single line impedance for BOTTOM Layer is not calculated in cross section upon changing the thickness of dielectic layer
% \ E5 ~. |: b6 E1082774 ALLEGRO_EDITOR TECHFILE Import techfile command terminates abnormally when importing a generic techfile.7 Z/ @" J9 D b$ e& v+ ?
1082820 CONSTRAINT_MGR UI_FORMS The configure generic cross-section pull downs do not work.
6 \+ q6 J6 F) r; g% i) M" `1083133 SIP_LAYOUT INTERACTIVE SiP will crash when using the beta Pad Rename command to change a BGA pads name.
2 M1 m, ?+ M9 W/ U1083158 ALLEGRO_EDITOR GRAPHICS The cursor chage to Arrow head for Shape Select is more sensitive to location in SPB 16.6
5 P0 O) {5 O1 B4 J6 P1083533 CONCEPT_HDL CONSTRAINT_MGR Bug -Net-count under few of the netclasses are not in sync between Schematics & Layout% a+ ?- ?. i" r7 ~
1083637 PCB_LIBRARIAN CORE Save As is not renaming the NAME in the symbol.css file
( y( h7 D7 R5 n# `6 F1083934 ALLEGRO_EDITOR PAD_EDITOR Error(SPMHUT-41): File selected is not of type Drawing.5 r3 T3 p* d5 k9 B+ Y7 X
1084148 CONCEPT_HDL CHECKPLUS The CheckPlus hasProperty predicate fails in the Physical environment.* _' u: N$ J" N5 u6 ~6 M" t9 { u% G5 O
1084166 SIP_LAYOUT DIE_ABSTRACT_IF Updating sip layout with new die abstract doesn't properly update IC_DESIGN_CELL* properties
; y$ R; A% Z( \0 E6 z1084285 CONCEPT_HDL INFRA Corrupted dcf was never fixed and caused PXL error
5 e6 \4 E+ y/ K! `1084441 CONCEPT_HDL CORE Assigned net property value changes to numeric
4 O k& s: F- }, j1084542 ALLEGRO_EDITOR DRAFTING Dimensions associated with frect doesn't rotate with the symbol.6 \9 t- J; h' j# D0 s
1084736 APD IMPORT_DATA Import SPD2 file from UPD-L shape Pad and text issue# \& x# S. ?# P* p1 K
1085008 ALLEGRO_EDITOR INTERACTIV Relative (from last pick) option in the Pick dialog not working for pick command
' |$ s; d6 x4 d0 m1085139 ALLEGRO_EDITOR GRAPHICS Infinite Cursor disappear during Add Connect if Infinite_cursor_bug_nt is enabled7 O5 {; A, o# l% ?( L- g: }
1085187 SIP_LAYOUT INTERFACE_PLANNE netrev with overwrite constraints fatal error& A" c- N# ^, T
1086402 ALLEGRO_EDITOR GRAPHICS Infinite cursor dissapear when using command like add connect or Place manually with opengl enabled.8 l/ o8 W t% I* j
1086905 PSPICE SIMULATOR PSpice crash while simulating circuit file with BREAK function; d- G6 Y* R2 a4 d" o: w
1087770 ALLEGRO_EDITOR EDIT_ETCH Allegro crashes on a pick with the slide command." a6 Q+ v$ n; v+ D
1088412 SCM CONCEPT_IMPORT why reimport block adds _1 to the netnames?; ?2 d/ Q5 E! ?) J+ c! ~/ a
1088958 CONSTRAINT_MGR INTERACTIV annot create Differential Pairs out of nets that belongs to a Net Group' u. g9 r8 w! P0 n: U7 l% K
1089336 ALLEGRO_EDITOR GRAPHICS infinite cursor and pcb_cursor_angle
; W. ^) b6 H% Z& r+ N3 x1090689 ADW LRM LRM: Unable to select any Row regardless of Status
- ^: L% M3 [: N6 A6 @, c1090955 ALLEGRO_EDITOR OTHER Cancel command crashes PCB Editor when add rectangle
9 Z O2 g. d& q8 e# G- S1091047 ALLEGRO_EDITOR REPORTS The "Dangling Lines Via and Antenna� report seems to be missing vias that are antennas.
, W' Z4 m, \: ?1091218 ADW LRM LRM is not worked for the block design of included project
: d; h4 b4 }; [4 I" S4 X$ b1091443 ALLEGRO_EDITOR OTHER Crash when toggling suppress pads' t5 X5 i' M# x2 u8 v/ m3 b: n
1091706 ALLEGRO_EDITOR EDIT_ETCH Allegro crash while routing after setting variable acon_no_impedance_width& ^) L. `* L% k3 {3 d% N9 W2 g
1092916 CAPTURE OTHER Capture crash4 g8 ]" O5 v+ q
1093573 ALLEGRO_EDITOR DATABASE team design opening workflow manager crashes allegro. possibly corrupt database0 W7 ?7 b% ?% x: C' Y% s# V
7 z0 p. A2 j0 y w0 ^! KDATE: 12-18-2012 HOTFIX VERSION: 0014 U8 i. e3 d3 E/ `# j/ p& j
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CCRID PRODUCT PRODUCTLEVEL2 TITLE3 d! G# Q6 S) m9 M% }
===================================================================================================================================
+ K2 u% R7 ~( m# W501079 ALLEGRO_EDITOR MODULES Enhancement for Module swap function similar to component swap
0 A, G% m+ X$ c) F$ ^! H3 s745682 CONCEPT_HDL CORE Attributes window requires resizing each time DEHDL is launched$ X% m* I( }9 i
825846 CONCEPT_HDL CORE The module_order.dat file gets corrupted# s( k( J& E6 E
871886 CONCEPT_HDL CORE Browse button in Signal Integrity window of DE-HDL option causes program crash
0 t( `0 h' x' Y' D891439 ALLEGRO_EDITOR INTERACTIV moving cline segments" H/ [7 v5 U3 g# g7 r( ]
898029 CAPTURE PRINT/PLOT/OUTPU ENH: TCL:To show net alias clearly in print out if alias has underscore
1 P- g3 B% b7 |923210 CONCEPT_HDL CORE Search with multiple properties does not show all properties/ |5 t, P O6 {! i) [
938977 CONCEPT_HDL CORE Properties attached to standard/DRAWING symbol does not propagate to parts placed in the schematic0 g& }$ R: v, C4 b* e; I
947451 ALLEGRO_EDITOR INTERACTIV Allow the tool to select multiple shapes when assigning a net to more than one shape.0 k* L- ~+ d: d; s* {" p
968646 ALLEGRO_EDITOR EDIT_ETCH The Cline to Pad spacing not followed for Multidrill pad it is more then minimum spacing
& Z! V p( v* y T6 q; r8 O* U976723 ADW MODEL_MANAGEMENT SI DML Model has to be provided the Auto Generate function for discrete components on DBeditor# r8 z, O/ d# U
981767 SCM UI Add series termination in ASA will crash if both output and input pins are selected.- o+ Y I8 z( j) {. O b. s( `" k
982273 SCM OTHER Package radio button is grayed out6 Y1 |$ W0 Q/ }7 Z; W
988438 CONCEPT_HDL CORE Visible constraint disrupts MOVE command9 ~5 l2 z; ?, M! D( r8 j+ X
989471 ALLEGRO_EDITOR INTERACTIV Functionality to zoom to the selected object in Pre Select Mode3 _5 e% Q& @- D
993562 CONCEPT_HDL INFRA After upreving the design save hierarchy is leading to WARNING(SPCOCD-34).
5 r" w: v5 M" h% ~% t2 N996577 SPECCTRA ROUTE Specctra not routing NET_SHORT connections; L% ]$ o. j. b) c. F: v9 [5 d
997992 CONCEPT_HDL CORE Why are Page Numbers not enumerated correctly when multiple TOC Symbols are used?6 Y5 R# a" m v8 e9 y }
1001300 PSPICE MODELEDITOR BUG: Simserver crash with encryptedm model3 s, X5 ^7 ? I2 r7 {* j
1010124 PSPICE SIMULATOR Monte Carlo summary doesn't list all the runs in case of Convergence error in one of the runs
- d; S, g0 o% e: Q1 x1013656 SCM OTHER create diff-pair should honour diff-pair setup or ask user for positive negative leg; l& }! \( S2 [$ S
1013721 ALLEGRO_EDITOR EDIT_ETCH Routing near a 2x3 multi drill padstack does not maintain the spacing constraints.
* f, D+ C5 r) m5 ]: g1016859 SCM REPORTS dsreportgen exits with %errorlevel%& k' [' {4 _* X% k
1018506 ALLEGRO_EDITOR INTERACTIV Edit copy with retain net of via will assign net to pin
7 C% Z" \8 Q5 }: b" k m1020746 CONCEPT_HDL OTHER PDF Publisher tool behavior inconsistent between OSs
8 C$ K$ U' r& B9 l- _0 j. Z: `1020798 SIP_LAYOUT SHAPE Shape not voiding on layer 2 causing shorts2 r- _# P$ k9 p9 w0 i
1023051 SCM UI Wrong and incorrect message is generated while adding connectivity in SCM matrix view � DSTABLE-140: ^" n" r1 ]( w9 u+ ?2 i& G
1023774 APD WIREBOND After "xml wire profile data" is imported it isn't reflected to actual wire.
+ Y/ |! G. C) d1 f1023807 SPECCTRA GUI Unable to close SPECCTRA using File > Quit or by clicking on standard window red close cross button
! E% m0 P. Q6 f3 t$ K/ P1024239 ALLEGRO_EDITOR INTERFACES DXF pin location is moved when I execute DXF out+ j. x: C$ J) P3 A0 F
1028237 CONCEPT_HDL HDLDIRECT Error binding design when generating simulation netlist+ J: a( G* z! E7 ?* E/ K `
1030591 CAPTURE LIBRARY Library Correction utiltiy locks the library and deosn't frees it even after being closed# [, F1 r2 K1 o
1035624 CONCEPT_HDL CORE Options pre-selected when launching base product
7 x7 w) ]3 Y% W1035896 SIP_LAYOUT ASSY_RULE_CHECK Rule Wire Length under Wire on line in Assembly Rule Checker doesn't work correctly4 `( d; ]2 J4 x; X% P
1036580 ALLEGRO_EDITOR MODULES Module created from completely routed board file has lot of missing connections in it.
; }0 }4 c3 ~+ u6 g, _# U5 n4 \1037345 ALLEGRO_EDITOR INTERACTIV Enhance Allegro's Snap-To tools to select the origin of a sub-drawing(clip file)3 l, {( C9 ^- s) s* J* T' K( o! Y
1038180 ALLEGRO_EDITOR DRC_CONSTR BGA escapes not being calculated in phase tol
* {5 I' Y2 g. G+ K1038285 SCM UI Restore the option to launch DE-HDL after schgen.2 E9 X% E: L: y
1038371 ALLEGRO_EDITOR INTERFACES Import > IDF fails with error "(SPMHDB-187): SHAPE boundary may not cross itself."9 P% v2 w2 A' A! ]
1038577 ALLEGRO_EDITOR DATABASE Modifying Void crashes Allegro
# F+ V2 R: y2 z8 p) @$ R/ d1039112 ALLEGRO_EDITOR ARTWORK Antietch and Boundary layers deleted when Match Display selected
8 J: o) h- B3 Y1 ?! X1039147 ALLEGRO_EDITOR COLOR Need an option to change color of Text marker and Text select in Display listing
& G$ M7 |& g9 t* c5 d7 {) }1040653 ALLEGRO_EDITOR DATABASE Cannot update netlist data, ERROR(SPMHDB-121): Attribute definition not found.
* _9 J! z5 h7 {. M& z1041368 APD DEGASSING The Degas_No_Void properties assigned to Cline does not work.' Y% I- o2 c5 U6 G d: m9 `
1041864 ALLEGRO_EDITOR MANUFACT Allegro crashes when opening the Backdrill setup menu3 t: ?2 R8 \% K% k+ M
1042199 SIG_INTEGRITY SIMULATION Waveform list was not refreshed by switching tab.- ^* S5 F% H4 L. d3 \1 J
1042348 SIP_LAYOUT STREAM_IF GDSII export includes the full refernce path, breaks CATS flow2 p4 Z0 Y, ]: b. g$ M# ~7 b
1043861 SIG_INTEGRITY REPORTS Derating values are NA in bus simulation report when derating table is not in working directory, T( G* c5 W* u
1043903 GRE GLOBAL This design crashes during planning phases in GRE.8 T( \+ C& j% ?6 W! ?' w( u
1044029 PSPICE ENCRYPTION Encrypted lib not working for attached
9 W1 H% P; ^+ T- P! k# Q1044222 ALLEGRO_EDITOR INTERACTIV Capture Canvas Image changes working directory
8 y4 z; [# n& j: h5 B+ Q" a5 n( [1044264 PSPICE SIMULATOR Why does the 'ORPSIM-15009:This device scales to 0.0 at this Temperature' Error occur.
. {9 h6 \0 C s, j1044577 GRE CORE Plan > Topological either crashes or hangs GRE
9 z, Z B) w% ` \7 R" J1044687 TDA CORE tda does not get launched if java is not installed
( { b2 y/ q8 Y( b1044754 SIG_INTEGRITY SIMULATION Incorrect waveforms when simulating with stacked die
3 k- k" L S7 ?8 ]1045607 ALLEGRO_EDITOR OTHER Component get placed even after Cancel IDF in form./ F' \1 q1 o: }6 m1 D% C
1045694 CONCEPT_HDL INFRA Why to package the design twice to pass the net_short property to the board?
' ~. E. l0 M. W- C/ n+ C2 R. p1045863 CONCEPT_HDL INFRA Customer had the crash several times when they run script with SPB16.51.3 ?6 o- C) S: W m7 C6 w! ?* M
1046929 CONSTRAINT_MGR OTHER Unable to create physical of spacing cset after rename the default cset in design entry.
3 x4 i1 m2 _7 {; `1 s1047590 ALLEGRO_EDITOR SCHEM_FTB Buses created in Allegro-CM are deleted by netrev in traditional flow& H3 t& X" u, U4 ~7 m+ {4 p* ~% Q' Y8 P
1047823 CONSTRAINT_MGR OTHER acPutValue predicate text not being displayed at bottom of Constraint Manager window.
% |2 f7 t' L1 d' p5 f1 @1048403 ALLEGRO_EDITOR skill Allegro crashes opening more than 16 files with skill
3 X( `) l4 G, Z$ g; n: o' x1049262 ALLEGRO_EDITOR OTHER APD and extracta crash owing to Wirebond.
6 B/ }' V5 V2 S1049303 CONCEPT_HDL CORE Block rename deletes schematic data immediately in 16.52 |$ Q' W6 r% L+ H
1049317 CONCEPT_HDL OTHER bomhdl with scm mode not working on RHEL in 16.57 ~& Q1 V; X) g; s
1049399 SIG_INTEGRITY OTHER Toggling z-axis delay in CM shows the same value
9 A/ V! ~" q% J/ S+ l7 H* p) t1049956 ALLEGRO_EDITOR DATABASE BUG:dbdoctor deletes fillets as design is migrated from old version
: o6 y4 Y) w' ~9 a, J/ N1050408 APD DXF_IF Symbol has 45 degrees rotation in mcm but DXF doesn縯.
c% M4 n/ W5 P. {. ?5 p$ u1050483 ALLEGRO_EDITOR DRC_CONSTR DRC has been waived but after updated DRC system generated a new DRC.2 r, R: m1 E' u
1050918 ALLEGRO_EDITOR MANUFACT Testprep Automatic generate testpoints with wrong padstack Itype in SPB165S026.3 B* N1 B7 X/ a1 [; v
1051588 ALLEGRO_EDITOR PAD_EDITOR Pad_Designer library drill report omits some drill holes5 h) ^( i! y. V' p& y) w
1052005 SIG_INTEGRITY OTHER Huge difference in Z-Axis delay with the latest hotfix for 16.5 that did not exist in older ISR's of 16.5.) C- T- [/ r9 x% u
1052045 ALLEGRO_EDITOR OTHER Bug - Thermal relief connects not sustaining 15 degrees component spin in version 16.5 unlike v16.3
+ K1 _3 `2 D! J- z! O+ [1052449 CONCEPT_HDL COPY_PROJECT Copy Project does not update all relative paths in the cpm file2 e5 U- O1 S' a
1052600 ALLEGRO_EDITOR SHAPE Adding a specific cline causing shape errors
$ ^# L l( D5 z# e5 c1052753 ALLEGRO_EDITOR DRC_CONSTR Allegro showing soldermask drc only when the symbol is rotated.% _! I# T t8 c$ O3 X: n5 z
1054235 ALLEGRO_EDITOR PLACEMENT Cannot place alt_symbols for mechanical parts.* K4 L _4 D/ p5 ~1 T( M
1054269 ALLEGRO_EDITOR MANUFACT Backdrill Setup and Analysis crashes on attached design9 h3 o2 C& P( E$ a) Z p6 r- G: F
1054351 ALLEGRO_EDITOR SHAPE Shape voiding fails for board having diffpairs with arcs) i7 w6 k) J8 h5 T( s# r$ g
1054456 ALLEGRO_EDITOR MENTOR mbs2lib incorrectly translates refdes label
# F3 m4 \$ P8 t1 y% S1055273 ALLEGRO_EDITOR INTERFACES DXF exported from Allegro has an offset in pad location for Y- direction.
$ J! Z) T5 S+ L. u7 Y ~" [1 }1055328 CONCEPT_HDL COPY_PROJECT Project Manager - Project Copy9 b% T5 m9 j1 m7 Q. C# ~+ o
1055481 APD SHAPE keepout does not clear shape unless it's picked up and dropped down
& q. I# I- Q |) i$ x$ a1055729 CIS GEN_BOM Standard CIS BOM per page is not working correctly with option Process Selection3 K( ?$ U. m; K9 y1 f2 V
1056418 ALLEGRO_EDITOR OTHER PDF exports the blank text markers whether or not the markers are visible.2 r; W2 X* X; k3 l1 G8 z
1056579 CAPTURE OTHER Ability to define custom variables for titleblocks that update for specific variant views
# J [- `; R! s1 F' ?9 N% R5 G1057003 ALLEGRO_EDITOR SHAPE Z-copy to create RKI does not follow board outline* {+ j! \, [4 H3 w0 N4 }; Q
1057976 ALLEGRO_EDITOR DRC_CONSTR No Same net Spacing DRC on attached design.
' W. k7 a0 L) g0 D0 k+ C1058002 SIG_INTEGRITY SIMULATION Incorrect Xtalk sim netlist was created.5 {, N4 B1 B1 A. l2 s
1058364 ALLEGRO_EDITOR SKILL axlTransformObject() is moving refdes text when only symbol pin is selected for move
3 e+ Y4 F1 g1 M, p: w. a6 {1058940 ALLEGRO_EDITOR INTERFACES IDF(PTC) out command output wrong angle value$ [/ b& a+ w" v. s
1059037 CIS PLACE_DATABASE_P What enables the Refresh symbol libs option under hte update menu in CIS explorer3 Q9 S8 I$ Q S9 q% H
1059389 ALLEGRO_EDITOR MANUFACT about back drill analisys report/ a2 H# {1 v& K8 i
1059901 CONCEPT_HDL CORE Global Property Change and <<OCC_DELETED>> property value.
- `2 g0 _7 w4 w& C4 C1060428 ADW DESIGN_INIT ADW Flow Manager Copy Project fails to complete
( X C }" t O d" j1060589 F2B PACKAGERXL Packager Fails with ERROR(SPCOPK-1053): Cannot find a ppt part that matches the instance properties.8 G$ T% [8 |1 b9 a, s0 C
1060977 F2B DESIGNSYNC back annotate in 16.5 does not bring in already placed nets as global nets
' Y( d9 S& f: E% M1061223 CONCEPT_HDL CHECKPLUS What determines a passthru pin?1 {2 _5 W# w9 _; p g) L+ t
1061424 CONCEPT_HDL CORE Customer creates <<OCC_DELETED>> property values.! F" A- a' D1 L, }+ @5 T+ M v
1061572 ALLEGRO_EDITOR INTERACTIV Shortcut keys wont work after "Edit Text" command is finished.
2 M) z% A* C8 @2 E% v* K3 }- B1061659 ALLEGRO_EDITOR DATABASE Unable to return drawing origin to 003 Q. g# J) t; B& n& y: c
1062558 APD DXF_IF If set both in X and Y offset DXF only get one and not get absolutely value in 45 degree rotation
; F) |, I# V+ i7 `1062982 ALLEGRO_EDITOR MODULES Module containg partitions has been imported to the main design and cant be refreshed.
/ ]: t1 w& }$ |1063284 PCB_LIBRARIAN OTHER PDV Save As is broken
; m7 g1 R1 p- k! H1063658 ALLEGRO_EDITOR SCHEM_FTB Allegro Import Logic does not remove library defined diffpairs
. _. A! Z% V" b& d1063778 CONCEPT_HDL CHECKPLUS The hasSynonyms CheckPlus predicate is not returning true for all global signals.
3 Z' b7 n0 |" H# ^4 b, p1063924 CONCEPT_HDL CONSTRAINT_MGR Highlight the net between DE-HDL 16.5 and Constraint Manager.
- C4 n7 ?5 N" r! A! I1064707 CONCEPT_HDL CHECKPLUS Rules Checker core dumps on design( e. P, E U4 ^" v
1065124 PCB_LIBRARIAN SETUP PTF properties cannot be deleted from the setup in PDV$ S0 I1 k6 W8 @! j- ^/ |
1065618 CONSTRAINT_MGR ANALYSIS DRCs on board but Constraint Manager shows the columns as green.# G1 i/ K: ?7 E2 I5 ~: x
1065641 PCB_LIBRARIAN CORE PDV symbol editor is crashing when deleting a group using delete or CTRL+X6 V; Y7 K, J1 e' w5 N
1065745 SIP_LAYOUT DATABASE The logic assign net command crashes the application
8 R S& D3 O. s; n- E% P1065860 ALLEGRO_EDITOR REPORTS Design crashes when running a padstack usage report3 x/ N9 h- z. w8 j( T. G
1066051 ALLEGRO_EDITOR TESTPREP Auto Testprep generation creates TP with Testpoint to Component Locatin DRC
) D' j1 C. e ?$ M7 b/ N6 W: _: q1066318 CONCEPT_HDL CREFER Issue with LOCATION visibility in flattened schematic
$ c0 C8 G3 J% ~' v* |1067339 CONSTRAINT_MGR ANALYSIS Relative Propagation Delay analysis in the Partition file seems very inconsitent./ G( d8 F1 W9 M7 ?) w ]
1067984 SIP_LAYOUT OTHER layer compare batch fails with write protected file' B H- T& [' V- F2 ], a
1068425 F2B DESIGNVARI Out of memory message in Variant Editor while 縞hange properties� command- P/ s8 l& }8 L8 l* Q( O
1068547 ALLEGRO_EDITOR EDIT_ETCH Outward Fanout is not fanning out this 4 sided part as intended1 s- ~/ S3 n- ]3 H, N1 @. M8 \
1068966 SIP_LAYOUT DRC_CONSTRAINTS DRC update aborts on this design with ERROR -30000671 b9 [* T- l$ x
1069215 CAPTURE DATABASE Capture Crash on usnig a TCL utltiy to correct design+ w, F1 x# h9 x( q
1069517 SIP_LAYOUT DIE_EDITOR change die abstract pins tab default action from delete to modify
/ |* ]' o$ X9 o) |1 n1069915 ALLEGRO_EDITOR EDIT_ETCH Allegro hangs with when doing spread between voids
" D* ~% Y. A3 r0 K: D1070007 ALLEGRO_EDITOR PLOTTING Export IPF omits drill figure characters for backdrill holes
9 Y. v2 D, ^6 |* n6 D- n" r1071722 SIP_RF DIEEXPORT Virtuoso SiP Architect not writing out pins to the .dra needed for LVS flow( D6 J7 E4 t% f) v/ W" V! N" R8 c% i) s
1072067 APD EXTRACT When expoting using Extracta oblong pads with anyangle are abnormal0 o7 i$ X- _) e5 e3 J
1072791 ALLEGRO_EDITOR DATABASE Database check cannot fix error and keep report the same issues cause artwork cannot export.
0 M7 R: [/ `& b5 M1072806 CIS EXPLORE_DATABASE Query tab in CIS explorer doesn't show searh fields in 16.6& {& ^& X( `) a( C$ h! m/ M9 W* S
1072843 ALLEGRO_EDITOR PLACEMENT The move command that was present in the right mouse pop up menu during manual placement is missing in 16.5; W/ E6 D9 G4 o8 X8 [. }
1072904 SIP_FLOW SIP_LAYOUT Probe pins not being mirrored in Die Editor correctly in Chip Down mode.
2 D' G; b+ O& M) x1073237 SIG_INTEGRITY GEOMETRY_EXTRACT Some nets has no result at Bus Simulation and Comprehensive simulation.) r" u' F3 T/ l
1073445 ALLEGRO_EDITOR GRAPHICS 'infinite cursor graphics fail -ghost copies as you move cursor
' l1 h0 }4 W' M$ P6 B, G1073464 SCM SCHGEN Schgen never completes.& e1 J7 { e6 q$ K' I2 X
1073587 SIP_LAYOUT OTHER axlSpreadsheetSetWorksheet command clears the cells in memory( E5 S/ N$ G1 ]" Y+ x1 l
1073745 CONCEPT_HDL CORE Import design fails
' l K7 n; z' Q! A1073852 ALLEGRO_EDITOR INTERACTIV While doing a Copy Via use the last 'Copy Origin'
; ?3 \ L f3 [( N6 F, o" ~' z, ]1074279 ADW DSN_MIGRATION Design Migration fails purge if there are cells with BODY_TYPE
& J8 X/ i- `, _1074791 CONCEPT_HDL HDLDIRECT User gets port exists in schematic but not on symbol message even though the port does not exist
7 } r6 N* U- a# I1075135 ALLEGRO_EDITOR DRAFTING Ability to edit dimension text block in Instance Parameter2 V' x1 X& f2 O* k* N' G+ ?
1075151 ALLEGRO_EDITOR SHAPE Cannot change global shape parameter back to thermal width oversize after having used fixed thermal
1 B: R8 H, \7 T& L1 }) L" H, @1075256 ALLEGRO_EDITOR OTHER Import > IPF in 16.5 is dropping data." ]; m' P5 x) X$ g" b( i
1075853 ALLEGRO_EDITOR REPORTS please add "PART_NAME" at Extract UI1 \7 E" p7 e0 n( G, Z) G
1075934 ALLEGRO_EDITOR DRAFTING Able to Changing Dimension Text Block
, @, g; V1 S4 b0 q0 x1075955 CAPTURE SCHEMATIC_EDITOR ZOOM in 16.6 using key "I" on keyboard in not centered on mouse pointer
7 H! L) L) z) p( V5 ]1075964 ALLEGRO_EDITOR SHAPE Shape voiding is not consistent in conjunction with odd angle and arc traces8 J! R7 C. A3 d, G% n
1076086 SIP_LAYOUT IMPORT_DATA missing wirebond after import SPD2
, M' j4 B, \. J' h8 f1076202 ALLEGRO_EDITOR EDIT_ETCH Allegro add connect causing crash after Hotfix7 R; Y% Z! d" h1 {' |6 J7 M8 n
1076205 CAPTURE PRINT/PLOT/OUTPU : Printing of User Assigned RefDes
6 w6 `( s1 M0 T1076536 ALLEGRO_EDITOR DRC_CONSTR Embedded component which protrude out toward Top do not create DRC with Place Keepout on Top; H+ L8 a- e) E5 m2 T4 G
1076538 CONCEPT_HDL CORE Property visibility changes in attribute form not updated in schematic canvas.
X3 e6 ?+ Q: K' X% L- M2 \1076655 APD DXF_IF Dxf does not get offset value if die symbol padstack has offset value) d' {6 @4 `3 c9 L
1076846 ALLEGRO_EDITOR EDIT_ETCH Grid snapping broken after slide in 16.6
* v: D+ t6 W$ F5 w7 }1076891 ALLEGRO_EDITOR INTERACTIV Symbol rotation not displayed correctly when defined as a funckey
: j) @9 o! W: d% [1076909 ALLEGRO_EDITOR DRC_CONSTR Allegro crashes while placing modules from database7 I4 d4 o' F" M& P+ w! e4 O
1077084 CAPTURE NETGROUPS Crash on selecting bus when Enable Global ITC is unset0 ~ ]# v. a: i' A3 W h O
1077169 APD SHAPE Shape > Check is producing bogus results.9 l) W; r4 t" T& _( j+ `% u C
1077572 ALLEGRO_EDITOR DATABASE Mechanical symbol created with 16.6 cannot be placed on board.
+ k* J; K) L# t$ c8 \1077879 ALLEGRO_EDITOR SKILL Allegro Skill axlDBCreateFilmRec fails when 15th argument missing "draw hole only" for the first tim* X+ b4 X! O5 l- m7 p
1078380 SCM OTHER Custom template works in Windows but not Linux7 _% [% l2 i9 ]( ~2 N e! v, Q
1078497 ALLEGRO_EDITOR INTERFACES Import DXF does not seem to work correctly.
5 E7 H6 _' I+ ?1 F' y8 m1078682 ALLEGRO_EDITOR DRC_CONSTR Unaccetable slowness with Slide
) Z& P9 g' N) T1079082 ALLEGRO_EDITOR PLACEMENT Swap components, gives error SPMHGE-616, when symbols instead of components are selected for swapping
. k, {/ D1 J5 [4 B' Q: u4 L1079533 ALLEGRO_EDITOR PLACEMENT Swapping components in 16.6 results in Error "E-(SPMHGE-616): Symbol and layer embedding requirements do not match"
, x( w+ x- C6 h. X# {8 K( w; \1079937 CAPTURE SCHEMATIC_EDITOR ZOOM in 16.6 is non uniform on text
. d- ^# e6 f0 N# ?- f1082582 ALLEGRO_EDITOR GRAPHICS Allegro hangs on a given testcase using the MMB zoom control
! N$ z6 b, P1 U1082981 ALLEGRO_EDITOR SKILL Allegro crash while change the new symbol type as mechanical.4 Y& V% @9 J# b/ r% L6 h% @
1083230 SIP_LAYOUT SHAPE Shape fill in 16.6 releaase not fillilng shapes as good as it did in the 16.5 release.; a5 Q6 K" g* |! j3 q
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/ a# k- w( j5 I: P下载链接：# ]% v: h- `$ @- G3 M( E
http://pan.baidu.com/share/link?shareid=332083&uk=3826038294
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发表于 2013-3-29 16:28
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