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cadence SPB16.6已经推出,需要的朋友可以点击下面的链接下载:( h/ _$ m# u3 x' e9 ~0 j9 P. @
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下载地址:http://dl.vmall.com/c0eqmqz0e33 Q4 R3 @5 C4 R. k2 [% X
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- \# K8 }7 N3 o6 [' ^Cadence SPB16.6 SuperHotfix003发布,具体修复问题如下:
f7 ~# _# W, ]DATE: 02-8-2013 HOTFIX VERSION: 003
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CCRID PRODUCT PRODUCTLEVEL2 TITLE- B; P6 |6 V% X4 v' e* J& R. z
===================================================================================================================================
4 O) S' @4 R! r: S1077728 APD EXTRACT Extracta.exe generate the incorrect result( R8 C; M v m' \3 c9 {6 z4 x7 t! Y
1084711 APD DXF_IF padstacks with offsets cause violations in Export > DXF
/ r( d/ _9 I V. m1090369 SIG_INTEGRITY LICENSING Impedance value not updating in orcad PCB Designer) d7 ~: U5 [: y% X
1093050 allegro_EDITOR DRC_CONSTR Taper trace on diff pairs not checking to min line spacing.
3 I0 ?8 F+ z" X# h1093563 SPECCTRA ROUTE PCB Router crashes with reduce_padstack set to on' p. V @+ L/ A9 M$ B' b
1093717 APD DATABASE Design is crashing in Tools > Update DRC and in Dbcheck but seems inconsistent
6 ^3 y2 q' ?* d8 _+ _0 N/ a4 e+ }1094788 SIP_LAYOUT WIREBOND Wirebond edit move command
5 l1 C" x" {7 }' }* j7 ^1095786 ALLEGRO_EDITOR DRC_TIMING_CHK Allegro PCB crashes when running DBDoctor& ~: c* d p* A
1096234 ALLEGRO_EDITOR DFA Via pad connected to shape did not show up after suppress unconnected pads option.
* o/ i% b1 |' Q+ l6 `) k1096313 RF_PCB LIB_TRANSLATOR Allegro Discrete Library to Agilent ADS Translator offsets in the CDNSsymbo.iff
' U; O5 A% w" x. m% {" O1096613 ALLEGRO_EDITOR INTERACTIV Enh-While moving parts silk ref des should remain visible
0 ^, H" M0 j. ]7 }5 v4 J1096676 concept_HDL CORE SPB 16.5 HF36 breaks designs that workded fine in HF35
9 _5 W+ y7 S( P1096913 APD IMPORT_DATA Import > NA2 fails to bring in the Y1 component.
2 G3 {: O# c9 I4 ?* k; a, p3 [, B1097751 ALLEGRO_EDITOR DATABASE Import CIS netlist crashes.4 B: f* N. O( i2 g: M
1097889 ALLEGRO_EDITOR DRC_TIMING_CHK Allegro crashes when routing from a via to a pin using High Speed option license.
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