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cadence SPB 16.5及最新Hotfix下载地址(Hotfix更新至038)
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& w' f6 W& Z+ c% _9 {; `, k$ C下载地址:http://dl.vmall.com/c05sb7i5ed
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. c; u: ?3 Y( }: q5 lHotfix中只需要安装最新的版本即可。2 b( c8 s5 D) z# c4 m0 _
3 Y2 Q; t: L1 `; V9 n, A6 NHotfix038对以下项目做了修正:
- ]6 a# c( ~$ DDATE: 02-15-2013 HOTFIX VERSION: 0383 j9 |1 ^) H+ }; ]4 X
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9 s8 a$ } T; _5 W; r9 l787041 FSP DE-HDL_SCHEMATIC FSP Refdes inconsistency when gen schematics
: r3 N+ \1 d8 O" q j- ]) R4 B) h911292 concept_HDL CORE Property command on editing symbol attaches property to ORIGIN immediately: B A# r, z Q" U% E3 b; U
995532 FSP DE-HDL_SCHEMATIC Hierarchical block name representing FPGA does not get updated in DEHDL after refdes change in FSP.
' c1 r4 A' q" h3 a& | @1005812 F2B BOM bomhdl fails on bigger SCM Projects
% q" G9 h) [4 ~3 u% s1045500 CONCEPT_HDL CORE Why Search results does not display the correct Physical Pages.- i9 ~5 h% }* T# O
1059037 CIS PLACE_DATABASE_P Enable Refresh symbol libs menu in CIS explorer7 j. n6 d* }# _" u
1065636 CONCEPT_HDL OTHER Text not visible in published pdf( T2 }# M6 E/ D: Y$ g/ L
1067283 SCM PACKAGER ALLOW_CONN_SWAP does not work for lower level schematic parts
8 [7 q1 _, x6 k& L1073354 CONCEPT_HDL CORE Bubble defined on symbol pin is not visible on the schematic0 c* l% C! N( e% H/ t: P$ K) Q
1077527 CONCEPT_HDL CORE ConceptHDL net with name U cannot be found using Global navigate
* s2 {: H7 q, |1083761 CONCEPT_HDL OTHER AGND text missing from PDF Publisher' K: K5 v: {& {) J" R9 _
1091335 CONCEPT_HDL OTHER Color change cannot remain in some situation.
. H8 x; ~6 q3 x% Z7 Z1093050 allegro_EDITOR DRC_CONSTR Taper trace on diff pairs not checking to min line spacing.
" E7 u5 @$ v5 t7 i" f; F6 e1094513 CONCEPT_HDL CORE How to display $PNN for which SIG_NAME is not visible?
+ u3 C- x1 o( s \) T# H1095705 CONCEPT_HDL CREFER Cref_to_list not updated on repl icated blocks in 16.5 release worked fine in 16.3
! L {* d# i1 L5 q1095786 ALLEGRO_EDITOR DRC_TIMING_CHK Allegro PCB crashes when running DBDoctor/ B! `5 w6 l7 R0 ^2 |- ~
1095861 F2B BOM Using Upper-case Input produces incorrect BOM results
$ O% G9 |$ ?: k1 s/ M* @" G1096234 ALLEGRO_EDITOR DFA Via pad connected to shape didn't show up after suppress unconnected pads� option.
2 q2 b. i' n/ Z l7 G7 B1096313 RF_PCB LIB_TRANSLATOR Allegro Discrete Library to Agilent ADS Translator offsets in the CDNSsymbo.iff
0 W+ f9 E0 t( ^1096613 ALLEGRO_EDITOR INTERACTIV Enh-While moving parts silk ref des should remain visible
" z% n% E1 y2 L' I& N1096676 CONCEPT_HDL CORE SPB 16.5 HF36 breaks designs that workded fine in HF35 p- e% |9 H% B' \' j/ S
1096913 APD IMPORT_DATA Import > NA2 fails to bring in the Y1 component.% j$ |5 p" [, g8 M; `* Z! K- ^. z
1097751 ALLEGRO_EDITOR DATABASE Import CIS netlist crashes.
! R" F! O. L) x( s: p8 R `# [1097889 ALLEGRO_EDITOR DRC_TIMING_CHK Allegro crashes when routing from a via to a pin using High Speed option license.
" t: Q+ W. `% B1 L1098252 ALLEGRO_EDITOR MANUFACT Double digit drill character overlaps with figure "circle" in NC drill legend$ O; f: S. D! m0 B# D
1099151 SIG_INTEGRITY SIMULATION All Neighbor crosstalk numbers reported when there are no aggressors
) P8 t4 D; ]$ a1 {1099998 CONCEPT_HDL CHECKPLUS CheckPlus marker file not locating signal when signal name includes the # character.5 B0 ?5 K6 J5 Y8 y. _
1101009 CONCEPT_HDL CORE Cursor stays as arrow after performing File > Save Hierarchy |
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