|
|
EDA365欢迎您登录!
您需要 登录 才可以下载或查看,没有帐号?注册
x
cadence SPB 16.5及最新Hotfix下载地址(Hotfix更新至038)) L2 H! X5 D4 [" \* `
; t# i$ X1 L3 R! X" x }
. w# C$ i0 H) G( |+ a0 |
* w5 @& ^- ]6 w- m* _ {( c
下载地址:http://dl.vmall.com/c05sb7i5ed
! V6 e1 i: J; C' Y( S5 y2 s9 p
# T$ l) r0 D$ c9 }8 @9 g* Z
6 j8 N% ?. A6 Z6 b8 M; \2 `Hotfix中只需要安装最新的版本即可。
& e+ D0 \, r/ B. F" t
/ X/ g3 Q+ M: J4 cHotfix038对以下项目做了修正:
! O, P# y/ x% q# _* ^; aDATE: 02-15-2013 HOTFIX VERSION: 038
) f: x1 v! S) z/ E! W===================================================================================================================================
9 k' E6 _0 D& ^' G$ Q S PCCRID PRODUCT PRODUCTLEVEL2 TITLE+ U8 i3 @) T3 N- e& g" A1 i
===================================================================================================================================
3 J" o( X; a3 e" q0 D7 ~$ A4 K l& D787041 FSP DE-HDL_SCHEMATIC FSP Refdes inconsistency when gen schematics- U! [/ d; G- R/ `& {- `
911292 concept_HDL CORE Property command on editing symbol attaches property to ORIGIN immediately
0 F, D$ l- l- i0 f7 p995532 FSP DE-HDL_SCHEMATIC Hierarchical block name representing FPGA does not get updated in DEHDL after refdes change in FSP.+ l- i% p! [! ^ G+ N4 j
1005812 F2B BOM bomhdl fails on bigger SCM Projects
6 U4 r# [% d% q4 T: Y1045500 CONCEPT_HDL CORE Why Search results does not display the correct Physical Pages.; u0 l6 W( j* m# `: P; H- z, v
1059037 CIS PLACE_DATABASE_P Enable Refresh symbol libs menu in CIS explorer. V# [1 H& L( d8 g* }
1065636 CONCEPT_HDL OTHER Text not visible in published pdf
; ]; f o Q+ ]# }1 p2 S* G1067283 SCM PACKAGER ALLOW_CONN_SWAP does not work for lower level schematic parts
1 G. K) H* @0 U7 |1 }% b* m1073354 CONCEPT_HDL CORE Bubble defined on symbol pin is not visible on the schematic6 [" L( v/ B' i N- X$ [
1077527 CONCEPT_HDL CORE ConceptHDL net with name U cannot be found using Global navigate2 \' f5 X7 ~- k& A1 O5 n
1083761 CONCEPT_HDL OTHER AGND text missing from PDF Publisher
7 g3 A4 X) X* y/ a/ Q1 V3 l# |1091335 CONCEPT_HDL OTHER Color change cannot remain in some situation.
9 P; \0 ~# M0 @8 X; J7 ?1093050 allegro_EDITOR DRC_CONSTR Taper trace on diff pairs not checking to min line spacing.5 Y6 ^% E; k9 C7 H! j
1094513 CONCEPT_HDL CORE How to display $PNN for which SIG_NAME is not visible?
% Q" |3 a0 q$ Q2 ]; a" \# O1095705 CONCEPT_HDL CREFER Cref_to_list not updated on repl icated blocks in 16.5 release worked fine in 16.3% R" F6 H3 w/ B# S* E
1095786 ALLEGRO_EDITOR DRC_TIMING_CHK Allegro PCB crashes when running DBDoctor# ?/ k- P0 X' B4 Z# Q7 l% P- X: g
1095861 F2B BOM Using Upper-case Input produces incorrect BOM results
/ @# g# F- N& `8 v! {2 d7 R9 w1096234 ALLEGRO_EDITOR DFA Via pad connected to shape didn't show up after suppress unconnected pads� option.
* V ~' {6 h8 E; j; I' H8 m1096313 RF_PCB LIB_TRANSLATOR Allegro Discrete Library to Agilent ADS Translator offsets in the CDNSsymbo.iff+ ?1 Q7 L; W7 S5 u8 W
1096613 ALLEGRO_EDITOR INTERACTIV Enh-While moving parts silk ref des should remain visible' Q1 @- R" b+ @6 Z
1096676 CONCEPT_HDL CORE SPB 16.5 HF36 breaks designs that workded fine in HF35
1 B( h9 L) S$ f6 n& B1096913 APD IMPORT_DATA Import > NA2 fails to bring in the Y1 component.2 V7 Y1 ]' F6 ~3 d# p( ~
1097751 ALLEGRO_EDITOR DATABASE Import CIS netlist crashes.
; s4 j$ P2 i1 w% q3 W; T: F6 r4 Y5 c1097889 ALLEGRO_EDITOR DRC_TIMING_CHK Allegro crashes when routing from a via to a pin using High Speed option license.
- p& G* H0 P4 q. C1 f! @3 F1098252 ALLEGRO_EDITOR MANUFACT Double digit drill character overlaps with figure "circle" in NC drill legend
9 z) r! Z' Q* G4 S. g7 K1099151 SIG_INTEGRITY SIMULATION All Neighbor crosstalk numbers reported when there are no aggressors: b8 }) m- G i
1099998 CONCEPT_HDL CHECKPLUS CheckPlus marker file not locating signal when signal name includes the # character.
) l. E) |$ `- C1101009 CONCEPT_HDL CORE Cursor stays as arrow after performing File > Save Hierarchy |
|