16.6 的 hotfix 出現囉

penny190

{:soso_e100:}
2 Q% ~5 Y# L" l+ V" _4 M16.6 的 hotfix 出現囉 ~~ 14 Dec 2012 SPB16.60.001, Version: SPB:Hotfix:16.60.001~wint   

longzhiming

是不是16.6BUG多得受不了了?{:soso_e120:}

haveok

还在用16.5

rx_78gp02a

期待这个hotfix

rasytc

更新了神马

sz_cheny

求链接

oostilloo

ASI也可以下载了，Allegro Sigrity SI

yueyuan2003

别的地方找到的更新说明，其实干嘛老是跟着公司更新软件啊，我就觉得16.3挺好的，功能就很好了
DATE: 12-18-2012   HOTFIX VERSION: 001
===================================================================================================================================
CCRID   PRODUCT        PRODUCTLEVEL2   TITLE
===================================================================================================================================
; v) ^/ j# `$ ^, F7 A501079  ALLEGRO_EDITOR MODULES          Enhancement for Module swap function similar to component swap
745682  CONCEPT_HDL    CORE             Attributes window requires resizing each time DEHDL is launched
4 [4 t# _) Y9 F' m825846  CONCEPT_HDL    CORE             The module_order.dat file gets corrupted
871886  CONCEPT_HDL    CORE             Browse button in Signal Integrity window of DE-HDL option causes program crash
891439  ALLEGRO_EDITOR INTERACTIV       moving cline segments
898029  CAPTURE        PRINT/PLOT/OUTPU ENH: TCL:To show net alias clearly in print out if alias has underscore
' W: \+ p* _) {923210  CONCEPT_HDL    CORE             Search with multiple properties does not show all properties
# A, @* Q3 d! F. E! e. |8 q938977  CONCEPT_HDL    CORE             Properties attached to standard/DRAWING symbol does not propagate to parts placed in the schematic
947451  ALLEGRO_EDITOR INTERACTIV       Allow the tool to select multiple shapes when assigning a net to more than one shape.
968646  ALLEGRO_EDITOR EDIT_ETCH        The Cline to Pad spacing not followed for Multidrill pad it is more then minimum spacing
% [  x& w, O/ m6 h* T; w# \976723  ADW            MODEL_MANAGEMENT SI DML Model has to be provided the Auto Generate function for discrete components on DBeditor
4 }; a( E) S' I4 a" J  D$ y6 f% z981767  SCM            UI               Add series termination in ASA will crash if both output and input pins are selected.
982273  SCM            OTHER            Package radio button is grayed out
988438  CONCEPT_HDL    CORE             Visible constraint disrupts MOVE command
( L( f3 `* [0 H! U989471  ALLEGRO_EDITOR INTERACTIV       Functionality to zoom to the selected object in Pre Select Mode
/ d% Q/ d4 B& _' p, {9 ^993562  CONCEPT_HDL    INFRA            After upreving the design save hierarchy is leading to WARNING(SPCOCD-34).
1 E3 P  F! Q. N& s4 U0 H" A' z6 X996577  SPECCTRA       ROUTE            Specctra not routing NET_SHORT connections
997992  CONCEPT_HDL    CORE             Why are Page Numbers not enumerated correctly when multiple TOC Symbols are used?
) a0 }# ]; V/ t, j+ y" u1001300 PSPICE         MODELEDITOR      BUG: Simserver crash with encryptedm model
/ {5 A3 v& N0 k! Z4 @1010124 PSPICE         SIMULATOR        Monte Carlo summary doesn't list all the runs in case of Convergence error in one of the runs
1013656 SCM            OTHER            create diff-pair should honour diff-pair setup or ask user for positive negative leg
1 i4 ]- a% }* i1013721 ALLEGRO_EDITOR EDIT_ETCH        Routing near a 2x3 multi drill padstack does not maintain the spacing constraints.
5 t4 ^, ?' s5 m! m1016859 SCM            REPORTS          dsreportgen exits with %errorlevel%
1018506 ALLEGRO_EDITOR INTERACTIV       Edit copy with retain net of via will assign net to pin
1020746 CONCEPT_HDL    OTHER            PDF Publisher tool behavior inconsistent between OSs
1020798 SIP_LAYOUT     SHAPE            Shape not voiding on layer 2 causing shorts
1023051 SCM            UI               Wrong and incorrect message is generated while adding connectivity in SCM matrix view � DSTABLE-140
1023774 APD            WIREBOND         After "xml wire profile data" is imported it isn't reflected to actual wire.
1023807 SPECCTRA       GUI              Unable to close SPECCTRA using File > Quit or by clicking on standard window red close cross button
1024239 ALLEGRO_EDITOR INTERFACES       DXF pin location is moved when I execute DXF out
- ?+ M& J/ q$ h1028237 CONCEPT_HDL    HDLDIRECT        Error binding design when generating simulation netlist
- n. ?1 Y) g& Z  h1 c1030591 CAPTURE        LIBRARY          Library Correction utiltiy locks the library and deosn't frees it even after being closed
1035624 CONCEPT_HDL    CORE             Options pre-selected when launching base product
1035896 SIP_LAYOUT     ASSY_RULE_CHECK  Rule Wire Length under Wire on line in Assembly Rule Checker doesn't work correctly
1036580 ALLEGRO_EDITOR MODULES          Module created from completely routed board file has lot of missing connections in it.
% Q5 g5 C9 s' d2 A4 z/ H7 S: X1037345 ALLEGRO_EDITOR INTERACTIV       Enhance Allegro's Snap-To tools to select the origin of a sub-drawing(clip file)
$ r1 [: S; X! e6 @5 {( x1038180 ALLEGRO_EDITOR DRC_CONSTR       BGA escapes not being calculated in phase tol
3 ~& T* ], u3 ?- E: {, L% I1038285 SCM            UI               Restore the option to launch DE-HDL after schgen.
1038371 ALLEGRO_EDITOR INTERFACES       Import > IDF fails with error "(SPMHDB-187): SHAPE boundary may not cross itself."
' i1 T9 e0 m8 h2 n& V1038577 ALLEGRO_EDITOR DATABASE         Modifying Void crashes Allegro
1039112 ALLEGRO_EDITOR ARTWORK          Antietch and Boundary layers deleted when Match Display selected
& _4 i. [- c) q; F) \* x3 ?1039147 ALLEGRO_EDITOR COLOR            Need an option to change color of Text marker and Text select in Display listing
0 k+ I; j* D9 p- _1040653 ALLEGRO_EDITOR DATABASE         Cannot update netlist data,  ERROR(SPMHDB-121): Attribute definition not found.
1 f! {/ I2 a6 Y0 R1041368 APD            DEGASSING        The Degas_No_Void properties assigned to Cline does not work.
! t$ R7 `$ v1 I/ w- m6 k1 x; h1041864 ALLEGRO_EDITOR MANUFACT         Allegro crashes when opening the Backdrill setup menu
6 a9 J, w8 y0 B9 G1042199 SIG_INTEGRITY  SIMULATION       Waveform list was not refreshed by switching tab.
$ H) J) U0 p4 M2 ]1042348 SIP_LAYOUT     STREAM_IF        GDSII export includes the full refernce path, breaks CATS flow
1043861 SIG_INTEGRITY  REPORTS          Derating values are NA in bus simulation report when derating table is not in working directory
1043903 GRE            GLOBAL           This design crashes during planning phases in GRE.
1044029 PSPICE         ENCRYPTION       Encrypted lib not working for attached
* Y: P! w4 t- b0 v+ B1044222 ALLEGRO_EDITOR INTERACTIV       Capture Canvas Image changes working directory
' r7 w3 b* ^+ s; t' s3 O& o1044264 PSPICE         SIMULATOR        Why does the 'ORPSIM-15009:This device scales to 0.0 at this Temperature' Error occur.
1044577 GRE            CORE             Plan > Topological either crashes or hangs GRE
9 n% ~- a, ?5 G. J! K/ k8 k1044687 TDA            CORE             tda does not get launched if java is not installed
1 v6 G  J& |! P! A1044754 SIG_INTEGRITY  SIMULATION       Incorrect waveforms when simulating with stacked die
1045607 ALLEGRO_EDITOR OTHER            Component get placed even after Cancel IDF in form.
1045694 CONCEPT_HDL    INFRA            Why to package the design twice to pass the net_short property to the board?
$ `; B# M; c$ V  k1045863 CONCEPT_HDL    INFRA            Customer had the crash several times when they run script with SPB16.51.
9 d1 t4 }. t  G* t" B1 u! G1046929 CONSTRAINT_MGR OTHER            Unable to create physical of spacing cset after rename the default cset in design entry.
1047590 ALLEGRO_EDITOR SCHEM_FTB        Buses created in Allegro-CM are deleted by netrev in traditional flow
1047823 CONSTRAINT_MGR OTHER            acPutValue predicate text not being displayed at bottom of Constraint Manager window.
1048403 ALLEGRO_EDITOR SKILL            Allegro crashes opening more than 16 files with skill
1049262 ALLEGRO_EDITOR OTHER            APD and extracta crash owing to Wirebond.
1049303 CONCEPT_HDL    CORE             Block rename deletes schematic data immediately in 16.5
1049317 CONCEPT_HDL    OTHER            bomhdl with scm mode not working on RHEL in 16.5
1049399 SIG_INTEGRITY  OTHER            Toggling z-axis delay in CM shows the same value
1049956 ALLEGRO_EDITOR DATABASE         BUG:dbdoctor deletes fillets as design is migrated from old version
5 u  z6 n1 q9 D' ]9 R1 M: ]7 G1050408 APD            DXF_IF           Symbol has 45 degrees rotation  in mcm but DXF doesn縯.
8 M% x4 m2 w3 @) Y1050483 ALLEGRO_EDITOR DRC_CONSTR       DRC has been waived but after updated DRC system generated a new DRC.
* s' c0 J! s& }4 C8 e* Q* G4 ^/ {1050918 ALLEGRO_EDITOR MANUFACT         Testprep Automatic generate testpoints with wrong padstack Itype in SPB165S026.
1051588 ALLEGRO_EDITOR PAD_EDITOR       Pad_Designer library drill report omits some drill holes
1052005 SIG_INTEGRITY  OTHER            Huge difference in Z-Axis delay with the latest hotfix for 16.5 that did not exist in older ISR's of 16.5.
1052045 ALLEGRO_EDITOR OTHER            Bug - Thermal relief connects not sustaining 15 degrees component spin in version 16.5 unlike v16.3
1052449 CONCEPT_HDL    COPY_PROJECT     Copy Project does not update all relative paths in the cpm file
* Q8 W7 k4 P% A- J1052600 ALLEGRO_EDITOR SHAPE            Adding a specific cline causing shape errors
1052753 ALLEGRO_EDITOR DRC_CONSTR       Allegro showing soldermask drc only when the symbol is rotated.
1054235 ALLEGRO_EDITOR PLACEMENT        Cannot place alt_symbols for mechanical parts.
4 `) U3 Q. ]. \1054269 ALLEGRO_EDITOR MANUFACT         Backdrill Setup and Analysis crashes on attached design
1054351 ALLEGRO_EDITOR SHAPE            Shape voiding fails for board having diffpairs with arcs
2 V4 I, U# ]7 \. o* h9 }6 x1054456 ALLEGRO_EDITOR MENTOR           mbs2lib incorrectly translates refdes label
1055273 ALLEGRO_EDITOR INTERFACES       DXF exported from Allegro has an offset in pad location for Y- direction.
1055328 CONCEPT_HDL    COPY_PROJECT     Project Manager - Project Copy
1055481 APD            SHAPE            keepout does not clear shape unless it's picked up and dropped down
1055729 CIS            GEN_BOM          Standard CIS BOM per page is not working correctly with option  Process Selection
1056418 ALLEGRO_EDITOR OTHER            PDF exports the blank text markers whether or not the markers are visible.
1056579 CAPTURE        OTHER            Ability to define custom variables for titleblocks that update for specific variant views
1057003 ALLEGRO_EDITOR SHAPE            Z-copy to create RKI does not follow board outline
1057976 ALLEGRO_EDITOR DRC_CONSTR       No Same net Spacing DRC on attached design.
1058002 SIG_INTEGRITY  SIMULATION       Incorrect Xtalk sim netlist was created.
1058364 ALLEGRO_EDITOR SKILL            axlTransformObject() is moving refdes text when only symbol pin is selected for move
1058940 ALLEGRO_EDITOR INTERFACES       IDF(PTC) out command output wrong angle value
' Z) g2 q7 I0 b( S: r* G! Y1059037 CIS            PLACE_DATABASE_P What enables the Refresh symbol libs option under hte update menu in CIS explorer
- O4 b" F& W; n) H( R4 i8 s1059389 ALLEGRO_EDITOR MANUFACT         about back drill analisys report
1 n! ~* E/ ?0 F# D% C1 P* q1059901 CONCEPT_HDL    CORE             Global Property Change and <<OCC_DELETED>> property value.
1060428 ADW            DESIGN_INIT      ADW Flow Manager Copy Project fails to complete
1060589 F2B            PACKAGERXL       Packager Fails with ERROR(SPCOPK-1053): Cannot find a ppt part that matches the instance properties.
1060977 F2B            DESIGNSYNC       back annotate in 16.5 does not bring in already placed nets as global nets
  I% B; Z' i' {' {9 l6 H* [) R4 C7 }1061223 CONCEPT_HDL    CHECKPLUS        What determines a passthru pin?
1061424 CONCEPT_HDL    CORE             Customer creates <<OCC_DELETED>> property values.
! h& w$ {( V6 ~; X- i1061572 ALLEGRO_EDITOR INTERACTIV       Shortcut keys wont work after "Edit Text" command is finished.
1061659 ALLEGRO_EDITOR DATABASE         Unable to return drawing origin to 00
: I" r6 t# z. c( [* F: a5 l# I$ f& E1062558 APD            DXF_IF           If set both in X and Y offset DXF only get one and not get absolutely value in 45 degree rotation
" ^  P$ X8 D+ ?' Q0 _5 }8 _0 E* c, \1062982 ALLEGRO_EDITOR MODULES          Module containg partitions has been imported to the main design and cant be refreshed.
) ]6 k3 ?" H& D  s, M4 I1063284 PCB_LIBRARIAN  OTHER            PDV Save As is broken
7 r; Z+ R, g8 E0 ^9 y1063658 ALLEGRO_EDITOR SCHEM_FTB        Allegro Import Logic does not remove library defined diffpairs
1063778 CONCEPT_HDL    CHECKPLUS        The hasSynonyms CheckPlus predicate is not returning true for all global signals.
  U- }) k# x8 T$ m" y+ R1063924 CONCEPT_HDL    CONSTRAINT_MGR   Highlight the net between DE-HDL 16.5 and Constraint Manager.
1064707 CONCEPT_HDL    CHECKPLUS        Rules Checker core dumps on design
1065124 PCB_LIBRARIAN  SETUP            PTF properties cannot be deleted from the setup in PDV
1 K  J% q* N7 a$ ~; q/ d1065618 CONSTRAINT_MGR ANALYSIS         DRCs on board but Constraint Manager shows the columns as green.
1065641 PCB_LIBRARIAN  CORE             PDV symbol editor is crashing when deleting a group using delete or CTRL+X
1 j0 Y  G: G" M8 e9 b1065745 SIP_LAYOUT     DATABASE         The logic assign net command crashes the application
1065860 ALLEGRO_EDITOR REPORTS          Design crashes when running a padstack usage report
1066051 ALLEGRO_EDITOR TESTPREP         Auto Testprep generation creates TP with Testpoint to Component Locatin DRC
  G% o' b+ I/ g2 u9 @, X1066318 CONCEPT_HDL    CREFER           Issue with LOCATION visibility in flattened schematic
9 N6 Q; C* P, j( h, U1067339 CONSTRAINT_MGR ANALYSIS         Relative Propagation Delay analysis in the Partition file seems very inconsitent.
. |8 M/ ]. x2 F! A9 A. d( j1067984 SIP_LAYOUT     OTHER            layer compare batch fails with write protected file
8 S; {" R$ B/ s: c4 x1068425 F2B            DESIGNVARI       Out of memory message in Variant Editor while 縞hange properties� command
1 ?8 R# t" c" |- L' b1068547 ALLEGRO_EDITOR EDIT_ETCH        Outward Fanout is not fanning out this 4 sided part as intended
1068966 SIP_LAYOUT     DRC_CONSTRAINTS  DRC update aborts on this design with  ERROR -3000067
8 {' o" h$ P/ G' {2 L1069215 CAPTURE        DATABASE         Capture Crash on usnig a TCL utltiy to correct design
1069517 SIP_LAYOUT     DIE_EDITOR       change die abstract pins tab default action from delete to modify
1069915 ALLEGRO_EDITOR EDIT_ETCH        Allegro hangs with when doing spread between voids
1070007 ALLEGRO_EDITOR PLOTTING         Export IPF omits drill figure characters for backdrill holes
1071722 SIP_RF         DIEEXPORT        Virtuoso SiP Architect not writing out pins to the .dra needed for LVS flow
' E& W7 p8 @! @1072067 APD            EXTRACT          When expoting using Extracta oblong pads with anyangle are abnormal
1072791 ALLEGRO_EDITOR DATABASE         Database check cannot fix error and keep report the same issues cause artwork cannot export.
' q7 F0 S5 g- a; n4 n" z+ T8 s1072806 CIS            EXPLORE_DATABASE Query tab in CIS explorer doesn't show searh fields in 16.6
1072843 ALLEGRO_EDITOR PLACEMENT        The move command that was present in the right mouse pop up menu during manual placement is missing in 16.5
1072904 SIP_FLOW       SIP_LAYOUT       Probe pins not being mirrored in Die Editor correctly in Chip Down mode.
1073237 SIG_INTEGRITY  GEOMETRY_EXTRACT Some nets has no result at Bus Simulation and Comprehensive simulation.
# C3 M, I; l) L1073445 ALLEGRO_EDITOR GRAPHICS         'infinite cursor graphics fail -ghost copies as you move cursor
" X, z9 g' X8 @  J- N6 E1073464 SCM            SCHGEN           Schgen never completes.
1073587 SIP_LAYOUT     OTHER            axlSpreadsheetSetWorksheet command clears the cells in memory
! b* p* C/ Y, v8 J1073745 CONCEPT_HDL    CORE             Import design fails
( k* d" x2 \# M1073852 ALLEGRO_EDITOR INTERACTIV       While doing a Copy Via use the last 'Copy Origin'
7 l2 t* G. L( R" Z; {1074279 ADW            DSN_MIGRATION    Design Migration fails purge if there are cells with BODY_TYPE
5 J! E- i2 Z1 n4 r+ G* \& }4 [1074791 CONCEPT_HDL    HDLDIRECT        User gets port exists in schematic but not on symbol message even though the port does not exist
1075135 ALLEGRO_EDITOR DRAFTING         Ability to edit dimension text block in Instance Parameter
1075151 ALLEGRO_EDITOR SHAPE            Cannot change global shape parameter back to thermal width oversize after having used fixed thermal
* n; `* ]: h. c# d1075256 ALLEGRO_EDITOR OTHER            Import > IPF in 16.5 is dropping data.
1075853 ALLEGRO_EDITOR REPORTS          please add "PART_NAME" at Extract UI
& K" v8 t) F+ z3 ^8 c: z1075934 ALLEGRO_EDITOR DRAFTING         Able to Changing Dimension Text Block
1075955 CAPTURE        SCHEMATIC_EDITOR ZOOM in 16.6  using key "I" on keyboard in not centered on mouse pointer
% H" d5 s4 I$ J. X8 a) ]1075964 ALLEGRO_EDITOR SHAPE            Shape voiding is not consistent in conjunction with odd angle and arc traces
1076086 SIP_LAYOUT     IMPORT_DATA      missing wirebond after import SPD2
) y( b; Z0 H6 [6 a' X4 q/ v# @1076202 ALLEGRO_EDITOR EDIT_ETCH        Allegro add connect causing crash after Hotfix
1076205 CAPTURE        PRINT/PLOT/OUTPU : Printing of User Assigned RefDes
1076536 ALLEGRO_EDITOR DRC_CONSTR       Embedded component which protrude out toward Top do not create DRC with Place Keepout on Top
1076538 CONCEPT_HDL    CORE             Property visibility changes in attribute form not updated in schematic canvas.
7 d6 ~* |$ c# T/ l1076655 APD            DXF_IF           Dxf does not get offset value if die symbol padstack has offset value
& S! [* g0 V5 V' s' T$ Z1076846 ALLEGRO_EDITOR EDIT_ETCH        Grid snapping broken after slide in 16.6
1 }, F' U" k/ S1 G1076891 ALLEGRO_EDITOR INTERACTIV       Symbol rotation not displayed correctly when defined as a funckey
& A9 y. Z( j5 Z5 P" h1076909 ALLEGRO_EDITOR DRC_CONSTR       Allegro crashes while placing modules from database
4 X8 }% H' l. k9 n1077084 CAPTURE        NETGROUPS        Crash on selecting bus when Enable Global ITC is unset
1077169 APD            SHAPE            Shape > Check is producing bogus results.
8 F: ?% e- g) w( R1077572 ALLEGRO_EDITOR DATABASE         Mechanical symbol created with 16.6 cannot be placed on board.
" |4 U& l+ S* v' |  I0 `3 @* e1077879 ALLEGRO_EDITOR SKILL            Allegro Skill axlDBCreateFilmRec fails when 15th argument missing "draw hole only" for the first tim
# m7 F# y, V, b; [1078380 SCM            OTHER            Custom template works in Windows but not Linux
1078497 ALLEGRO_EDITOR INTERFACES       Import DXF does not seem to work correctly.
1078682 ALLEGRO_EDITOR DRC_CONSTR       Unaccetable slowness with Slide
; O8 ^; `& s3 {$ o5 p, r* J1079082 ALLEGRO_EDITOR PLACEMENT        Swap components, gives error SPMHGE-616, when symbols instead of components are selected for swapping
1079533 ALLEGRO_EDITOR PLACEMENT        Swapping components in 16.6 results in Error "E-(SPMHGE-616): Symbol and layer embedding requirements do not match"
1079937 CAPTURE        SCHEMATIC_EDITOR ZOOM in 16.6 is non uniform on text
* p: ?# Q5 s' b4 O/ U- u1082582 ALLEGRO_EDITOR GRAPHICS         Allegro hangs on a given testcase using the MMB zoom control
( t9 h: I/ c: W' n" i/ A( o& F1082981 ALLEGRO_EDITOR SKILL            Allegro crash while change the new symbol type as mechanical.
' R4 |  n5 c  W* u0 n! }  ^4 k6 m1083230 SIP_LAYOUT     SHAPE            Shape fill in 16.6 releaase not fillilng shapes as good as it did in the 16.5 release.
7 j9 @4 k9 D+ a+ [7 h0 H

rx_78gp02a

看到了几个16.6的“特点“原来是BUG

pcfg

rx_78gp02a 发表于 2012-12-17 21:16
/ \8 n  o9 Z4 \$ a9 p看到了几个16.6的“特点“原来是BUG

4 u5 m1 i9 W( m是的

jinshan010

有下载地址了吗？
- F- r. p) e0 L# F& l3 {. h) C+ N

MentorUser

Look & Thanks

mengshang

的确，Latest Release: 16.6-S001
Your Version: 16.5-S034
期待着下载呢

micdot

8 f% k, `# o; E( H7 e- w
现在提供下载地址：http://www.orcad.nl/patches/Hotfix_SPB16.60.001_wint_1of1.exe
目前，我已经下载完毕，安装后确认可以正常使用！

rx_78gp02a

第一个HOTFIX就有400多M，以后的会越来越大，这个怎么玩啊？