Thunderbolt 测试

stupid · 发表于 2012-7-30 13:38

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Thunderbolt (previously called Light Peak) is a new peripheral-connection technology, developed by Intel with collaboration from Apple, that combines data, video, audio, and power in a single serial connection. Based on the PCI Express and DisplayPort architectures, Thunderbolt allows for high-speed connection of peripherals such as hard drives, RAID arrays, video-capture solutions, and network inteRFaces, and it can transmit high-definition video using the DisplayPort protocol. Each Thunderbolt port also provides up to 12 watts of power to connected peripherals.

Introduced more than a year ago, Thunderbolt features two bi-directional 10.3125 Gbps links on a single electrical or optical cable using the same connector as a Mini DisplayPort. The main advantage is a significant performance boost over FireWire 800, USB 3.0 or even eSATA, as shown in Figure 1. It provides sufficient bandwidth to daisy-chain multiple high-speed devices without using a hub or a switch and offers low latency for highly accurate time synchronization.

Figure 1 – Thunderbolt significantly speeds up data transfer rates for peripheral devices.

Unlike industry standards that often involve long-drawn out committee sessions, Thunderbolt was the result of a close-knit effort by Intel and Apple along with a number of partner companies from across the industry.  At this point, Thunderbolt is more of an interconnect technology that incorporates elements of the PCIe and DisplayPort than a true standard.  But it doesn’t appear that the lack of formal standards body will keep Thunderbolt from gaining widespread adoption.

Thunderbolt ports first appeared on Apple’s Macintosh computers and are just now showing up on motherboards from MSI, ASUS and others. By the end of 2012, Intel expects about 100 peripherals based on Thunderbolt connector technology will be commercially available, with the number climbing steadily throughout 2013.  Thunderbolt is also being integrated on third-generation Intel Core processors code-name Ivy Bridge, reducing the need for a discrete chip to implement the technology.

From a design perspective, Thunderbolt offers the freedom to innovate new PC products and configurations. It gives engineers the ability to move high-performance expansion technologies outside the PC box or downsize laptops without sacrificing I/O performance.  It can also co-exist with other I/O technologies through the use of PCI Express adapters and drivers.

For Thunderbolt to truly gain broad adoption, a strong ecosystem with full test and measurement support will be an important ingredient.  Plugfests along with verification and compliance testing will help ensure that products incorporating Thunderbolt technology deliver expected performance and smoothly interoperate with each other.  Let’s take a closer look at what’s involved with testing Thunderbolt designs.

Specification overview
For designers used to working with high-speed serial buses, much of what’s in Thunderbolt will look familiar. Thunderbolt signaling is a dual NRZ (64/66b encoded) at 10.3125 Gbps (same as SFP+) with two differential Tx pairs and two differential Rx pairs.  As the overview of Thunderbolt electrical validation shown in Figure 2 illustrates, Thunderbolt relies heavily on DisplayPort testing. This is in part due to the use of the Mini DisplayPort connector and the native support for downstream DisplayPort devices as well as dual mode DisplayPort (DP++) for driving single-link HDMI and DVI signals Storage drive interfaces will require conformance to other technologies such as SATA. This means that if you are preparing a lab for Thunderbolt testing you should plan on being prepared to test a variety of other high-speed serial data standards as well.

Figure 2. Thunderbolt electrical validation ecosystem

Since the Thunderbolt spec is currently in transition from a 0.6 version it should be noted that the current measurement list shown in Table 1 is likely to grow or change as the specification reaches its final 1.0 version. Today this table constitutes the full extent of the physical layer validation requirements.

Table 1. Current Thunderbolt measurement summary

On the Tx side, the specification calls for three patterns. These include 8 1s and 8 0s on a low frequency square wave, PRBS-9 and PRBS-31 patterns. The channel measurements will be performed with a TDNA solution using methodologies first developed for SATA that involve return loss measurements into active transmitters. For receiver testing, most tests will be BERT based and represent a fairly light level of signal impairment. For instance, the ISI (DDJ) contributions called for with Thunderbolt are a fraction of that used in DisplayPort HBR2. The resulting eye diagram is very open and easy to generate. On the other hand, crosstalk is expected to be a bigger issue with the higher data rate. Real world testing of crosstalk involves receiver BER verification while actively sending data out the transmitter thus accounting for near-end crosstalk. The spec also calls for receiver compliance testing to be performed at 3, 4.8 and 100 MHz.

With its fast data rates Thunderbolt will present a number of test and measurement challenges, including fixture effects and the need to isolate crosstalk.

The effect of fixtures on measurements is shown in Figure 3. When the fixture effects are removed from measurements, the impact is a 35 mV gain in eye height. This gain corresponds to additional margin, which can be beneficial for very tight characterization. There is also a corresponding decrease in jitter from 19 psec to 17 psec realized by de-embedding the fixture losses. This means that for Thunderbolt testing, it will be very important to understand what fixtures are being used, how to de-embed their effects and apply the de-embed effects into the oscilloscope.

Figure 3. Thunderbolt fixture de-embed results on Tektronix DPOJET.

With two differential lanes and the high data rate, ISI or crosstalk is certain to make an appearance in Thunderbolt measurement results.  Additionally, with advances in interconnect and board layout technology, one of the areas of greatest focus is reducing insertion loss and signal-to-crosstalk ratio.  Further, depending on how the signal is generated (native PHY or a muxed PHY) significant sub-rate hARMonics will be present.  This means that for effective debug it will be very important to have jitter analysis tools that can properly separate and classify the jitter components of a signal, including those stemming from crosstalk.

The implications of complex channel interaction can be observed and indentified by examining the type and amount of bounded uncorrelated jitter (BUJ). In the past this has appeared as random jitter (RJ), in a Gaussian shape, in jitter analysis performed by an oscilloscope.  BUJ is a key indicator of the less than random coupling of energy from adjacent signaling lanes. This is un-correlated to the data pattern since its coming from neighboring lines. Therefore, BUJ is not Gaussian in nature and should not but identified as RJ but have its own classification under deterministic jitter (DJ).
Oscilloscopes with BUJ-aware jitter analysis algorithms perform an additional step in jitter analysis after separation of data-dependent jitter (DDJ) and periodic jitter (PJ) to separate BUJ from RJ as shown in Figure 4.  The capability provides better quantification of total jitter (TJ) and helps to isolate sources of ISI or crosstalk.

Figure 4. BUJ-aware jitter analysis and the resulting jitter decomposition map

To illustrate the value of this approach, consider Figure 5 showing measurements taken on a Thunderbolt device. The results shown in the tables provide a side-by-side comparison of BUJ decomposition vs. legacy decomposition. With the BUJ decomposition algorithm, TJ@BER is reported at 10.105 ps. With the legacy approach, TJ@BER is more pessimistic at 11.159 ps. The reason for the difference is that on the left the NPJ number is present and correctly placed under the deterministic tree, leading to a lower TJ@BER number. On the right, there is no representation of NPJ, driving up RJ and thus TJ@BER.

Figure 5 – BUJ decomposition provides more accurate TJ reporting compared to legacy jitter decomposition.

Transmitter testing

If one considers the complexity of DisplayPort HBR2 (5.4 Gbps) testing, it’s a pleasant surprise that Thunderbolt validation is roughly six times easier to perform. The reason for this relates to the use of active cable designs in Thunderbolt which eliminates the need for the complex handshakes and startup link optimization that lower speed passive cable-based counterparts, like DisplayPort, need to contend with.

Today, for compliance testing in accordance with draft spec 0.6, Thunderbolt calls for a basic set of 10 core physical layer validation tests as shown in Table 1. These are performed at one bit-rate (10.3125Gbpsec) and three patterns with and without SSC. This testing presently takes roughly five minutes to conduct using a 16 GHz real-time oscilloscope. Figure 6 below shows an automated Thunderbolt transmitter test tool for performing compliance to the 0.6 specification.

Figure 6. Thunderbolt Tx automation software simplifies measurement setup.

It is important to remember that Thunderbolt has two Tx pairs and two Rx pairs. When analyzing the Tx lines, it’s helpful to have instrumentation with sufficient performance to analyze these lanes at the same time. A 4-channel oscilloscope with at least 20 GHz bandwidth per channel makes it possible to put all the lines on the instrument and to analyze both differential channel pairs in a single snapshot. Figure 7 illustrates the use of a jitter and timing analysis toolset to perform the full set of Thunderbolt AC parametric and jitter measurements while in a debug mode with customized settings. Documenting test results is made easier with automated report generation as shown in Figure 8.

Figure 7. Full set of Thunderbolt Tx measurements across two differential pairs.

Figure 8. Thunderbolt Tx Test Report showing results from both lanes.

Receiver testing
On the receiver side, the overall testing story is encouraging. The impaired receiver signal, generated using a 12.5 Gbps or greater Tektronix BERTScope, uses an open eye, unlike comparable eyes performed in SAS or PCIe.  Also the ISI (DDJ) contributions used for Thunderbolt are a fraction of that used in DisplayPort HBR2. This greatly simplifies verification and compliance testing. With Thunderbolt, there is no loopback provision so interaction with onboard error detectors will be essential to query out the error statistics.

Thunderbolt receiver test protocol uses an impaired PRBS31 test pattern with sinusoidal and AC common mode impairments ranging from 3 to 100MHz.  These impaired signals are applied for 600 seconds or roughly 10 minutes per sinusoidal jitter frequency, and no errors are allowed during this interval.

As with most high-speed serial standards, connectivity to the signal under test is critical. Figure 9 shows a “Digital Port Micro” controller and plug fixture which attaches to the lower speed serial UART and is used to either interact with the receiver’s error counters, or to instruct a transmitter to broadcast a specific pattern type. The unit shown will support up to four high-speed differential pairs.  It also includes eight low-speed signal lines for control and power testing.

Figure 9. Thunderbolt test fixture or “Digital Port Micro” controller

Depending on the testing needs of the end users, there will be other Thunderbolt fixtures required to either break out the electrical signals from a Tx host or a DUT.  Additionally receptacle fixtures will be needed for cable testing.

In terms of test instrument requirements, Thunderbolt silicon designers will need a 30+ GHz real time oscilloscope for very accurate Tx characterization and Rx calibration along with a 12.5 Gb BERT, such as the Tektronix BERTScope for stimulus and error detector for receiver and cable testing.  For system compliance (e.g. cards, cables, transceivers) testing, a minimum 16 GHz real-time oscilloscope can be used, although a 20 GHz unit is the better choice, and should be coupled with a 12.5 Gb BERT.

Summary
Developed by industry heavyweights Intel and Apple, Thunderbolt packs a serious punch with impressive 10G speed and outstanding versatility. And with industry support lining up, Thunderbolt will enjoy strong tailwinds that will lead to lower manufacturing costs.  Although it may never be as ubiquitous as USB, Thunderbolt ports are likely to be widely available on everything from desktop and laptop computers to external hard drives, RAID arrays and monitors.

For designers, verification and compliance testing of Thunderbolt designs will present a number of challenges related to the use of two 10 Gbps differential lanes.  These include the requirement to de-embed the fixture from measurement results to ensure adequate margin and the need for tools that can properly isolate crosstalk-induced jitter from other jitter sources. Further, since the final Thunderbolt specification has not yet been published, designers should expect changes and additions to the measurement list.

The good news is that compared to serial data standards such as DisplayPort and SAS, Thunderbolt significantly simplifies transmitter, channel and receiver testing.  What’s more, the test and measurement industry is ahead of the curve with test solutions and fixtures already available for testing Thunderbolt devices.

About the Author
Chris Loberg is a senior technical marketing manager at Tektronix responsible for oscilloscopes in the Americas Region. Chris has held various positions with Tektronix during his more than 19 years with the company, including marketing manager for Tektronix’ Optical Business Unit. His extensive background in technology marketing includes positions with Grass Valley Group and IBM. He earned an MBA in Marketing from San Jose State University.

gavinhuang · 发表于 2012-7-31 18:47

看起来挺高端的，只知道thunderbolt 还是挺新的东西，功能很强大。目前看不懂，不过也谢谢分享。

kellphon · 发表于 2012-8-1 13:50

英特尔和苹果联合开发的啊，关注很久了，但貌似只有苹果用这个高速接口。

stupid · 发表于 2012-8-1 14:07

kellphon 发表于 2012-8-1 13:50 # b _: k; S8 L2 _0 H0 J
英特尔和苹果联合开发的啊，关注很久了，但貌似只有苹果用这个高速接口。

肯定不是，用这个接口最激进的是骚尼，已经有光版本啦。详见本坛。

kellphon · 发表于 2012-8-1 16:50

stupid 发表于 2012-8-1 14:07
- O9 V8 e* q; @+ M, A" @" o* ]肯定不是，用这个接口最激进的是骚尼，已经有光版本啦。详见本坛。

虽然骚尼很想用这个接口，但是这个接口的开发鼻祖绝对不是骚尼哦。
我就曾见过公司内部的说明文件，也有百度百科为证哦，嘻嘻，http://baike.baidu.com/view/292863.htm。

tonytp · 发表于 2018-7-27 13:31

非常和

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