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Hotfix中只需要安装最新的版本即可。1 G+ N' Y1 H; s/ W/ G0 B
Hotfix024对以下项目做了修正：# x0 F, a ]$ h$ k C+ @7 a% P; B p
DATE: 06-20-2012 HOTFIX VERSION: 0246 x: P" i, d/ a3 a! x8 ^
===================================================================================================================================9 S6 R, @" e* A6 r+ A) x
CCRID PRODUCT PRODUCTLEVEL2 TITLE
( z1 i. z2 w- F5 A) r! N, l===================================================================================================================================, M/ o6 r) w9 B1 O8 r( ?7 j
982824 ALLEGRO_EDITOR OTHER Import placement fails with a zero length log file.
3 R% U$ q0 Q: u5 N, ?+ A1006437 SIP_LAYOUT BGA_EDITOR SCM not loading the die if dies refdes and LFnames are changed8 n+ | m) s% Q% r9 E
1011040 FSP PROCESS Feature to avoid connectivity between fixed voltage Output and variable voltage Input! T( ]0 N$ h% J- ~3 B. }) C, U% {
1012985 ALLEGRO_EDITOR DATABASE Allegro crashes multiple times a day% }2 E. [) F+ t& K1 S
1013644 ALLEGRO_EDITOR SHAPE Sliding trace with oops creates a duplicate shape islands2 E; S" J0 e3 |, R) Q$ C
1014351 ALLEGRO_EDITOR OTHER Whenever we open a file (brd, dra) in PCB Editor with an OrCAD PCB Designer license,we get a warning SPMH0D-34
) t- z7 p n# i3 N' g3 P! {1014893 CONSTRAINT_MGR OTHER With CM open layout is extremely slow and Allegro crashes very frequently
& `2 S! k/ x$ D4 T: [7 b1015210 ALLEGRO_EDITOR DRC_CONSTR Deleting Via from an array casues DRC errors: r& J0 G" S5 U# O3 W5 [& \. u% G
1016546 CONCEPT_HDL CONSTRAINT_MGR Wrong value of NET_PYSICAL _SPACING_TYPE in Attribute form
/ j7 q }; G8 R# ]% X1016932 RF_PCB DISCRETE_LIBX_2A Incorrect Symbol Pin Numbers after import into ADS& I! M# A6 l7 U8 M- d' j, Z
1017332 APD VIA_STRUCTURE Refreshing Via Structures results in shorting to power plane.
3 `3 \7 P/ ?2 j! l4 t: ?1017931 ALLEGRO_EDITOR OTHER IPF import fails with error-IPF error : Illegal pen number4 ?0 O& W' d1 |' x
1018413 F2B PACKAGERXL Export Physical producing different results depending on how it is launched
$ _8 Z; z A/ h+ v4 x( W1018435 APD OTHER Oblong pads in Sip are not displayed correctly in the Stream_out .sf file.
( S+ Y( S z- T: o# `2 A* A1018936 ALLEGRO_EDITOR OTHER unexpexted DRC eror
- T1 J7 ~: j/ e/ ~1018978 ALLEGRO_EDITOR DRC_CONSTR Update DRC changes DRC without any change in design
9 y6 V4 e+ T! l- l7 Q2 ~' Y1019303 CONCEPT_HDL INFRA DEHDL custom outport displays error
4 u! }* O& d8 M& [% B( d# y- n1019913 ALLEGRO_EDITOR DATABASE BUG:Bottom pins are also shown in DXF export8 `. Z, R% s3 M% T1 ~8 A3 c# n
1019955 ALLEGRO_EDITOR SKILL axlRegionCreate and axlRegionAdd do not work in a symbol file.
. g, _5 b! ~, B5 p8 F( c1020749 ALLEGRO_EDITOR DATABASE 16.2 Parts not updating when opened in a 16.5 database9 j4 ]& h, g3 Q( {* N1 n ^# ?
1020780 APD COLOR APD crash on assigning color to net using Color192
8 b2 g# I* Q1 x; H' g! W0 B( W1021033 CONCEPT_HDL CONSTRAINT_MGR Cleared ecsets in 16.3 reappears as mapping errors without ecset names after uprev to 16.5 |
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发表于 2012-6-23 10:23
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