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module glitch(
- u1 d0 R0 j3 D: v; `3 I input clk,
5 o0 O0 ^8 y; \# f input rst_n,1 {9 K2 M8 |' J0 ?
input data,
! g% l, x* [: ^( C4 p output reg value_d);
: Z7 d# m1 C6 Y7 t6 l7 `4 \
A w c* L% h# i8 h" D, C/ h" Zreg data_t0 ;0 x. o- ^0 b3 h7 {- W6 _& h! ~
7 p1 Z0 ~" @9 x+ q
always @(posedge clk or negedge rst_n) begin; `* P2 B+ V2 g& C) N n& t K
if(!rst_n) begin
1 |0 G; w" e* I. F9 e7 u data_t0 <= 1'b0;
& x p6 c! A. P7 S value_d <= 1'b0;8 a8 E N# {! Z: {# [7 z
end
: {! G( k* S! K U/ F$ n else begin
" [3 m- o- L& ~2 n; F- V data_t0 <= data ;7 v# M$ o2 I0 M/ h
value_d <= data_t0;) q5 Z/ E) C5 U: F: }1 _
end
. i) z* v; T; B3 ~- ^end, H$ d+ s$ v/ d& E8 w5 k* `" G
2 F3 U' ?2 ?7 M; \
endmodule |
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