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DATE: 02-17-2012 HOTFIX VERSION: 0166 q0 T7 Z% |" u& k4 O( m( E9 _# f4 M
===================================================================================================================================6 d+ M, I# V5 A; {; `; v5 O7 e
CCRID PRODUCT PRODUCTLEVEL2 TITLE- ^& _7 ?: Z/ N. @" h
===================================================================================================================================1 N" h* ~7 f+ v) ~! W
840105 PCB_LIBRARIAN USABILITY PTF subtype is getting changed when Save As option is used in PDV
) |. ^4 F: \* q$ Y; x1 a873075 Pspice PROBE Decibel of FFT results are incorrect.
& ^; H4 i5 ]1 D: v938744 ADW COMPONENT_BROWSE Need ability to customize shopping cart columns to include any Part property
* a9 Q, W$ q* D* X! y1 u* a R7 N943003 SCM REPORTS The dsreportgen command fails with network located project
: _/ s K9 O8 C7 @ Q* r961530 allegro_EDITOR INTERACTIV The problem of Display measure command
1 H% ~$ d' G. q( ?( F8 |( L, {; l962157 concept_HDL CORE Where is the setting for enabling the Enable PSpice Simulator menu?* ?8 ^1 I$ \0 q0 D
962206 CONSTRAINT_MGR CONCEPT_HDL Import physical not passing all constraints from the board to frontend q5 }5 s1 C) m
968205 PSPICE DEHDL_NETLISTER Change SPLIT_INST property to PSICE_SPLIT_INST for Quad Switch type of design.
8 J D B/ P& q1 g, N968509 PCB_LIBRARIAN METADATA Incorrect pinlist.txt was generated if DIFF_PAIR_PINS_POS/NEG was set.) q. P6 R5 s# ~7 c& U
969450 LAYOUT TRANSLATORS orcad Layout to Allegro Translator crashes
* L# U* w# B9 ? }969997 CONSTRAINT_MGR CONCEPT_HDL ERROR(SPCOPK-1053): Cannot find a ppt part that matches the instance pro~( ]+ \. q* W: }3 o3 L4 T7 T0 [7 z+ n
971193 CONSTRAINT_MGR UI_FORMS Copy and pasting a formula causes the application to crash on windows.( p2 k+ r) h- t6 `; o
971601 CONSTRAINT_MGR CONCEPT_HDL ERROR(SPCOPK-1053) and WARNING(SPCODD-66) because of directory structure1 T0 J6 r" q k& D
973398 CONCEPT_HDL OTHER It should be not packaged with error while working the packaging process if the design has a ERROR, B: u2 u* {! C4 w7 m5 _, J0 U
973859 PSPICE ENCRYPTION Pspice crashes with encrypted model) R7 h8 O' J: Z( B' C2 E: u
973938 PCB_LIBRARIAN VERIFICATION pc.db is missing
" Z# b! E0 Z9 }2 M$ J: C# M7 f974540 CONCEPT_HDL CORE Graphics updates are real slow ?) U5 ?$ [# W$ Y# B; K- N
974791 F2B DESIGNVARI Variants are not back-annotating to schematic and turning to ?6 t/ I \3 y3 Q( ?8 C/ @
974818 ALLEGRO_EDITOR NC Backdrilling produces 0 plunges yet no errors reported.5 \# [! W/ f( H7 D: s
974945 ALLEGRO_EDITOR skill Why is axlPolyOperation is giving different result and not working5 L$ q) d @: b% F! Y
974946 MODEL_INTEGRIT TRANSLATION ibis2signoise returns the error - Delay measurement fixture must contain V for ECL technology( d; i' [$ o( D. R
975396 CONCEPT_HDL CONSTRAINT_MGR Constraints are dropped after migrating from 16.3 to 16.5
3 I7 t# Y7 J1 p3 A2 i1 V975633 ALLEGRO_EDITOR GRAPHICS 'dynamic_layer_visibility' option in 3D Viewer when checked or unchecked should not change (until next change)1 M, I$ p/ ]+ G5 }) D2 k
975720 ALLEGRO_EDITOR DRAFTING Datum dimension lines not adjusting to text move, t* y* c' x7 Z/ |; S
975745 ALLEGRO_EDITOR SKILL cdsServIpc different 16.2 vs 16.5 when Allegro exits
- z$ I, I7 F- [, j" N976013 CONCEPT_HDL INFRA Power pin connection of FPGA symbol is missing in netlist.3 ^/ Z% s- `/ u2 Z' p1 m* b. k7 M
976058 CONCEPT_HDL COPY_PROJECT SCM Copy project does not create the con and dcf files in tbl_1 views
/ g$ u5 Z# D7 l$ H I976073 CONCEPT_HDL COPY_PROJECT All the constraint data is lost in the SCM copied design
6 m5 x+ R h7 l3 c/ ^# d: L976160 CONCEPT_HDL CREFER Cref fails due to some Caeviews error in the design j7 x# b$ j) I- _
976204 ALLEGRO_EDITOR DRC_CONSTR Application falsely reporting Mechanical Pin Antipad to Shape Spacing DRC7 U% j8 x$ L9 k1 [3 Q
976448 F2B PACKAGERXL ERROR(SPCOPK-1069): Invalid POWER_GROUP property value+ q; H! E3 e$ N, @/ v6 j% h0 a% P
976521 ALLEGRO_EDITOR DRC_CONSTR multi-thread update DRC causes the application to crash
; h; z( D8 b" c976838 SIG_INTEGRITY OTHER Unable to create XNET for highlighted nets on attached database even after assigning proper Signal Models.
Q/ B5 s( G# e' N$ i5 Z9 v977517 F2B PACKAGERXL Export physical fails after update to 16.5 from 16.33 r. s% k" ~, n- `6 H0 @
977902 ALLEGRO_EDITOR DATABASE generate module is crashing allegro: |8 \9 ] H& }( [6 x7 |1 ~
978652 ALLEGRO_EDITOR pads_IN PADS_IN fails with ERROR: Finished with errors.
6 b/ D# U/ h$ s978744 APD DEGASSING Some shapes will not DeGas on this design, W6 K5 y2 K5 \
979940 SIP_LAYOUT OTHER SiP Layout Leadframe autobonding with profile selection
1 W& q" ]5 {% Y0 g2 R981699 CAPTURE HELP Start Page still shows Hotfix 14 after installing Hotfix 15
+ `, |1 t) \* {+ j; ~
# Z8 m G$ K, h- I) RDATE: 02-03-2012 HOTFIX VERSION: 015
5 B' q1 ] N8 Q1 y& K===================================================================================================================================
) ^+ O. ?2 o$ b( z# F1 n8 Y1 N5 l& iCCRID PRODUCT PRODUCTLEVEL2 TITLE1 \2 p: ~: T" A0 @, U
===================================================================================================================================
0 F2 X9 D" Q& Z, _: R. M871567 CONSTRAINT_MGR SCHEM_FTB Ability to filter out Single Node Nets from Constraint Manager
! d' h' _, d G- j% b* r921436 ALLEGRO_EDITOR MANUFACT Change in 'decimal place' for new dimension changes the already placed dimension2 }' S! ^ G3 ]( y0 }0 _( q
941433 CONCEPT_HDL COPY_PROJECT 16.5 Copy Project should warn if trying to copy a 16.3 design
6 H. e5 L- S! r! p# d954375 ALLEGRO_EDITOR MANUFACT Change dimension accuracy for few instaces of associative dimensioning% T9 v% v$ c& S: e6 K2 j5 X
961646 PDN_ANALYSIS EMVIEWER EMViewer Help > About shows wrong version" }0 r0 T1 S$ Y2 |/ A0 V, ?
964912 CONCEPT_HDL COPY_PROJECT ASA project crash after using copy project3 N1 j3 s/ I/ G) t6 U3 o, h) V& p
967223 ALLEGRO_EDITOR MANUFACT Bug:Oval slots orientation in one direction only
' i& k5 H. n4 F/ N968865 SIP_LAYOUT DIE_ABSTRACT_IF load of die abstract fails due to differences between component and symbol$ ?( H7 M c, h! L
969485 ALLEGRO_EDITOR SHAPE Shape does not update correctly in 16.5
" J' l p! r8 }% D! B5 X- b* p! n4 |2 H970331 CONSTRAINT_MGR ANALYSIS Impedance worksheet shows a zero value for impedance9 o/ O. S3 D$ o' c
970600 SIP_LAYOUT SYMB_EDIT_APPMOD Option in Die Editor to be able to "physically swap" pins
, F7 T5 M! J# g* `970910 F2B PACKAGERXL Our customer has problem with pin color after pxl 16.5.# S& O8 R5 u0 r+ e' r
970970 SPECCTRA FANOUT Fanout Vias is placed far away from decaps and does not change the Fanout length even when max_length is reduced.# O5 b- x0 x( Q) q
970985 SIP_LAYOUT OTHER Importing a .spd2 database file using NA2 will cause the APD/SiP tool crash
8 i! @9 }$ E3 V" M971757 CONCEPT_HDL INFRA Crash while Saving/Packaging the Design5 l1 _, J1 U8 y' H, w7 c
971923 ALLEGRO_EDITOR MANUFACT Allow to change decimal accuracy for dimension instances, A- |: v' G1 p$ V) b! @
972568 CONSTRAINT_MGR UI_FORMS Tools >Excel missing from CM
( ?- V) C; M/ U4 p% F. U2 ]: h. l972821 CONSTRAINT_MGR CONCEPT_HDL connectivity server warning: Unable to add property WEIGHT" h# L9 m& \' D5 D, b. U8 m
973185 SCM CONSTRAINT_MGR ASA2 block not seeing all instances in a package.: o' Z+ o* ^" U. O
973211 ALLEGRO_EDITOR INTERFACES IDX Object Type Change not recognized, \/ v; w& w- y! e: ^; }& l
973214 ALLEGRO_EDITOR INTERFACES IDX import package keepout height value change assigns incorrect value: d" A' a# W" p; S
973384 CONCEPT_HDL CHECKPLUS The multiple SIG_NAME has to be occurred an ERROR at the SPB16.5.1 Q! e2 t( k- [+ v
973514 SIG_INTEGRITY OTHER Mapping error when Ecset is updated to constraint manager from extracted net9 Q) F5 N5 X6 L) V# Z1 \
973950 ALLEGRO_EDITOR SHAPE Update to smooth crashes application
* m$ W7 {' g' Q! A* g974533 SIP_LAYOUT OTHER Crashes in Edit > Die Properties and obviously has a setup problem.
; ?/ Q3 X6 G/ T- t5 M974809 ALLEGRO_EDITOR SKILL argument available for hiding a property with function axlDBCreatePropDictEntry is not working; N; |# `- J r4 n3 S
976179 INSTALLATION ISR Installation of ISR S014 to 16.5 on windows is breaking the documentation index, v; D+ `7 ^3 d, A
- r: e O) m+ @9 e& h: M! c6 TDATE: 01-20-2012 HOTFIX VERSION: 0145 G) V) }0 |& \1 h* o
===================================================================================================================================1 d+ k u, E/ q! z$ f. _
CCRID PRODUCT PRODUCTLEVEL2 TITLE
1 y& F0 F4 g/ c; q# w2 K' \# E# \* X" z===================================================================================================================================- u( }$ Z8 R) v# h
733285 PSPICE SIMULATOR Enhancement:In server-client installation use existing index file from server! E2 t! g& M) P8 ~7 l: Z7 F* W
941020 SIP_LAYOUT OTHER Soldermask enhancement/ L. I3 u& G/ q$ m, U
946407 CONSTRAINT_MGR TDD When is it safe to open a 16.5 design in 16.3?
' x" V$ r$ g9 U H: r953067 CONCEPT_HDL OTHER Variant Editor "Error/Warning messages" form is unusable
# p x( i, A( c5 @0 K7 W+ w954818 CONCEPT_HDL COMP_BROWSER Replace button turns to Add in component browser when a component replace is done on the schematic
. l) a2 h2 Q0 U9 k: }0 T7 S956450 ALLEGRO_EDITOR DRC_CONSTR Analysis always shows analysis failed in uncoupled length in some diffpairs8 `% P. Z6 ], w
958259 F2B DESIGNSYNC ds.exe crashes on a big design when accessing the design from network drive
3 b" O6 Q8 O) y5 |1 R/ U9 C* w958395 ALLEGRO_EDITOR SHAPE shape voids won't merge
( r$ l: o t: Q R959212 MODEL_INTEGRIT PARSE Attempting to use "Mark qualified" option on DML File results in dmlcheck and Modelsim wanrings.0 M4 {; [, E* E& f
959940 APD AUTOVOID Void all command gets result as no voids being generated.; m! t1 ]$ G& \& K
960252 PCB_LIBRARIAN CORE Splash screen in PDV prevents showing error message, \. C' Y( o$ q" V6 r" N
961634 PDN_ANALYSIS EMVIEWER Cannot launch PDN EMViewer from withing PCB SI! s/ ^7 F5 s7 d* \
961645 PDN_ANALYSIS EMVIEWER Standalone EMViewer will crash when opening any result file in the form of *.emv file./ e5 [' a9 l {) k5 \
961700 ALLEGRO_EDITOR SHAPE dbdoctor reports ERROR(SPMHUT-144): Illegal arc specification( _2 t# `: c+ p) w# y$ J
961733 ALLEGRO_EDITOR SKILL Allegro crashes. Appears to have a memory leak.
4 G1 L0 e( X8 V; n7 Q: D5 |961758 ALLEGRO_EDITOR DRC_CONSTR DFA check produces no DRC when the dfa bounds are not a rectangle.
3 U; F& B: w. U3 Z5 P1 l961887 CONCEPT_HDL CONSTRAINT_MGR Match Group created from ECSet cannot be deleted in the same session of CM
/ l$ \9 W/ f2 t1 @' T962552 APD EDIT_ETCH BUG:APD crashing when we try to slideget information but move works fine4 j. @+ Q! R, l( ]: R
962869 CAPTURE STABILITY Capture crashes after RMB click on rotated parallel wires
& d5 X( s' s- p; t* K* @ Q+ |- o9 C0 f963232 CAPTURE MACRO Macros not being played in Windows7
9 u7 i. p" Z j6 T% g963300 ALLEGRO_EDITOR DATABASE Create > Module crashes in 16.5 but not in 16.3# V& e7 C/ ~2 s1 _5 ~/ d8 N$ C9 U( L
963651 CONSTRAINT_MGR CONCEPT_HDL ECsets are renamed after packaging on linux$ c( J8 p L; A9 [& s g% e1 `) j+ i
963663 CONSTRAINT_MGR ANALYSIS Q- Why the customized worsheet for Diff pair Impedance not analysing at all for this SIP design
) R9 M- c7 k& K. E# {) v% t) h3 m963715 SIG_INTEGRITY OTHER Application only adds the bottom conductor thickness for the via z-axis length
! b! a1 N' Y; C1 r964068 ALLEGRO_EDITOR INTERACTIV Allegro crash when using move alt sym mirror alt sym...
' V% U8 |9 G" G5 y! B" t964267 CIS PART_MANAGER Capture become non-responsive, working on Part Manager and creating CIS BOM, for large designs
, r% L2 @4 Z: ]# Y964597 ADW LRM Issue of LRM license checkout after renewal license by 16.5 (ADW15.5_S23+SPB16.3)" f; W2 j( {+ ^2 Z
966148 APD INTERFACES Character Limit for DIE Files (*.die) Import
- u T! U1 u) h4 @! K" E966416 F2B PACKAGERXL Cannot package this design4 e4 @/ z8 Z3 Y- j% B m
966421 CONCEPT_HDL CORE DEHDL Crash when applying property on components in duplicated blocks: X5 T) k; O4 K4 M# q; X
966693 CONCEPT_HDL CORE DEHDL crashes when doing model assignment if CM is open
; s7 \% M; Q. y: v1 U5 |- J6 n966795 ADW ROLLBACK rollback utility does not honor -product option from command line
) ?: B M f. E0 a967089 SIG_INTEGRITY OTHER Matchgroups created by ECSet not deleted when ECset is removed from object." B! b5 x% A3 w4 U+ m$ E9 r
967222 ALLEGRO_EDITOR OTHER PDF export is leaving data off the drawing% R, K' n2 o; W- }/ K6 l9 j) _8 n# o
967240 SIP_LAYOUT WIREBOND Change default bond fingers selected on multi-site leads during "bond to leads" program
" m _9 ]7 q i+ C1 ]967297 ALLEGRO_EDITOR OTHER Dynamic Fillet&Eliminate unused stacked vias cannot be used as the Miniaturization option.
2 E" H& O' x: [967576 CONCEPT_HDL CREFER Occurrence location property values do not appear in flattened schematic generated by CreferHDL; [0 R" r Q1 t5 S6 \1 B$ W$ H! b
968096 ALLEGRO_EDITOR DRC_CONSTR Mechanical Pin to conductor spacing is not followed.6 u- V7 X) u2 C' W( M
968222 SIP_LAYOUT DIE_EDITOR die pin loses IC net for a co-design die with multiple ports within IO-cell1 R7 q0 v* p" ?8 z2 q. j; n& M
968358 CIS PART_MANAGER Capture crash on removing a part from subgroup in part manager* |: s) P% d9 w- z* [
969594 CONCEPT_HDL CORE The dcf file is not updated with schematic changes
# B: k. ?5 F( w0 x, I" Z
: d. y2 z# @2 s5 E, J$ S. LDATE: 12-16-2011 HOTFIX VERSION: 013
9 f- t! q; m! i( N===================================================================================================================================# V7 P# n4 j$ T
CCRID PRODUCT PRODUCTLEVEL2 TITLE$ z: w3 O6 |$ ]5 |
===================================================================================================================================
* c4 Y% {* F5 H1 T, I$ Z3 _- I8 F2 S Q/ W& K875695 SIG_EXPLORER INTERACTIV Enforce Causality check box doesn't work.; Q8 d& B1 \6 q0 G0 Q
927148 CAPTURE PROJECT_MANAGER Capture crashes on creating scehmatic folder with name which already exists in design
3 [0 P4 `9 k" q, p- Y938013 CAPTURE NETLIST_OTHER The netlist in RINF Format contained two identical lines for PCB FOOTPRINT! P8 E3 q" q# b
941409 PSPICE PROBE BUG : Search accuracy wrong in new cursor window
; x+ a0 D: s( i- b5 r7 W( S8 W945242 SIG_INTEGRITY SIMULATION Unable to select "shapes" in find filter for 'show parasitic ' command4 A3 f' F- z9 u! N% [
946293 CONCEPT_HDL ARCHIVER Archiver hangs if there is a whitespace at the end of the path of cref.dat$ `2 x- M: B( B/ B1 @
946770 CONCEPT_HDL CORE 揤iew Design� function is missing in Windows Mode after reseting the menus.. l* m) g! z% z _+ q) ?9 n7 b
950994 CAPTURE NETGROUPS Problem in expanding the netgroup in Auto Connect to Bus function$ N; o8 a; K; p- v7 a9 ?
953530 SIG_INTEGRITY GEOMETRY_EXTRACT Display Parasitics is displaying wrong results for EMS2D Field Solver compared to topology extraction using Probe.3 S! k# f5 S- Q
953713 CONCEPT_HDL PAGE_MGMT Random page replacement/duplication in block$ w( ^( c% o; V' Z: u( }
953917 CONCEPT_HDL ARCHIVER archcore should handle errors correctly0 d- m( z. K. n& M4 b3 M( Y S
953971 ALLEGRO_EDITOR MANUFACT NC Drill files not generated correctly when using the option "搒eparate files for plated/nonplatedholes�# g0 e, O" F. `: k% ~6 f
954400 CAPTURE NETGROUPS BUS members of NetGroup are getting converted to Scalars in Export-Import NetGroup.
" p6 |5 @8 b: _954498 SCM B2F SCM crashes when importing physical1 S% i+ R, [% E- m' m8 L# O
954623 ALLEGRO_EDITOR EDIT_ETCH Unable to complete connection with Add Connect - related to soldermask to cline check?
Q: C6 r: B( ^) T9 O9 a! G3 O954894 ALLEGRO_EDITOR MANUFACT Dimensions disappear when opening database in v16.5 from v16.3
; ~) {# ` E b2 j955029 CONCEPT_HDL CORE custom text font size not recognized in symbol view
" g" @2 J7 H- w- M5 J4 I5 i5 U955133 SIG_INTEGRITY FIELD_SOLVERS The Field solver creates the differential trace model which is reversed T(D1) and T(D2) of bottom side.' {: P* k9 N1 c4 O$ V! w
955290 CAPTURE DRC Description for UPD0014 missing in the Browse DRC markers window
9 T/ z* c! q/ o+ c8 ~" _- J955299 ALLEGRO_EDITOR DRC_CONSTR drc text to smd pin does not work any more on this database in 16.3 S039
U& K# D0 u! h* @% ]; b/ {' W955338 CONCEPT_HDL CHECKPLUS Need to change PART_NAME
8 J2 D$ o' [, Q: i955447 SIG_EXPLORER OTHER Model path set in DE HDL Model Assignment not used by SigXP from CM in DE HDL, ~$ }8 l% _( \$ z2 _3 f
955740 SIG_INTEGRITY GEOMETRY_EXTRACT Crosstalk with Timing Windows does not work correctly& H" h% L7 q4 ~& I+ X4 N. }" ]
955749 ALLEGRO_EDITOR MANUFACT show element Info shows symbol dimensions on incorrect subclass
; L- W; u: S9 y9 f1 o: R$ j955912 ALLEGRO_EDITOR OTHER Shapes with voids that are exported to PDF have gray filled area over the void
% S/ G8 k/ s) H. A# B, J- J" [956129 CONCEPT_HDL INFRA DEHDL uprev hierachical design from 16.2 to 16.5 packaging failure.. C- l, f% D \" i
956373 ALLEGRO_EDITOR NC drawing name doesn't display in the log file
4 o( c' o4 j% c* W$ a2 l: u9 v956393 CAPTURE PROJECT_MANAGER "GENERAL" and "TYPE" tabs are missing from " roperties" dialogue box.4 d; J8 H6 ]+ r% f( u% N% v4 D
956448 PSPICE MODELEDITOR Can not generate a DEHDL symbol from Model Editor, because no Capture license found
- R* b9 V! B: \. l2 u( {* u' W5 j956456 CAPTURE NETLIST_OTHER OrTelesis netlist not transferring user properties defined under combined; ?6 M2 B) X# Q( E* a0 p
956489 ALLEGRO_EDITOR MANUFACT dimensions lost when symbol with diemnsions attached to symbol origin placed on board
5 `- y& }1 T# F* A956603 CONCEPT_HDL OTHER Part Manager "has stopped working" after changing a component
- R0 G! ~, g' z' J956751 ALLEGRO_EDITOR ARTWORK Import Gerber command does not work correctly# `3 s' {, Y5 K' v7 p) c
956847 PCB_LIBRARIAN METADATA PDV - Partdeveloper symbol to function linkage broken/changed in 16.5, ~ X, G# D) S
956987 CAPTURE OTHER Find from "Search toolbar" doesn't gives complete results
+ j: \8 n- a4 W2 n956996 CONCEPT_HDL INFRA Correction to ERROR(SPCODD-7): Following Primitive instance causes CM to empty0 u0 @; Z) S+ I# Z9 |' T
957009 CAPTURE NETLIST_OTHER Problem getting database property in mentor PADS PCB netlist
- _ \8 J% m5 w, l957137 APD DXF_IF DXF out command dose not work correctly.
+ f( Z2 N5 v5 L4 H+ V957167 APD GRAPHICS Highlighting for Static shape with display_nohilitefont environment variable.; t: E) q h9 v0 X4 n. n
957232 SIG_INTEGRITY OTHER Allegro crash during Model Assignment.0 _" k, E/ V/ y8 z# q% B4 U8 L
957267 CONCEPT_HDL INFRA Packager Error after Import Design
5 j5 J) z& M9 a5 t9 g957866 SIP_LAYOUT DATABASE Cavity outline is not getting deleted from symbol file
& b' D$ S( N1 G2 x; s7 b# C3 ?958010 ALLEGRO_EDITOR REPORTS Wants the ability to extract "Batch" reports from Partition ".dpf" files. L1 P% n/ x4 L, |" h3 u L# V
958252 ALLEGRO_EDITOR TESTPREP Resequence testprep with the option - Delete probes too close crashes the design5 C' `* G6 q% P% s0 I/ v) M
958253 ALLEGRO_EDITOR REPORTS Shape did not have thermal relief connected to pin but unrouted nets still shows zero.
$ ~( W1 i# Y U7 {958433 ALLEGRO_EDITOR DRC_CONSTR False embedded component DRCs
6 N3 |/ l% f1 ?5 @* s$ M958753 ALLEGRO_EDITOR SHAPE Dynamic shape is getting corrupted in 16.5
3 r; F2 ^1 F3 j7 Z! X0 `( v959011 ALLEGRO_EDITOR OTHER copy problem of via and cline
5 J9 [+ B& u; {4 T; @$ D3 U959101 ALLEGRO_EDITOR EXTRACT Using extracta with excluding Thermal reliefs
5 K: u& k7 n+ e8 A+ q q- G1 a959253 CONCEPT_HDL INFRA Design will not open$ R6 y- b5 l9 }7 O2 o) F
959299 APD MODULES Getting ERROR(SPMHDB-279) when trying to update modules placed on the Top side7 U3 p: V( p6 E" D! F
959884 CONCEPT_HDL INFRA Design Uprev/concept2cm crashes with Application Error/Out of Memory Error.
5 q: s, r# H; k* D! f5 {3 r959909 ALLEGRO_EDITOR SCHEM_FTB Site level propflow.txt file is ignored property is transferred1 t! W$ k; b0 F! G4 Z6 n
960067 SIP_LAYOUT PLATING_BAR Creation of plating bar removes "NODRC_ETCH_OUTSIDE_KEEPIN" property from the clines.
, E7 j, f, R/ Q# x! R0 P7 @960126 SIG_EXPLORER EXTRACTTOP Allegro PCB SI license is used automatically at Topology Extraction of Allegro Physical Viewer.
1 i. u- t+ K5 _) a/ L& \960143 SIG_INTEGRITY GEOMETRY_EXTRACT Running simulation in Bus sim happened crash while enable Coulpled Via model to S parameter
% j# o& c3 K4 k/ ?. n: p$ O961349 CONCEPT_HDL HDLDIRECT Motorola designs have broken connectivity compared to 16.3
% o2 G* v4 F! V- v; b: _961816 ALLEGRO_EDITOR INTERFACES Normal Export > DXF fails and offsets the pins of the BGA symbol
+ Z$ l2 d, s" ^1 s962519 SIP_LAYOUT WIREBOND Align option doesn't work for wb_tackpoint fingers
, H) ] Y* N; L" v( _6 ]
& ~0 K# {# R9 A4 G, UDATE: 11-30-2011 HOTFIX VERSION: 012
7 A, b Q& u7 M) ?1 j, _===================================================================================================================================6 t( E! I3 |0 V) {' o
CCRID PRODUCT PRODUCTLEVEL2 TITLE
6 E9 X: J! u4 s1 v* M9 T===================================================================================================================================
$ E2 y- A* U- }5 T959581 CAPTURE NETLIST_OTHER PCB Footprint is getting replaced by VALUE in OTHER netlist formats( q. O+ m1 h; e1 n- q' _" |6 c9 B
: }: G, u5 e& h% B0 P( \* X+ `& _
DATE: 11-18-2011 HOTFIX VERSION: 011: x! H" y( I. W. C7 Z2 i' b
===================================================================================================================================
# U6 i- V; J7 j( t2 [CCRID PRODUCT PRODUCTLEVEL2 TITLE% Z& N8 I# N3 E% g
===================================================================================================================================
8 q! d2 O# T- r0 p735439 PCB_LIBRARIAN CORE PDV Moving line-dot pinshapes by arrow keys breaks the pinshape
* q7 M9 i8 b) s& X% z# [894815 CONCEPT_HDL COMP_BROWSER Why does genlibmetadata command give 'Aborted $PROG' Message?
$ |% I* j" Q' v7 N903073 ADW COMPONENT_BROWSE datasheetl_url directive should support a display string for URL
5 Q P/ ], U+ a909919 CONCEPT_HDL OTHER Why is the PublishPDF UNIX command line looking for "true" script?
* a/ T, @& e% C1 j( `, d911561 CAPTURE CORRUPT_DESIGN Capture crashes on trying to save the design.% T4 R0 n! q( | O6 P6 t4 g: U2 X
919579 CAPTURE PRINT/PLOT/OUTPU Print mode be selected based on schematic mode
6 t; ?- P& O" t7 R, c) ^921247 CONCEPT_HDL COMP_BROWSER genlibmetadata.bat file does not have err defined8 C* [8 f1 k4 u( a
925182 CAPTURE PROJECT_MANAGER ENH: Feature to run update cache on all the parts in design cache at once.8 u- ^) B6 X. J* W( k1 d: i! n
926858 CONCEPT_HDL CORE Usability- Modify Component dialog forces user to do 'Reset Filters' to see other ppt rows, Z( ^1 A8 \8 @; u! _) C/ s
927657 CAPTURE NETGROUPS Enhancement: Placement of netgroup definitions under design cache list' v( F4 C8 g: b& N% R
934684 ALLEGRO_EDITOR MANUFACT The relation between the linear dimension and the symbol breaks.' c/ M4 Z& u7 I3 c6 N) ^- n
935836 SCM SCHGEN ASA crashes when generating Flat Document Schematic1 z! z0 O ~, N; I$ \" U
937165 SCM SCHGEN Can't generate Schematic7 G- P; J4 u K# g, _4 ] u
937292 CAPTURE GENERAL Memory usage keeps on growing and finally gets exhausted while search
' [) r, X8 f* m" P0 K937322 CONCEPT_HDL CORE Master.tag file alters the sequence of the files and Genview fails
5 F* y9 h! ^! V) K" v- L939135 CONCEPT_HDL CORE Unable to uprev a 16.3 Design to 16.5 with DEHDL-L License. i& Z8 }2 W2 B/ U' p$ v
940373 CAPTURE TCL_INTERFACE Enhancement: TCL command to add nets to Netgroup
0 B) \3 E4 g- j* n5 m/ m( R940547 TDA CORE ERROR(SPDWSD-69): highspeed cannot be checked in
4 ~# E% {$ f9 p. J940607 SIG_EXPLORER OTHER Inconsistancy in License usage for opening sigxp -orcad
: J3 L2 n7 p9 R( ^- ~" Q4 ?9 [% r940790 F2B PACKAGERXL User doesn't want to display pin numbers after Export Physical 16.5.; t9 o' Y' ] t, R6 J0 M, T+ C* I
940944 SIG_EXPLORER OTHER Inconsistant license usage while opening Orcad PCB SI using allegro -sq -orcad and allegro -sq9 V2 ]1 V+ v. |5 j$ f. k6 y2 a
941354 CAPTURE NETGROUPS Enhancement: Option to rename the unnamed NetGroups
9 j0 M2 H, h$ X9 _941455 ALLEGRO_EDITOR MANUFACT The Dimensioned mechanical symbol when placed in the board does not show all the dimensions.
0 D% v, Z0 E9 o. |! ?; G* {941863 ALLEGRO_EDITOR EDIT_ETCH Different behavior of design in v16_3 & v16_5 when add connect is executed on a segment thru script
8 o, K$ ?4 b( T" D& [% n% N941881 CONCEPT_HDL COMP_BROWSER How can I suppress the dialog from universalbrowser -genlibindex?
9 H' q3 S7 l" v! v942474 CAPTURE NETGROUPS NetGroup member type of last added member must be remembered by Capture7 Y7 A- w4 b( P% I$ q l' R
942522 CAPTURE GEN_BOM Export in excel check mark doesn't invoked BOM in Excel
. u4 {/ w$ T$ `3 p9 v) v7 ?942557 PCB_LIBRARIAN EXPORT_OTHER PDV Export to Capture crash, e5 G6 T. \' M. v% I! d; ~
942569 ALLEGRO_EDITOR MANUFACT Dimension move and change text deletes leaderless balloon
/ Y w5 x% m4 m9 D) w, o1 F: W/ S* T942573 ALLEGRO_EDITOR MANUFACT Balloon type parameter has no effect on leaderless balloon.
' `3 M" O% j u* c& v942613 CONCEPT_HDL CORE Genview supports only SCHEMATIC/SYMBOL/VERILOG/VHDL views as input type. .xcon not recongnised4 _( t l9 I+ a$ t. C( e* h8 d5 j; U
943032 SCM OTHER ASA is not passing the correct reuse_module name to Allegro PCB layout.8 @* R# F8 e" C+ @* v0 m( K* o
943401 CAPTURE NETGROUPS Alphabetical ordering of NetGroups in Place NetGroup m$ O: u9 ^, ?& V
944006 ALLEGRO_EDITOR EDIT_ETCH Vias added to shapes behave differently
* Q/ e3 R2 r- t: k; B* u* T944367 CONCEPT_HDL OTHER Too late to do Model Assingment in conceptHDL 16.5
X5 ?2 u; S5 q) b; y+ u- |8 v G1 o8 @944788 ALLEGRO_EDITOR GRAPHICS Oblong Pad shows unexpected lines
# a8 |4 g, }( Y7 j945221 CONSTRAINT_MGR RETAIN_CNS CM Conflict Resolution fails on more complex designs using ECSets and constraints# K7 q& c( w$ ~" f5 d u
946270 ALLEGRO_EDITOR PLACEMENT The Rotation Type was changed to "Absoute" if the "iangle 90" use at placementedit mode of spb16.5
: t7 f! N2 O) e6 w' e# ?/ J946350 F2B DESIGNVARI Variant Editor rename function removes all components
0 W7 g" y4 S3 ]3 ^4 O- c946380 F2B DESIGNVARI Some VARIANTX properties are hard some soft - why?
; d- S8 k# Y% b2 y1 y: f946419 SIG_INTEGRITY SIMULATION Cannot select component on BoardModel for controller in bus setup form
0 i2 ]3 j4 D$ V8 S' [: w9 F& \946458 SCM SCHGEN Schematic generator adding an unnecessary page9 u2 R' L }) A4 c
947667 ALLEGRO_EDITOR PADS_IN Need support for PADS-POWERPCB-V9.3-BASIC+ j/ @: _+ v0 G: _6 a
947789 ALLEGRO_EDITOR MENTOR mbs2brd crashes during translation on the attached design.! c7 m0 L+ k3 B( \
948110 CONCEPT_HDL CONSTRAINT_MGR Concept HDL craches when opening SigXP from CM5 [/ b( D" N; z: }: `
950970 ALLEGRO_EDITOR MANUFACT Unable to generate artwork, dbdoctor fails to fix errors.
2 z+ D; T: {# \: ^) p& Q' K: P951901 ALLEGRO_EDITOR EDIT_ETCH In 16.5 add connect to same net is shoved
5 I' A X/ Z* D- ~ q' l! l: y951919 ALLEGRO_EDITOR OTHER Exported package symbol soldermask and pastemask padstack locations not the same as original$ Z! g9 Q) I8 @5 x( v a+ |" \9 h
951926 CONSTRAINT_MGR OTHER What is MaestroNotifyNotSetReport.txt file?% F5 y3 K* ?/ q6 a
951939 F2B PACKAGERXL Uprev to 16.5 is changing refdes for some pages
0 e$ V5 n" M3 J. c+ Z951983 CONCEPT_HDL INFRA Problems converting an Allegro design from 16.3 to 16.5' e: Y( T$ J, i/ K
952057 SCM PACKAGER Export Physical does not works correctly from SCM: u6 b( X% f% m7 L# `
952217 ALLEGRO_EDITOR GRAPHICS crash when opening 3d viewer in PCB Editor. r% h& Z! ~7 A& D' ~. j# w
952634 CONCEPT_HDL CHECKPLUS Checkplus logical rule fails on a design which packages fine in 16.5- k" \, u% o* u, z3 e1 l* ~
953018 APD REPORTS Shape affects Package Report result.
m/ D' t. N9 z# ^9 C, ?) o+ R |953337 ALLEGRO_EDITOR OTHER Allow netname and padstack names to be visible for testpoint vias when viewed in Allegro PDF Publisher.
0 [6 {3 t+ T& j1 e x953827 ALLEGRO_EDITOR EDIT_ETCH Snake Breakout function crashed Allegro
' V5 c( F- v0 L9 M7 |9 D953918 GRE CORE GRE cannot route second and third row of pad in die symbol.
( s8 m3 B' W) u$ D/ j954055 CONCEPT_HDL CREFER Crefer fails with UNC install path
* j5 q" M' g2 Y954920 SIG_INTEGRITY CIRCUIT_BUILDER Each neighbor crosstalk simulation crashes or returns blank report3 J% x% }( i9 g6 L4 h
0 p: o3 ?6 Q+ {
DATE: 11-7-2011 HOTFIX VERSION: 010
3 }" d) t# [! Z# ^===================================================================================================================================
( C6 k u0 [8 o% R2 H2 B* i$ j+ fCCRID PRODUCT PRODUCTLEVEL2 TITLE) P1 _. @2 w& f
===================================================================================================================================/ n- x0 I, b0 @/ z
658866 ALLEGRO_EDITOR EDIT_ETCH enhancement option - so that Sliding a via inside a pad does not create a cline9 H r" q3 \4 a3 i7 A, T1 V
928624 ALLEGRO_EDITOR GRAPHICS Layer visibility control for 3D Viewer
3 F- x7 w7 T5 [, ?5 \. [934991 SPECCTRA LICENSING Specctra_adv option is not working correctly for PA3100 plus PS3500 license in v16.5 tiering profile' ^( ^5 y: _) N0 d- u/ g
938073 ALLEGRO_EDITOR PLOTTING Plot Page size A0 and A1 with problem
: H2 Z, d2 P8 s938128 ALLEGRO_EDITOR DRC_CONSTR DRC changes when do update DRC.
8 F0 H7 L/ `/ ?! E& {4 [) D. \3 e, S938648 ALLEGRO_EDITOR GRAPHICS Enh - Requesting a way such that Package keepout appears transparent in 3D Viewer
0 D! c! V& O; F5 e8 f0 f940518 SIP_LAYOUT SYMB_EDIT_APPMOD Swap pins command doesn't complete
& K1 L+ Y; s: p5 e941426 CONCEPT_HDL COPY_PROJECT Copy Project fails - Updating opf view This can't happen!
$ s. s7 l+ Y( F! D7 x5 t1 \941499 ALLEGRO_EDITOR DRAFTING BUG imit Tolerance isnot working for Dimensioning/ v- X! ^/ N$ K$ A4 k8 }5 X' G
941814 CONCEPT_HDL CREFER CreferHDL crashes during ScheGen
# o) K" @; p9 O" p) q$ w- e942914 SIG_INTEGRITY OTHER ZAxis delay calculation7 v/ s0 M/ ~ r% {
943053 ALLEGRO_EDITOR SHAPE Modifying the Board Outline shape will cause the tool to crash
0 l" F. V- e& x945321 SIP_LAYOUT EXPORT_DATA generation of a xml file from cdnsip for shrunken die
# a' L5 q; r7 c5 l* {: z/ C4 A1 N) z945350 ALLEGRO_EDITOR SHAPE iPick does not work on shape boundary edit.+ h: D- O5 N. r" `
945449 APD SKILL When they create a new menu entry with skill APD crashes with next menu selection.
- c( U( B: z! G- j: M946390 ALLEGRO_EDITOR DRAFTING refresh_symbol crash when trying to refresh mech sym that has dimensions
. c( }( W3 ^+ S7 s3 q946401 APD EXPORT_DATA stream out gdsII results in shorting of PWR/GND nets due to elongated etch5 ^4 h$ _) `, l Y9 `9 E1 s
946819 SIP_LAYOUT DEGASSING Shape degass command3 Y8 Y$ s2 Y& a
946869 ALLEGRO_EDITOR OTHER Allegro PDF arc representation needs cleaned up
+ s F6 d: _1 K/ z |: ]" L4 n947230 ALLEGRO_EDITOR SKILL Skill execution crash Allegro 16.5 but work correctly with Allegro 16.3* g1 k, c6 n% ^5 U* _3 O
947603 ALLEGRO_EDITOR OTHER Component Properties (Default or User Defined) not transferred to PDF file
2 A/ p- \5 u l9 R950995 SIG_INTEGRITY OTHER Netrev fatal error when importing logic* _8 y G% p2 g$ I: B) d
951123 ALLEGRO_EDITOR INTERFACES IPC fails to output drill hole info in columns 33-37
9 y- ?) v" {1 e; t* D951557 CONCEPT_HDL CORE Cannot create the entity folder for old plumbing symbol; S; ?! e/ j# H, k! C0 M" r& v
/ ~0 a# T, ?/ b: r( s+ n9 rDATE: 10-26-2011 HOTFIX VERSION: 009
0 h- @; v! o P# ~- J: R===================================================================================================================================: n5 T( I' r5 n7 j+ O
CCRID PRODUCT PRODUCTLEVEL2 TITLE
' R( K0 E7 X2 \* A3 F: _===================================================================================================================================
( A# q% l5 F% C( a h" z( \/ \945788 CONCEPT_HDL CORE Some component properties on the parts are incorrectly changed after Import Sheet4 `% \% n; R/ g) C7 j4 s
945789 ADW LRM Some component instances are not updated by LRM even though cache ptf is updated from reference( s2 c& b2 P W5 \& i- N- N
; I4 u& C/ M& Q2 A, U9 p& b
DATE: 10-21-2011 HOTFIX VERSION: 008* N* A! X+ U+ s3 ]
===================================================================================================================================
: X: i) O. o# g! x' aCCRID PRODUCT PRODUCTLEVEL2 TITLE
6 P8 z: W8 D1 U& Y W===================================================================================================================================0 u1 [+ e% n$ p# m- R3 M
906827 ALLEGRO_EDITOR DATABASE Logic > Parts logic does not work correctly.
$ p/ s( G0 [: T923346 CONCEPT_HDL CORE Not able to move the reference designators inside hierarchal blocks after uprev to 16.5
- h, Y$ _. P- d4 t926347 ADW COMPONENT_BROWSE Usability- Libflow Part check in comment should end up in Comments attribute for UCB/Designer to see it
G, p2 a; A# \* X/ y) J929348 F2B BOM Warning 007: Invalid output file path name
9 _+ ]' j# f/ s: b" [929777 CONCEPT_HDL OTHER Component Revision Manager gives internal error
+ t' f, _; M" R3 Z% Z1 [. D [9 D930783 CONCEPT_HDL CORE Painting with groups with default colors2 j" |" v8 ? k( j
936748 ALLEGRO_EDITOR INTERACTIV "Unplace Component" menu inconsistent between General Edit and Placement Edit Mode.
9 s' O0 [8 J0 j9 ?938143 ALLEGRO_EDITOR CREATE_SYM Why is this Extra Property 'ECSET_MAPPING_ERROR
3 f6 z+ ?3 \- z1 a2 t938281 SIP_RF OTHER export_chips creating bad data when symbol is split and contains V- V+ pins
1 W8 A3 J; z E. w5 e% W938812 ALLEGRO_EDITOR SYMBOL Cannot create a BSM with this DRA, errors out but does not state a reason. e$ }+ b; b p: T, W. V( w+ a1 e
939075 CAPTURE TCL_INTERFACE Texts are getting garbled in command window
Q- V) k: ^/ ^) c9 k939193 F2B PACKAGERXL ERROR(SPCODD-439): Connectivity server is unable to load the design.* _; \7 u& [/ i0 c! J6 f5 i& [
939199 CONCEPT_HDL DOC "Retain electrical constraint on net" mismatch between schematic (YES) and design (NO)6 O1 F$ E( z4 I7 U; D0 B6 E
939346 ALLEGRO_EDITOR SHAPE Shape disappears when updating with variable shape_rki_autoclip set.5 u. ]% J% P8 c2 v2 K
939901 CONCEPT_HDL INFRA NET_SPACING_TYPE shows �?� on lower hierarchy level nets after Upreving to 16.5 version.5 d: ^) {) ]: T& h. r1 N
939918 PSPICE PROBE Print > Preview for output file causes Pspice crash.
: R) X0 @* G: T8 q, `940217 CONCEPT_HDL COMP_BROWSER UCB reports 'No Symbol found for the part'
) k0 o, n& Z4 o% c' D940835 CONCEPT_HDL INFRA Desing package different after uprev to 16.5 where comp instance propeties are lost lost$ c; f! V1 Y4 q3 G9 C& C1 ^
941125 ALLEGRO_EDITOR DATABASE Performance advisor doesn't skip non plated slot padstacks; A( {4 [1 g& P: d1 e
941876 SIG_INTEGRITY OTHER Illegal model name cause pxl fail in 16.3
" S7 N. [9 Q6 \* o942210 SCM OTHER Is the Project File argument is being correctly passed?
! B/ r4 D4 s/ i9 ?, C: r942274 CAPTURE PROJECT_MANAGER Crash on renaming a Design Cache part in Project Manage after doing replace cache9 I& u4 h+ s0 ^7 b% J
942839 ALLEGRO_EDITOR GRAPHICS Graphics Issue- Pads are not visible
( k$ g+ `- P& V' ]. {943055 ALLEGRO_EDITOR SKILL axlDBCreatePropDictEntry causes application to crash
. U' L8 z2 ?2 E6 O
9 l9 W( N' T3 E' ]8 TDATE: 10-21-2011 HOTFIX VERSION: 007
+ T* J% ?- x2 |( G===================================================================================================================================
" z8 Q. i9 j% u' h! h) ]; mCCRID PRODUCT PRODUCTLEVEL2 TITLE
) g, l: }: J+ k+ N* x$ Z===================================================================================================================================
+ h3 u2 d5 k6 N4 c& w9 b841096 APD WIREBOND Function required which to check wire not in die pad center.
: ^$ j$ k3 b- G5 x903263 CAPTURE SCHEMATIC_EDITOR ENH: Selecting parent netgroup must select the underlying netgroup bits.
, ?5 w! E5 y4 ^% ?; j0 p/ V: V906692 ADW LRM LRM window is always in front when opening a project
& u$ B3 l N5 A9 B912942 APD WIREBOND constraint driven wire bonding5 q7 {4 f: `! c7 d
912951 CONCEPT_HDL CONSTRAINT_MGR Need to manage temporary files on Linux systems
9 m, o2 o T* |/ Z, j, w915178 SIP_LAYOUT DIE_STACK_EDITOR Die Pad names changing when updating Die in a design
+ Y6 m9 j# a7 ]) S) h- t917887 PCB_LIBRARIAN VERIFICATION Part should not be released if the alt_symbols has errors
) l9 S9 g! _. u; V# v6 k& S8 v. D923315 SIG_INTEGRITY GEOMETRY_EXTRACT crosstalk simulation fails with TMP popup failure( s1 \+ z- P% l6 O2 t( P8 X
927382 CONCEPT_HDL CHECKPLUS 'Verify Symbol' forces the use of 'Concept_HDL_Studio' license
+ N# X6 \6 K, K4 ?% l3 H( T927664 CONCEPT_HDL CONSTRAINT_MGR Internal Error disposeipsp
* i6 m+ y1 t2 M: ^930152 CAPTURE NETGROUPS Scalar net names when being connected to net group overlap when connections are made one by one, q4 E- `9 F# w+ z2 O2 g* q
930180 CIS LINK_DATABASE_PA Visible property position on schematic get reset on "link database part" operation5 [9 e G% Q# Z9 X" M; a* L! p1 F
930188 CAPTURE DATABASE Capture 16.5 crashes in being re-invoked.2 ^* t8 L. u- ^' U
930541 CAPTURE NETGROUPS NETGROUP element renaming doesn' renames the associated net ?
' S6 i" {: B& X. n {930866 PDN_ANALYSIS SETUP OrCAD PCB SI Session crashes when we open PDN Analysis with "OrCAD PCB SI" license.) t: P$ U3 t& Q% {2 y N
930926 ALLEGRO_EDITOR GRAPHICS Via and Holes not visible eventhough set to Visible in Color form
/ \8 D9 y3 F4 n+ |& X1 V931274 ALLEGRO_EDITOR DRC_CONSTR Negative Plane Islands waived DRCs reappear after performing update DRC.
7 M5 j2 R0 {5 F4 K0 m# P932091 CONCEPT_HDL CORE Prop attached to SIG_NAME property
( y( K: _" J# a- e932255 ALLEGRO_EDITOR GRAPHICS Change in Zoom level makes arc segment to disappear6 q9 k$ a3 `0 n6 O* p
932292 ADW LRM LRM crashes during Update operation on a customer design
0 N5 _$ k' ?* [/ g; G932639 SIG_INTEGRITY OTHER Add Connect command hangs for about 14 seconds and then returns.
1 T3 v/ C; G2 T" L$ S932704 APD DEGASSING Shape > Degass never finishes on large GND plane P8 s7 T6 H, q+ h+ f9 V
932871 APD GRAPHICS could not see cursor as infinite1 [# O: N( {3 N* h# z
932882 CAPTURE SCHEMATIC_EDITOR Capture crash with FIND command - ISR05 H/ c* F5 ]# h7 Z
932969 CONCEPT_HDL CORE ConceptHDL crashes when you save the design in 165 > hotfix #05
- N0 Y% J% M0 a `933024 CAPTURE NETGROUPS Naming restrictions for NetGroup members
' G) t- K" `" @" H6 Q9 G& e; r/ Q933145 F2B PACKAGERXL Add Subdesign list is truncated in Force SubDesign Design Name pulldown
$ u# e$ D4 ]! F7 M933214 APD ARTWORK Film area report is larger when fillets are removed
4 t9 M2 ]: S: v0 P933356 CONCEPT_HDL CORE Net prop display size become 0 if it was attached to SIG_NAME prop.6 W/ O. E7 P% T6 `$ Z% q% S# v
933532 ALLEGRO_EDITOR COLOR Bad color assign and initialisation during creation of new subclass: s; x+ b. h4 `+ ]! |: C; [2 H
933549 ALLEGRO_EDITOR OTHER Chart text missing in export PDF file.9 ]" @, m% Q" U4 Q6 G$ s
934008 ALLEGRO_EDITOR REFRESH refresh symbol updates symbol text to some unexpected values" F- N, g8 m. u
934031 ALLEGRO_EDITOR DRC_CONSTR Bug : Update DRC removes Waived status for some DRCs
# Z+ f3 X- C- i2 K- U934087 CONCEPT_HDL CORE Opening DEHDL and Model Assignment before design loads causes crash: y( P$ V+ e; B- @* q* t
934396 CAPTURE SCHEMATIC_EDITOR Find operation is not searching power symbols with + or - signs.( S1 o$ S. G! H! r4 ?& J
934533 F2B DESIGNVARI The Variant Editor errors are not written to the variants.lst file+ t2 m v! W& h3 i
934811 SIP_LAYOUT UI_FORMS CDNSIP should not hang if contraction value in z-copy command is out-of-bound
0 p9 N) I, I, b; G" P }0 |( f934909 SCM UI Require support for running script on loading a design in SCM' x% q! G' _& Q' M- [6 `2 `/ A& R
935632 CAPTURE SCHEMATIC_EDITOR SHIFT+Mouse wheel scroll(horizontal) of page is not working in Auto Wire Mode.; ?3 a+ [/ l4 s$ I3 O: D0 F
935794 ALLEGRO_EDITOR SHAPE BUG:Shape not filled in 16.5 but it does in 16.3# z7 g' h% K2 @
935988 ALLEGRO_EDITOR INTERFACES When attempting to downrev this 16.5 design to 16.3 the tool will crash
- l7 z: q& c0 v! M936056 ALLEGRO_EDITOR DRC_CONSTR place_manual crash while moving mirrrored symbol) A9 M% g2 `2 J; E7 z9 b* {1 H( X
936098 ALLEGRO_EDITOR SKILL axlDBCreateCloseShape does not work correctly.: n4 D& ?2 N' V+ |4 L' G
936212 ALLEGRO_EDITOR INTERFACES DXF not created if Blocks created for Symbol and padstack3 s$ r2 S# {% ]: E" O# T; J( N
936797 CONCEPT_HDL COPY_PROJECT Copy Project crash9 B4 e2 ?! q) K! ]4 a+ l
936808 ALLEGRO_EDITOR DATABASE Allegro crash replace mechanical symbol' i# h6 Y p; T7 v( o* U
936853 CONCEPT_HDL CONSTRAINT_MGR DEHDL crashes when trying to extract net from CM
. b$ g/ s% D2 [# C6 C. V1 O" J937087 CIS DESIGN_VARIANT Upreved design becomes very slow in Variant view mode. DELEET THE DESIGN AFTER RESOLVING THE ISSUE" H! E {, d: u' p( {
937173 CAPTURE OTHER Wrong license information "UNLICENSED" in Capture >> Help >> About" j: G `: T: W5 u6 _! w
937290 APD PLATING_BAR Plating Bar checks does not recognize connection made through etchback through shape.
" q& d' g7 O; v: T7 N G8 O2 R937411 ALLEGRO_EDITOR DATABASE downrev_library reading from one directory and writing to another hangs the command.
5 Y$ e- R# \( R3 E4 C# r938235 SIP_LAYOUT STREAM_IF Die Orientation is not correct after importing a stream file.
6 S' k9 ?3 K8 ?938273 ALLEGRO_EDITOR OTHER PDF export is is not opening viewer with ads_sdlog variable set5 m* \- L" t$ w2 E7 T- |" h2 R/ J+ _
+ f3 v. S: C8 G; H$ h
DATE: 09-16-2011 HOTFIX VERSION: 006! L& @/ h4 X3 I9 }
===================================================================================================================================
: c% t0 Y0 D6 y2 e9 Z5 mCCRID PRODUCT PRODUCTLEVEL2 TITLE
1 k, B! Y1 Y" F; D( z===================================================================================================================================
" H3 M+ r3 C% |4 v2 U820131 CONCEPT_HDL OTHER Moving symbols to other page will make Allegro components unplaced because logical_path changed.
. L8 O: c i) Y3 ~. u863860 CONSTRAINT_MGR SCHEM_FTB CM should display or Local Interface and Global nets to help defining low level constraints
0 y$ v# B" ~# H/ o919822 TDA CORE Cannot configure LDAP to only list the login name
. d. b, f% _7 X6 Z: m1 B, ~922907 ADW TDA 搇ast_callout_file� directive in the BOM section is empty causes tda for show Access Denied error: n5 c" D. a1 n
924322 ADW COMPONENT_BROWSE Random - No instance properties are added on Add To Design (RMB or double click) from Search Results
. @0 @. I* m. R4 i+ b' H924448 F2B DESIGNVARI Design does not complete variant annotation9 v0 x0 b4 ^6 W( x* _- u f4 @
925584 CONSTRAINT_MGR SCHEM_FTB 16.3 upreved Design passes the SLOT/Function Properties to PCB
$ ]1 T/ F- U } t7 I; h- K* ?. L927102 ALLEGRO_EDITOR OTHER Question of Conductor Detailed Length Report
5 F v% G, ]* J4 y927104 F2B DESIGNVARI Tools > Annotate variants crashes when there are ASCII characters in the property values$ q4 b0 g3 }: I2 l0 B6 ]4 a
927142 F2B DESIGNVARI Incorrect pop up asking while executing variant editor from the command line0 C) }& J h6 P# ?* G# p' F
927166 CAPTURE NETLIST_ALLEGRO ENH: Feature like NET_SHORT in Capture Allegro flow which allows user to short 2 or more power nets8 z, w5 \' ^- w8 |* ~& M
927410 ALLEGRO_EDITOR DATABASE ERROR(SPMHUT-144): Illegal arc specification error when Run DBDoctor- X: _0 ~' `' E N% Y& ?
927475 CONCEPT_HDL CORE About forcereset command of nconcepthdl
6 m: c: p6 |, d927498 CONCEPT_HDL CORE Pin_Name starting with minus causes incorrect behavior for $PN display A( G* R5 e9 J! d, c/ ?
927608 ALLEGRO_EDITOR PADS_IN Import PADs fails with error message: Failed to close the Allegro database: ]1 j7 a+ c: w- b
927637 SCM CONSTRAINT_MGR ASA crashes on change root and also performance is too slow.
* O4 d s2 v; l4 k928429 SIG_INTEGRITY OTHER Request - Package Wizard to work in PCB SI.' V7 ^2 r7 |1 Q7 u5 f' O
928483 ALLEGRO_EDITOR DRC_CONSTR Running Update DRC removes Via List DRC Error when via is actually not in the list
* H8 W( V6 n; W$ l) s& ?928738 PSPICE PROBE Y-axis grid settings for multiple plots. s6 v6 C. Q- f* t+ l1 |* b' _$ A
928748 PSPICE PROBE Cursor width settings not saved
$ b6 `2 v: ^; ]: ~! b; e928779 CONCEPT_HDL CORE Error (1053) occurs on a copied part in SPB165 release9 Y3 h# [& p3 h# V8 J& w
928838 CONCEPT_HDL CONSTRAINT_MGR ECSets not migrated in 16.5$ Y8 O, m# f( D2 x+ r1 j9 P* U: a
928885 SIG_EXPLORER EXTRACTTOP PCB SI crashes when extracting a net from Probe
2 R$ }9 m; n% s$ K929284 CONCEPT_HDL ARCHIVER archive does not create a zip file
, w: F5 Y& v$ X) A/ G) t% x929542 SIP_LAYOUT DIE_ABSTRACT_IF net issue of multiple ports of co-design die in SiP; F& Y+ {* W9 ^7 d& ^" I
929656 ALLEGRO_EDITOR PADS_IN PADS translation fails with Microsoft Visual C++ Runtime Library error
+ B6 p+ `7 D' v930063 ALLEGRO_EDITOR TESTPREP Test prep crash Allego when it can not create pin escape0 g+ ]/ p- ^6 a1 T6 O3 d
930217 CAPTURE NETGROUPS Net aliases doen't gets assigend to bus bits if bus name is checked in NETGROUP.( A" d6 Q+ Y* c2 K
930355 SIP_LAYOUT WIREBOND about "wirebond add nonstandard" command
8 M d4 l( J9 a930607 APD OTHER Layer mapping information is reomved from Layer conversion file upon exporting DXF from board file.
/ h* e" P" m/ s3 e/ b930646 ALLEGRO_EDITOR DRAFTING Bug - Adding Linear Dimenstion for ISO standard add the Angle information as well% K7 s' H; P7 H
930894 CAPTURE TCL_INTERFACE PDF export doesn't creates property file if some symbols are used in page name/folder name
- T- H6 x* l2 C) P7 m! I930944 ALLEGRO_EDITOR OTHER Setting variable 'appmode' equal to 'none' is not changing the Application Mode when reinvoked' Z# e2 @ v8 W! t
930978 ALLEGRO_EDITOR SCHEM_FTB 3rd party netin error - Pin is connected to net <netname> not reconnected no longer happens$ w( F7 q* T8 U& f8 r( o/ ?" z* S& y
931248 ALLEGRO_EDITOR DRC_CONSTR Match Group was removed if member nets became xnets." Y6 i& v4 n+ E w& U% F5 W& r
931278 CONCEPT_HDL INFRA $PN gets copied when upreving design from 16.2 to 16.5 version
& v3 Q% i8 Z, N" z: _8 k931349 CONCEPT_HDL COMP_BROWSER DEHDL craches and corrupts connectivity file when using Modify command extensivly.! m# l, ]' O% f* ^9 F8 R7 [7 o
k3 ~) l& U9 U A6 z& |, Q0 x7 z, sDATE: 08-31-2011 HOTFIX VERSION: 005
! \( A# f4 E! q k3 k+ c2 G===================================================================================================================================
8 K* o+ ?$ h# P/ d" A/ S9 K aCCRID PRODUCT PRODUCTLEVEL2 TITLE
2 S6 }/ [3 m6 j" k7 a2 q+ e===================================================================================================================================. k5 _. t* H; B# i' ^
825848 ALLEGRO_EDITOR SHAPE Shape not filled when edges from 2 RKO shapes touch around mouting hole
3 R2 B: j! y3 C4 T0 S* Q837723 CAPTURE PROPERTY_EDITOR Occurrences of external design not related to current root should not show
4 c' v2 `8 g2 E0 K9 |' P# w. e. q891079 CONCEPT_HDL CORE DEHDL crashes with large number of commands in Winodws mode! z" [. _0 |, b, `5 C1 e% B5 N
910908 SIG_EXPLORER OTHER Cannot open top if Tx AMI dll name contain more than 2 dot.6 s" S: [) N r" ?* K6 r
914036 CAPTURE LIBRARY ENH: Option to delete a corrupted part from a library and leaving other parts intact in the library.
4 u7 {) _4 ]' U$ M! ]) ^+ p914679 ALLEGRO_EDITOR INTERACTIV Custom toolbars are not retained when switching between brd to dra and back to brd file using the File > Recent Designs
' I1 S0 V) v# K/ a- `' ~. n914870 MODEL_INTEGRIT OTHER mergedml fails to merger 2 DML files from the model integrity) }4 X. K4 p) B# f. _
915645 ALLEGRO_EDITOR MANUFACT Allow the user to place the cross-section chart at a desired location
# p' Q0 J4 m* k, B7 C& [915653 ALLEGRO_EDITOR INTERACTIV unable to delete non-etch shape
! y. k) D/ W% p7 O7 C% ^$ [915711 ALLEGRO_EDITOR MANUFACT dimensioning tolerancing by limit not working5 I: ^' ?) J d
916321 CAPTURE GEN_BOM letter limitation in include file) t8 A3 \" V5 [6 S
916907 CAPTURE SCHEMATICS 揂uto Connect to Bus� should place the wire through non-connectivity objects5 L0 u/ A6 a/ o# X/ ~: U' e
920327 CONSTRAINT_MGR ANALYSIS The TotalEtchLength predicate in Constraint Manager does not work for a netclass with a bus.' x* b* U' R( i
920753 ALLEGRO_EDITOR GRAPHICS If I confirm to padshape with zoom-in after install the s002 It was changed to wrong shape.1 M8 N% ` v4 _# c. M, o" F
921097 ALLEGRO_EDITOR GRAPHICS Padstack seen partail filled when Zoomed in even "static_shapes_fill_solid" is set/ k/ t9 I, ]; s7 P; T" e! H
921226 ALLEGRO_EDITOR DRAFTING Unable to select Package Geometry class when dimensioning in the symbol editor.
6 c6 f% }2 o8 u: L+ A# ^921623 ALLEGRO_EDITOR GRAPHICS Bug : Symbol not visible when zoomed in 16.5 S002+ S2 Y! d& G! x1 E' `9 }
921891 ALLEGRO_EDITOR DRAFTING dimensions are lost after downrev(ing) a SPB 16.5 design with associative dimensions8 a- Y: T! W) }! X3 `4 l3 I
921937 ALLEGRO_EDITOR COLOR Padstacks with shape symbol are not showing correctly. \+ p! s5 ~3 t- F7 W" O3 f% M
922066 CONSTRAINT_MGR ANALYSIS Custom measurement Actual not being cleared when layout changes.; t$ e9 C5 p3 i: k9 g9 q
922117 PSPICE PROBE Label colors are not correct in Probe
9 L7 w; ]: u/ A5 V0 x' K8 _922519 ALLEGRO_EDITOR SKILL add_bviaarray command fails for some clines but not all/ J1 R9 o2 t" _( C) E# N" h0 X# \
923224 ALLEGRO_EDITOR GRAPHICS Thermal flash Display problem in Allegro v16.5 Hotfix S0027 q! I% e" \! B8 m# s
923286 CAPTURE DRC DRC markers not reported for undefined RefDes7 u9 x' h% H" P2 v6 S0 C
923362 ALLEGRO_EDITOR PLOTTING Print to Postscript file not correct in 16.5
2 K5 ?- v! }$ z. u923416 ALLEGRO_EDITOR PAD_EDITOR Pad Designer crash on clicking on the Arrow before Soldermask_top) j7 K- S+ w8 n/ J+ G
923507 CONCEPT_HDL CONCEPT-PCBDW The function of Import Design in the SPB16.5 Design Entry HDL (for data of ADW15.5_S23 + SPB16.3)
+ i8 M* y9 U. K: o6 l: Q! n923910 CIS PART_MANAGER Copy & Paste operation from Part Manager copies properties only to first section of the part.
# r, M# e7 c7 E ~3 S" q6 l2 E923913 CAPTURE PROJECT_MANAGER Capture runs slow on attached design% B) X+ q6 z0 F, s( u. q
923937 CONCEPT_HDL CORE Back annotation time significantly increased with the metadata generation on, h6 S( Z$ Q( I5 y1 }8 q
923949 ALLEGRO_EDITOR INTERFACES Incremental DXF_IN gives 'Invalid subclass' error: _* {2 n+ W# c
924458 SCM OTHER Project > Export > Schematics crashes" i% M/ h( h1 N5 i
924621 ALLEGRO_EDITOR SHAPE Dynamic shapes are disappearing upon updating them to smooth.& j) C/ R- Y4 o/ F4 L2 T. j
925193 SIG_INTEGRITY FIELD_SOLVERS Diffential Impedance (DiffZ0) values computed in the layer stack-up is incorrect. F u9 }# e6 J" v4 r! j1 f
925195 ALLEGRO_EDITOR DRC_CONSTR Incorrect pin to shape DRC error6 N6 a7 M+ _" f$ C8 L: ~+ g
925338 CONCEPT_HDL CORE This application has requested the Runtime to terminate it in an unusual way& D9 d% R, c$ H3 t, Z. S
925435 CAPTURE TCL_INTERFACE Capture crashes if 揝ave design as UPPERCASE� option is disabled.
8 v# v4 Q" o, U- I% O925530 SIG_INTEGRITY OTHER Why the single line impedance value for Top and Bottom layers are different for this design?
1 B6 d* F; A( \: {1 B" r- f925864 ALLEGRO_EDITOR DRAFTING Ability to add dimensioning to different CLASS/SUBCLASS
1 F! V8 X j. j0 P7 l6 w: g, f7 }925976 ALLEGRO_EDITOR MENTOR mbs2brd fails to import data
& M* H' g" S, B3 C& D3 Z926409 SIP_LAYOUT DRAFTING Exporting a 16.5 design to 16.3 will cause the leader/dimesion lines to be removed.. F( j+ G$ m y; ~; r$ }
926443 CONCEPT_HDL CONSTRAINT_MGR In new 16.3 "035" ISR Concept2cm will crash with error.
7 i% w- Z- Y& [4 G/ }' a/ H! o9 x926503 CAPTURE GENERAL Memory leak Capture/Pspice
3 B: ~: b3 p( l5 o/ I" Z- Y- O926553 CONCEPT_HDL CONSTRAINT_MGR CMGR ERROR There is no net in the Cset that has pins matching those in net 1 in the Xnet1 y' X, q" k2 y1 b5 T5 b+ F4 T9 b4 E
926691 ALLEGRO_EDITOR OTHER Crash while Importing Technology File in CM, with Overwrite Constraints.
& t* Y: @/ n( F& r( f! J926887 CONSTRAINT_MGR CONCEPT_HDL Pin pairs lost after Export Physical+ L& [4 _- j# m
927159 CONCEPT_HDL CONSTRAINT_MGR Export Physical fails due to errors in ConCM.log when SIGNAL_MODEL injected property is ''3 E) W3 ~, \: o: ^# A- A9 L; h
1 D8 o9 e, |2 {; K ^1 D7 u2 M
DATE: 08-19-2011 HOTFIX VERSION: 004
: M+ N3 ~8 w. N7 u=================================================================================================================================== c1 E% {$ J6 ] U* f9 ^. [( P$ [
CCRID PRODUCT PRODUCTLEVEL2 TITLE7 r- b; ?' a/ S$ n( A
===================================================================================================================================
+ Z R& Q v# _- ?/ C785417 CONCEPT_HDL COPY_PROJECT copyprojectui crashes with a Windows runtime error% N' @- @' T. f$ r/ A7 l5 o' V
851044 CAPTURE GEN_BOM "Export BOM report to Excel" does not appear in the Standard Bill of Material Window.
; m. b* C8 b7 g1 y- y; u868216 PSPICE MODELEDITOR Encryption of subckt names, internal nodes, comments0 [) a) E! z& R, L) g$ {* V
870247 PSPICE SIMULATOR Encrypt a model and simulate it, info about inside nodes being dumped in the probe file
& A* O. \* W- l% I6 U% {7 n! `& V877091 CAPTURE SCHEMATICS Save JPEG, GIF, PNG and other image formats in the database in its compressed form0 v+ C/ }2 J# L) D# s
894059 CAPTURE OTHER Enhancement: Adding column in edit>browse>parts window
5 b& Q4 D3 O b: q895902 RF_PCB OTHER Alphanumerical allegro pin numbers are unusable in ADS 2009 Update 1
* {5 P( G, A* O1 T895919 RF_PCB OTHER Round trip Allegro to ADS to Allegro requirement
) C5 X; v0 @: `; V* ~903102 ALLEGRO_EDITOR OTHER Zcopy shape command for cline seems not to work correctly.6 c, u+ z' ]7 y' @. z/ D: w* r2 m* U* K: ]
905562 SIG_INTEGRITY SIGWAVE Noise margin seems not to be measured correctly with Eye Measure function.
3 x4 k( r6 M+ P909469 SCM TABLE ASA crashes when opening project
2 S% q# w# s/ z- r$ R8 {909595 APD LOGIC Inconsistency between export die text out and show element after pin swap
% H4 n- C g! N9 R, `' K" Y+ v911123 CONCEPT_HDL CORE 16.2 Design uprev to 16.5 fails with ERROR SPCOCD-152- _* }" f0 E2 @7 y. L
911569 CAPTURE EE_INTERSHEET_RE Q: Why is capture assigning incorrect Irefs in attacehd design ?- V0 r) O( U6 K' Y8 ~
915657 ALLEGRO_EDITOR OTHER Allegro PDF Publisher Mirror capability
T) x1 r! i$ h3 a- ?915755 CONCEPT_HDL CONSTRAINT_MGR Cannot view net in SigXP
9 P% _8 \7 f8 }% d916062 CAPTURE GENERAL Auto Wire Crashes Capture! `' `% h5 j; L* Z+ E
916820 F2B OTHER RF create netlist with problem: ]$ F. r2 r2 P! I3 k! e7 A
917967 ALLEGRO_EDITOR REFRESH Update symbol resets refdes location for bottom side components only.
; u5 s( v& ]2 f/ _& ^! g919343 ALLEGRO_EDITOR PLACEMENT Place Manual is crashing the board file
" S0 [5 I4 n; `919481 CONCEPT_HDL CHECKPLUS CheckPlus isGlobal function is not working
+ ^) i! Z7 A4 |/ L: p! v O2 P7 U919510 CONCEPT_HDL PAGE_MGMT takes 10 min to insert page in DE HDL
' `9 {( @' S! w' b919976 APD DATABASE Update Padstack to design crashed APD.
. h& V1 ?- e" `6 B0 W920418 SIP_LAYOUT OTHER SiP enhancement to Auto Assign Pin Use to add ability to change the pin use definition
) F% Q$ |/ C8 y, {920420 SIP_LAYOUT LOGIC SiP enhancement to Logic Auto Assign Net to display a dialouge Auto Pin Use assignment should be run: f T9 { g( }7 s) H
920712 ALLEGRO_EDITOR ARTWORK Program has encountered a problem ... error when creating artwork/ M1 P0 `8 ]' F u
920763 ALLEGRO_EDITOR ARTWORK Soldermask gerber missing thru-hole pins% o* a. v9 w1 [$ U: Z
920976 ALLEGRO_EDITOR GRAPHICS Question regarding the difference in the behavior of 3D Viewer w.r.t. height_min
, C5 a. _3 R2 b- x4 G920993 ALLEGRO_EDITOR DRC_CONSTR Minimum Metal Spacing Error is detected on Same Net
% s. C* M- v; N/ r921727 ALLEGRO_EDITOR DRC_CONSTR Pad Boundary causing P/P drc to adjacent symbol.( y( I7 Y% D& c# b* P" C
922579 CONCEPT_HDL CORE Xcon file gets corrupted upon Save of Hierarchical design with Global nets tied to interface nets
1 j( Q4 y6 T5 @* O5 d* s3 I922592 CONCEPT_HDL CORE DE-HDL does not report illegal connection when Global Net tied to interface net using an Port symbol and named8 A9 w! T8 ~' H$ q B4 T" p
922758 ALLEGRO_EDITOR DATABASE Allegro crashes while placing second mechanical symbol with route keepin+ A' e8 {& D2 n4 c* X% L
922839 ALLEGRO_EDITOR DFA The DFA drc display is unstable./ z }: Q: r/ R, A, o9 t0 ]4 X
923293 ALLEGRO_EDITOR INTERFACES File> Export> IDX is failing for this design while creating an empty error log.
% v0 G9 x: H+ J$ e4 V! O- j924772 ADW PCBCACHE Import Sheet is not bringing in Parts used in the source pages into target cache ptf, G* y9 [$ H7 l1 ~
- @7 k: {; d$ H3 }DATE: 08-4-2011 HOTFIX VERSION: 003; d1 _) K' `4 T9 J; |
===================================================================================================================================3 W& Z! V8 X! w8 |9 a J2 l" s
CCRID PRODUCT PRODUCTLEVEL2 TITLE
8 C6 `4 b3 m. M5 C R9 r3 y5 F===================================================================================================================================
, d7 ^ |5 @ U8 e6 ]" j: f787414 CAPTURE PROPERTY_EDITOR Part value can抰 be moved on schematic if a part has been copied to a new design and not saved yet.
2 w( a& G# l, `& M+ W6 C+ r" k9 L903898 PCB_LIBRARIAN GRAPHICAL_EDITOR PDV move symbol graphics and Undo causes corruption in graphics1 }& L7 y- P2 _2 F" k
904287 ALLEGRO_EDITOR ARTWORK some cline with arc is missed, when creating artwork.2 R- ]2 s1 E7 k! B: M2 N3 S6 ^
904418 CHANNEL_ANALYS SIMULATION channel analysis sim does not give valid result/ J. }+ w$ ]" V, k& a" U! @$ E9 D2 f
905777 SIG_INTEGRITY SIMULATION User gets popup message that halts an analysis until it is acknowledged8 G, b+ K6 b1 [9 h: L! L8 c
906139 SIG_INTEGRITY OTHER Bus sim result were cleared at the next run even if no preference changed.! _2 `0 n/ h* O' I) k4 E" m& o0 j
908680 SIG_INTEGRITY OTHER Extra prop delay due to resistance
$ b) P* O: @/ u909583 ALLEGRO_EDITOR SKILL axlPolyOperation AND operation is not working correctly.0 \1 Y" r# B9 n( k
910315 ADW LRM Import Design with ADW causes partmgr and pxl errors8 ^3 o/ `5 E: B, U. n- b7 o; U
910689 CONCEPT_HDL CONSTRAINT_MGR NO_SWAP_COMP warning after uprev to 16.5
" o \2 {7 k% k! c _6 K1 N8 S911684 CONCEPT_HDL CONSTRAINT_MGR Attribute Definitions are incompatible for attribute 'HEADER'. when attempting to place in 16.5
d: E) h ]! q$ }# s) C- N912343 APD OTHER APD crash on trying to modify the padstack2 G( b n, Q: s8 j- `6 q1 u
912384 PCB_LIBRARIAN CORE PDV Symbol Editor often freezes when moving groups objects by arrow keys
# F2 w; A2 E9 K0 u: |$ R912853 APD OTHER Fillets lost when open in 16.3.1 }( t. ~( g1 j4 L
913586 ALLEGRO_EDITOR ARTWORK Cannot create the drill figures in this design.
: B; A9 q5 o9 q# C. {- Y$ @914009 ALLEGRO_EDITOR DRC_CONSTR Diff impedance worksheet showing almost zero impedance for differential pair in attached testcase.
6 }6 g# \0 ^" f) Q914110 CONCEPT_HDL OTHER DEHDL 16.5 Uprev overides property values on hierachical blocks
( \7 Z- X% w9 N, H; G! J914264 F2B OTHER Cross Probing from DEHDL for global nets present inside block doesn抰 highlight in PCB Editor.
/ @, v' \2 j+ N5 ^ L1 q% a914309 CONCEPT_HDL CORE 16.5 DEHDL crash on saving the user design8 M. Y9 l) e9 G7 P# }3 J4 W* Y- S
914558 ALLEGRO_EDITOR ARTWORK Gerber6x00 output creates unpainted niche in a shape- y1 W$ `( v+ U$ g( `; P
914633 ALLEGRO_EDITOR ARTWORK Artwork failing in v16.5 while the same design when downrev'd to 16.3 is working fine.
1 v, }6 Z" ~+ l* C2 \' u+ j& [0 `914634 ALLEGRO_EDITOR SKILL IsThrough flag for a padstack is reset9 O7 r& S. n8 t0 Y! m
914746 ALLEGRO_EDITOR DRC_CONSTR DRC Update repeats takes longer on each successive pass.7 c0 `8 W( Z7 Z1 T
914962 ALLEGRO_EDITOR SHAPE Corruption with Shape filling3 u+ r* D' `9 F3 Z
915583 CONCEPT_HDL CORE performance issues in 16.5 compared to 16.3) w5 P$ F2 m9 i" R$ O1 G+ _
915630 PCB_LIBRARIAN OTHER Error when running SI Model Interface Comparison using IBIS models
4 }& i; F$ E3 n4 }915742 CONCEPT_HDL HDLDIRECT I get a newgenasym error and crash when trying to save the symbol8 i* o0 P( o# i
916154 SCM NETLISTER scm crashes when exporting physical database to allegro
0 _! N% I5 w+ V916448 CAPTURE NETLIST_LAYOUT Capture 16.5 Layout netlist contains errors: X& J6 p" W8 }4 \3 f& @: t! {
916462 ALLEGRO_EDITOR DATABASE Edit>Split_plane>create hangs Allgro PCB Editor3 g+ R A9 F0 l3 j- g
916469 ALLEGRO_EDITOR REPORTS One Unrouted pin does not show in Unconnected Pins Report
" f* K( b8 z9 I916495 ALLEGRO_EDITOR INTERACTIV Pick selects components from invisible (Off ) layer
! H% i6 ^" _0 ^: i n916889 CAPTURE NETGROUPS How to change unnamed net group name?
! ~; ]& T; [" U0 N* G917002 ALLEGRO_EDITOR OTHER Allegro PDF Publisher creates extra circles not available on film* T8 W/ M+ U$ M8 c `4 I
917434 APD OTHER Stream out GDSII has more pads in output data.4 |* G3 Y- t, t/ o$ ^" Q+ l
917739 CONCEPT_HDL INFRA Global Net tied to port is getting split into 2 nets in 16.5, in 16.3 it is treated as a single net# B0 `$ j4 h1 y, n x) N/ n
918187 CONSTRAINT_MGR OTHER Missing acGetTotalEtchLength predicate.
$ V; u1 e6 l) o1 O& N; e918576 CAPTURE DRC Incorrect DRC is reported for visible power pins which are connected to power symbol
5 D5 W. Q6 a' B
$ Q, E1 N T/ r2 bDATE: 07-24-2011 HOTFIX VERSION: 002
8 Y( K& H- H N6 D9 l===================================================================================================================================
: V; l" J( Y/ w2 `CCRID PRODUCT PRODUCTLEVEL2 TITLE
, @, m1 F1 r/ o4 U1 d, V===================================================================================================================================
1 q! Q$ s: _- [9 e. N527444 ALLEGRO_EDITOR EDIT_ETCH Slide command needs to be enhanced for same net spacings% ^* P4 p+ C8 U5 b( f6 r' U$ m& }
583257 ALLEGRO_EDITOR EDIT_ETCH Add Connect and slide command needs to be enhanced for same net spacings.
D: g$ @# }4 E) T+ W o/ U592956 ALLEGRO_EDITOR EDIT_ETCH Same net traces will not push and/or shove each other.
$ z& b4 P0 |, C2 C* K# c+ r" ?1 Y745285 ALLEGRO_EDITOR EDIT_ETCH Requesting a true "shove" in Route > Slide for Same net routing.& k, w$ ]0 B3 g5 z+ U8 p/ ^
773503 CAPTURE OTHER Doing "Mirror Horizontally" creates extra un-connects or extra junction dots in Capture V16.3.& S, t/ n3 _0 v
774270 F2B PACKAGERXL Require to ignore space in Pattern setting to prevent duplicated Refdes.
7 C9 I* I( N3 }! Z" x" X799984 ALLEGRO_EDITOR INTERACTIV Enhance the Fix command to select just cline segs8 \ [( Q4 k! B* [" ]: l+ r
809008 CAPTURE SCHEMATIC_EDITOR New nodes get appeared within the design when we select the design and do "Mirror Horizontally"./ R4 Q! P8 o5 i% }0 b
810058 CAPTURE SCHEMATIC_EDITOR New nodes get appeared within the design when we select the design and do "Mirror Horizontally".
4 M! d! ]2 P7 X$ ]; ?821133 ALLEGRO_EDITOR MANUFACT Output artwork for pad data that are suppressed unconnected pads with Gerber 6x00 format
( u* V! F/ r) J831710 CAPTURE SCHEMATIC_EDITOR Capture adds extra junctions to design by itself
( v1 B& g9 H' u842410 ALLEGRO_EDITOR EDIT_ETCH Ability to slide with "Shove" for "Same Net" segments/vias.; J$ S! B$ V2 ]9 ~ \4 _1 x
854971 ALLEGRO_EDITOR INTERACTIV Capability to add cline segment in a temp group2 i G) z1 l, i! t9 t, Y* {
860772 ADW PCBCACHE Save Shopping Cart (pcbcache) is crashing component browser& W& m- h6 H& G5 F% {
867842 CAPTURE PROJECT_MANAGER Capture crash with 'Open File Location"
$ ?6 e- l+ p8 w7 F% \868306 CAPTURE CONNECTIVITY mirror vertically removes junction creates extra nets
7 A- T/ w7 ^. ]3 G4 X882677 EMI RULE_CHECK bypass_plane_split fail if BYPASS_XXXX_EFFECT_DISTANCE Z1 m& C7 [: @1 a5 J0 `. M9 z
891439 ALLEGRO_EDITOR INTERACTIV moving cline segments x* k$ v/ S/ p" L7 D/ m
893544 ALLEGRO_EDITOR INTERFACES IPC-D-356A netlist issue with BB vias.
' z x% Q* g( m$ C/ T [893765 ALLEGRO_EDITOR PARTITION Mail command not sending out email on Linux platforms.
) u9 U* W) e) P- x8 ?& S9 h, e! @894390 SIP_LAYOUT EXPORT_DATA Generate all balls in the xml file for export to EDI's readPackage command5 p- F( s4 c/ j
895933 APD DATABASE Update Symbol shifts the center of the Dynamic Fillet and creating DRCs
3 g" y. [* C* Q/ b! u4 A896598 ALLEGRO_EDITOR PLACEMENT error message is misleading
$ d1 h9 P/ M) f- l; P- n897196 CIS LINK_DATABASE_PA Schematic Contents are not shown in CIS window while link Dbase part for parts placed from library
" q( r! O/ b7 T$ G) w898598 ALLEGRO_EDITOR MENTOR Negative planes from Mentor Board Station not being translated.+ a2 Q. ^/ v' p0 J- v& \; b2 r2 i
899556 ALLEGRO_EDITOR ARTWORK Import artwork seems not to work correctly.+ \ d4 k) ]" B% e5 N! n
900501 ALLEGRO_EDITOR PLACEMENT "lace Replicate Apply" is showing lot of DRC's during placement of replicated circuit in 16.5
8 c8 i, T" @% i+ G J901141 CIS EXPLORER Japanese character appear garbled in CIS explorer window.4 M# @8 ^: c' A7 j m9 c
901666 CAPTURE OTHER Home page of Flowcad-Switzerland and Flowcal-Poland is not preserved on captre restart on start page
/ N* }# w+ K0 Q9 {% a902066 ALLEGRO_EDITOR DRC_CONSTR Shape in Region not follow the constrains: T$ o/ s9 g2 p2 J; G
902349 CAPTURE LIBRARY Capture crashes while closing library- s( p( ^; T* y8 [8 r, `
902508 F2B PACKAGERXL SPB16.5 Packager-XL consumes much more memory than 16.3- h: I6 o1 ~: l2 ]& E
902841 CAPTURE GENERAL Capture Start page does not show) Y" a! H! W; t$ K! g
902876 F2B PACKAGERXL Packager fails on the design upreved in 16.5
D8 c0 o- M6 I M+ w902959 CONCEPT_HDL HDLDIRECT HDLDirect Error while saving design
* g& @; R, ~ K6 B. W6 K903171 PSPICE NETLISTER Why Capture is treating hierarchical power ports as floting nets in complex heirarchy designs?7 ^7 G& M! p3 g* u0 h- \* Q3 Q4 A
903713 ALLEGRO_EDITOR PARTITION Placement Replication do not work fine in the Design Partition7 ]: u8 s/ w# @" J N
903799 SIP_LAYOUT DIE_EDITOR Disappear die pins after exiting co-design die editor
% x8 h! {# Y/ u, A9 z904021 ALLEGRO_EDITOR OTHER Export PDF from SPB 16.5 produces a file not text searchable
: R F/ I8 a4 _8 ?904339 CONCEPT_HDL CORE new design crashes using the attached CDS_SITE
v" {2 f% Q& P6 T9 N$ T- h/ {2 K: P904522 F2B PACKAGERXL Part will not package in 16.5 but packages in 16.3& {; K+ R+ W. ]( R! z! J
904764 APD OTHER Enhance Scale Factor of Stream Out to support 4 decimal places
/ V% _- R2 V: _% d V% x904771 ALLEGRO_EDITOR MANUFACT Pin Number display issue.; Z/ ~8 A$ ?+ G, r. k- Q D6 G
904853 ALLEGRO_EDITOR GRAPHICS Enhancement for showing Static shape as it was seen in 16.3& [# T5 S0 `" ?
905144 CONSTRAINT_MGR ECS_APPLY Min Line Spacing is larger than Primary or Neck Gap less(-) Tolerance but No Warning in CM
5 y, o q6 w4 \% {2 E& S$ t905314 F2B PACKAGERXL Import physical causes csb corruption6 h3 T- c4 E% w6 A- G0 b6 Q; P! A
905337 CONCEPT_HDL CORE ConceptHDL crashes after Import Design process.
& z' |8 D! A C4 ]1 k0 K/ D( K905533 ALLEGRO_EDITOR INTERACTIV Pin numbers for components on BOTTOM Side are moved in Preselect mode,when the BOTTOM layer is invisible8 j) ^+ y2 h; B' |, f
905796 CONCEPT_HDL CONSTRAINT_MGR Fujitsu CM issue inaccurate concept2cm diff pair issues
S3 ] S5 m7 c0 t* w( B905811 CAPTURE EE_INTERSHEET_RE interesheet references in the form of grid grid page number instead of page number grid& M6 O2 m$ ?+ @
906118 CONCEPT_HDL CONSTRAINT_MGR Cannot open CM if SIGNAL_MODEL value was not assigned in ptf.
) _0 o5 a/ P% |5 Y" g* H906153 ALLEGRO_EDITOR SCRIPTS Unable to run allegro script in batch mode on the attached board.; ]8 N9 f4 ]' G+ T
906182 APD EXPORT_DATA Modify Board Level Component Output format
) J7 A* }7 [ c' F Y906200 ALLEGRO_EDITOR DFA Enh- DFA drc invoked in Batch mode returns false constraint value in Show Element& C O' o" w3 @# i6 A( K# G+ x
906517 PSPICE PROBE PSpice new cursor window shows incorrect result.
. J# l" f$ s; D" A U906627 ADW COMPONENT_BROWSE ppt options are not read if ucb is launched from FM. works fine if launched from dehdl.( S- V6 D6 w" X0 V( |( H# L
906647 SIG_INTEGRITY LIBRARY lib_dist creates a signoise.log in current directory (with backup files like ,1 ,2 etc.) on each run* ~; |8 G w# p4 i6 T7 d
906673 F2B PACKAGERXL Ignore the signal model validity check during packaging5 D/ Q/ Q8 O0 ~0 W! e0 _5 e
906688 ADW LRM A copy of source design gets created in worklib of target design after 'Import Design'
9 g% ]" E8 q2 z1 g9 v7 c5 ^906750 ALLEGRO_EDITOR PARTITION Importing design partition removes the testpoint reference designation
9 F! v1 S5 b% n$ _. ^- N# I906874 PSPICE NETLISTER Error less than 2 connections for unconnected hierarchical pin- u! i; T z2 b. A) z5 Z6 u
907095 F2B OTHER Part Manager does not show Error as Undefined when directive ptf_mismatch_exclude_inj_prop is used
' i* n/ [0 Z" t. i: V" X+ r907424 ALLEGRO_EDITOR GRAPHICS Allegro add option for pre 16.5 shape display* c9 p- z8 s) I2 E
907490 CAPTURE NETLIST_LAYOUT 16.5 Layout netlist is not correct. It differs form 16.3 layout netlist.( A( I$ K; Z' O% }6 c
907884 SIP_LAYOUT MANUFACTURING Need to add an "NC" pin text option for "Manufacturing Documentation Display Pin Text"$ u+ J0 a& o. e& ?: ]: t
907885 SIG_INTEGRITY OTHER Matchgroup targets lost when importing netlist to Allegro layout in HF31
5 s$ c* h/ q0 r( \$ d& i907929 CAPTURE TCL_SAMPLE TCL command to delete a property from parts in a library is not working correctly
q, I: ]1 K. J: Y$ {907933 SIG_INTEGRITY OTHER Single line impedence not working in OrCad PCB Professional
0 [6 I" q6 c: I5 G3 _# T907963 CONCEPT_HDL CORE Design uprev issue when moving from 16.2 to 16.5
9 D& E$ u# @6 c2 g; Y908000 SIG_INTEGRITY OTHER Inconsistence z-axis delay reported on Tpoint when define at via location.
( b3 R3 }! \: k {! T908057 CONCEPT_HDL CORE DE HDL crash with the cut and paste of a signal name/ I" v1 H; R. L" H& _
908060 CONCEPT_HDL CORE CTRL+LMB Option not working correctly in 16.3+ u' G, X( Q" s" N4 D$ w
908210 CAPTURE CONNECTIVITY Connection is being lost while dragging a component/ W- w# ~3 U9 N" b
908241 CAPTURE DRC DRC error column is blank in DRC markers window in 16.5
5 D! a' o/ X1 L2 H908339 RF_PCB BE_IFF_IMPORT mechanical holes VIAFC are not at the right place
3 f3 Z# [0 ?% l" V: M+ Y( Z908534 SIP_LAYOUT SYMB_EDIT_APPMOD issues with symbol editor and copying pin arrays
' l: z$ d/ y' l$ u908535 F2B DESIGNVARI When I try to view my variant file the variant editor crashes
7 P" a( e4 S' d% `6 t$ g" \908595 APD 3D_VIEWER cadence Design 3D viewer" screen pops up and is all black because the colors have all converted to b' V! B, K1 ]; ^1 Y
908849 CAPTURE ANNOTATE Getting crash while annotating the attached design
4 c. k# v# \3 S: o( H908874 CONCEPT_HDL CORE Part Manager - No Part Found error when using CCR# 775788 feature
) D. i0 D" T+ n: o/ F7 v909077 CONCEPT_HDL CORE After packaging pin numbers remains invisible even when $PN9 R) M& W- Y; W" O& ]! A, C
909104 ALLEGRO_EDITOR SYMBOL Warning message needs to be modified. It does not save the symbol and also not tell the actual problem.' ?0 ?* u) o _1 L" H/ {/ g
909417 ALLEGRO_EDITOR REPORTS "report -v upc" returns 'Segmentation fault' on Linux1 u. j8 ~% [0 [
909635 SIP_LAYOUT DIE_STACK_EDITOR Add Interposer crashes in SiP Layout$ y% ?" i |8 X$ o& }4 B) U( T
909749 ALLEGRO_EDITOR MANUFACT Allegro Crash during dimensioning8 z5 J" K- h* h q% \) a; |
909760 SIP_LAYOUT MANUFACTURING Create bond finger solder mask doesn't follow the mask opening as defined in the padstack+ n) r2 W5 O: e( a4 { b- i
909861 F2B PACKAGERXL NetAssembler broken within the latest 16.30.031* {! F3 U8 a( R* n3 S
910006 CONCEPT_HDL INFRA Motorola design fails to uprev from 16.3 to 16.5, xcon file is getting corrupted.' d( X: v ^1 n+ S# M; Y
910141 CAPTURE NETGROUPS Modify NetGroup definition does not update Offpage Connector- [2 b" i& c I9 D5 D0 }
910340 ADW LRM Import design in schematic, only 1 page import, the entire block is getting imported.
' c4 d s n; t% r7 g910678 SIG_INTEGRITY OTHER The Analyze> Model Assignment> Auto setup is not creating/assigning models to discrete components in 16.5; j; x& d# G' X
910713 F2B DESIGNVARI Variant Editor crashes when you click web link under Physical Part Filter window.
' a2 l$ H" M3 }5 i910936 F2B PACKAGERXL ConceptHDL subdesign net name is inconsistent4 u) Z; Y4 e" h8 B( z
911530 ALLEGRO_EDITOR SYMBOL Package Symbol Wizard does not create symbol with the name given
9 V, s2 S1 E* }) {911631 CONCEPT_HDL CORE DEHDL crashes when opening a design, e0 X. h% _4 X
912001 ALLEGRO_EDITOR OTHER option_licenses entries are made in allegro.ini even when not set as default3 u, |% l. v/ x
912459 F2B BOM BOMHDL crashes before getting to a menu
6 z$ R, q0 W2 U% J7 g/ O913359 APD MANUFACTURING Package Report shows incorrect data: p3 V M1 n7 e7 r
# Q, M& f5 I7 D: z: @; PDATE: 06-24-2011 HOTFIX VERSION: 001
7 K* r" K% D0 X& K4 n===================================================================================================================================; g/ }% a4 Y) A8 l. _; S
CCRID PRODUCT PRODUCTLEVEL2 TITLE8 T6 B% D' P- ^4 [. b! s
===================================================================================================================================1 ^2 ]# W) B! r( z$ `( M
293005 ALLEGRO_EDITOR DATABASE Allegro crash when attempting to move mech. symbol
+ s/ n$ X6 N2 U. H- ^2 `; A298289 CIS EXPLORER CIS querry gives wrong results
% B* s0 x6 e0 V. i366939 ALLEGRO_EDITOR OTHER Cannot attach refdes on silk subclass with add text
* F5 K D5 i1 Z* X4 v4 l6 x432200 ALLEGRO_EDITOR MANUFACT Fillets with an arc are required for Flexi designs5 w8 R, M9 _$ T, @4 Z
443447 APD SHAPE Shapes not following the acute angle trim control setting.0 V! h' j6 ~% a* k' }1 X( r
473308 PSPICE AA_SENS Passing variables to lower level blocks using subparam7 S% z, @- U0 t( B: U) A
517556 PSPICE AA_SENS Advanced Analysis does not support variables being passed down the hierarchy. u) U% t/ v% x
548143 ALLEGRO_EDITOR SHAPE Dynamic shpe on Etch TOP will not void properly.5 Q$ U+ O. ]& B, l5 x j% j
606959 ADW COMPONENT_BROWSE Key properties with blank values are not getting read in shooping cart1 ?% e4 L* u# i" F( K5 H/ n
616466 ALLEGRO_EDITOR SHAPE Solid shapes are not getting filled
' @& I0 S2 {7 |5 t641358 SIP_LAYOUT DIE_STACK_EDITOR Request for Via and Multi Layer Pin support for DIE stack Area (blue region)
1 a* |7 n0 @* X @644122 SIP_LAYOUT OTHER SiP Layout - xsection - ERROR Adjacent conductive layers are not allowed, but these are diestack layers not conductor
. U: b5 v. H8 [/ O2 Z645816 ALLEGRO_EDITOR SHAPE Slide a cline all removes gnd shapes on board' d, a6 j: D/ v/ k
725355 ALLEGRO_EDITOR SHAPE User can not voided Logo correctly.
. s: D7 m0 K+ u7 v763569 CONCEPT_HDL CORE Display status of Hide/Show unconnected pins icon in DE HDL UI7 l2 f+ h( L: L. w
770021 CAPTURE BACKANNOTATE Changing pin group property after pin swap resets pin numbers
) r' k# I( x/ ]( Q2 r792126 CAPTURE PROPERTY_EDITOR Attempt to change display for occ prop resets6 |; N, Q: G% @) }0 U! C
799014 CONCEPT_HDL CONSTRAINT_MGR concept2cm errors not shown in export physical after hier_write
. a8 ]$ G* ]8 \+ A5 r' T( J803147 CIS LINK_DATABASE_PA Link DB part should not change RefDes of multi package part* l7 V7 b, l* ~+ R8 m' ^! t! p
804240 PSPICE DEHDL Problem in simulation result for a multi-section split part.
. ~, @/ M$ b& C809118 CAPTURE NETLISTS ENH to compare two schematic Capture designs
( t, F0 ?5 i: k& n816568 ALLEGRO_EDITOR SHAPE shape disappears when update to smooth.. State no etch
4 u$ E6 `& Z) ?6 C% x830053 CAPTURE STABILITY DXF export fails if schematic folder name as /: G' {# e+ j$ y+ C9 H% m- f. g% ~
832108 ALLEGRO_EDITOR SHAPE Shape void incorrectly.
$ r2 V) C' Z# N833542 CONCEPT_HDL CORE PDF publisher font is NOT WYSIWIG with respect to what seen in DE HDL7 k. c3 Q( j. }. q
835777 CIS DERIVE_NEW_DB_PA For XLS, donot display table as worksheetName$worksheetName to avoid 8012 error+ R8 U( g' O5 ]" c9 ] p" H
837640 CIS GEN_BOM date format of CIS BOM has broken macros of 16.2 in 16.3 version7 C) m2 e; w( U- Z) b2 p/ W' J
844074 APD SPECCTRA_IF Export Router fails with memory errors.
7 l" y" J0 {" L( W851595 CONCEPT_HDL CORE Pin numbers overlap on the pin and increase in size- |( J7 a2 `' \% m
852832 CAPTURE BACKANNOTATE Why is Capture crashing with Mentor back annotation?
+ B2 w& W6 L8 a3 D7 x855015 ALLEGRO_EDITOR OTHER The rats are NOT connecting to the ends of the clines like they should be.
7 ]$ Y1 |1 _/ E$ s859883 CAPTURE NETLISTS ENH to compare two schematic Capture designs" u6 o" a+ T+ ^. d' ~3 d" M
866009 SIG_INTEGRITY OTHER Net with Pull-up/down should not be used for Diff-pair.
) z# X8 Q3 u' G+ J: z, b866830 SCM REPORTS Multiple lines added as separator between title block and report header instead of single line
4 b6 S7 t% B0 q$ C# j7 F866833 SCM REPORTS Extra indentation is left in the left side of the report when the Line Numbers are set to OFF
: p4 p% c; M8 b1 T% N) W868618 SCM IMPORTS Block re-import does not update the docsch and sch view
$ N: q* ~1 l% c4 _2 D. O, r7 ~) Y4 l873402 SIP_LAYOUT LOGIC pin swap for co-design die in SiP
9 h9 q0 B3 ?7 r8 @7 d+ b: F874010 SIG_INTEGRITY OTHER PCB SI crashes when the Xnet is extracted with VARIANT_TO_IGNORE property.: h- S& E$ C4 |2 k6 k
874400 ALLEGRO_EDITOR INTERACTIV Flip mode issue with move command
1 q% j; k+ d+ E* q874966 ALLEGRO_EDITOR INTERFACES Placed mechanical component do not get Ref Des or part number in IDF file% A1 g8 l5 X+ F4 N
875709 ALLEGRO_EDITOR REPORTS Film area report generated incorrect data at l1
) ]' y' v, P6 C5 n876275 CONCEPT_HDL CONSTRAINT_MGR Constraint Manager not retaining target net
3 K* G; P2 t |) x* l% A879361 SCM UI SCM crashes when opening project4 |/ {" O4 u% e+ o) P1 g& A( n
879496 CONCEPT_HDL OTHER Customer wants to have the tabulation� key as separator in HDL BOM.
; D$ D( W: U" p) g879514 PSPICE AA_MC Monte Carlo to handle equation as comp VALUE.
( F4 k5 K; E" R5 v+ E881845 ALLEGRO_EDITOR SHAPE Delete island deletes complete shape
5 Y0 w% q% K4 C882413 PDN_ANALYSIS PCB_PI PDN Analysis should support routed power nets
7 |- u/ F' q0 @& Q; \6 a+ d882427 PDN_ANALYSIS PCB_PI PDN Analysis target impedance should have a variable multiplier- k, e4 T: L; y0 k V2 S7 d. d
882567 SIG_INTEGRITY OTHER PCB SI crash if boolean type prop was specified to VARIANT env." L' I4 p2 c7 s. g( c i r# F
882644 ALLEGRO_EDITOR PLACEMENT PCB Place Replicate Function automatically match Enhancement. c$ @2 B2 \0 K! {/ h0 B, `
883164 ALLEGRO_EDITOR INTERACTIV Vias marked fanout moves away from position when moving component
/ }( U2 o4 ]; v: }883224 SIG_INTEGRITY SIMULATION crash while reflection simulation from Constraint Manager
0 i. A, z# O7 T- {5 M1 ~883760 PCB_LIBRARIAN METADATA Incorrectly formatted revision.dat file in the metadata folder$ E7 r7 J9 F) c% t
885391 SIG_INTEGRITY SIMULATION RLGC data sampling algorithm and w-element interpolation.
7 q# B9 y" g: {- R885849 ALLEGRO_EDITOR MANUFACT Silkscreen Audit cannot find Solder mask for the text string
3 k+ p- A2 Y6 S( g4 W885996 SIG_INTEGRITY OTHER The effect of sn_maxwidthlimit user preference is not seen in cross section impedance calculations
2 w, b$ A7 O; f4 @+ P886090 ALLEGRO_EDITOR INTERACTIV Add Arc w/Radius does not snap to grid2 Z7 P2 g. m/ k" m/ p
887180 CAPTURE SCHEMATIC_EDITOR Signals Navigation window doesnt get updated for Buses" Y! r1 o3 [' g( g. e' @
887442 APD SHAPE Copper pour of Dynamic shapes on Top layer which contains many existing signal traces fails.6 l6 T+ r& F% M
887578 SCM AUTO_UI Component Replace pops-up the DSPANE-204 Message
. f) {/ h. C7 m+ D) m887926 SIG_INTEGRITY GEOMETRY_EXTRACT Field solution failed if diff trace on bottom doesn't have reference plane.& M; D6 x! ~# z" X/ q- \2 C7 ?
888414 SIG_EXPLORER OTHER View Trace Parameter display the thickness of dielectric incorrectly.$ l( t; i' e0 O. _
888600 CONCEPT_HDL CREFER Cross References not added to Schegen schematic, f$ N* R5 {; ^! f# E+ Y, s; p2 ]+ u0 k
888679 SIP_LAYOUT SHAPE Can't create the Dynamic shape on layer M1_sig without unwanted horizontal openings appearing.
4 t* N$ g# K2 p. ^888804 ALLEGRO_EDITOR OTHER Fillet will become static shape after import from partition board.
4 m. l0 I, p& g7 l888945 CONCEPT_HDL OTHER unplaced component after placing module
1 x$ E' `3 y& `7 h/ H+ [. ~* A889222 ALLEGRO_EDITOR SHAPE Allegro freezes/hangs when adding shape as Polygon with OpenGL ON.
( Z) G( e, H# r6 O( P. {889365 SIG_INTEGRITY GEOMETRY_EXTRACT top/bottom trace impedances extracted to sigxp are wrong in 16.38 E8 j- g* `7 `9 R0 X* w
889404 ALLEGRO_EDITOR OTHER Incorrect pad size for Top conductor padstack written to column 59-62.9 Q! _) Y7 S, d2 i i8 B+ A# _
889426 CONCEPT_HDL CHECKPLUS CheckPlus does not find single node net
) |9 r; F$ |, V9 a889636 ALLEGRO_EDITOR MANUFACT Incorrect spelling of "Visibility" in "Film Control" tab in the Artwork Control Form
8 U/ q1 t+ [+ n5 {& m891235 F2B PACKAGERXL Packager crashes without creating a pxl.log file" {0 L% G7 B: Y' Y' M2 c" J
891292 ALLEGRO_EDITOR SHAPE arc routing causes weird undesireable shape fill performance6 R* ~" q% s1 R& ~" R
891856 ALLEGRO_EDITOR EDIT_ETCH crash when sliding diff pairs
) o# R2 J/ U7 D$ c3 H* n892375 ALLEGRO_EDITOR PLACEMENT Place Replicate Update disband other groups, irrespective Fixed property added or not.
* s( a# r/ y# G) Y9 o0 a+ J7 [5 M892455 ALLEGRO_EDITOR SYMBOL Why the overlapping pins are not reported with DRC?8 K5 O; m8 n! l& H7 d% l
892541 SIG_EXPLORER OTHER Export/Import layerstack through the technology file is changing the layer thickness
, b9 y' K% U- d5 `0 T8 ^892766 APD WIREBOND Excuting Finger moving cannot push aside finger to move with together by shove all mode
) ~% ?/ [$ \% }! N2 K892907 ALLEGRO_EDITOR DRC_CONSTR DRC not reported for etch_turn_under_pin violations
, Q& T N& k2 i# a892963 ALLEGRO_EDITOR SKILL Bad shape boundary created after axlPolyOperation 'OR+ U4 S. U% ~8 `% H) O
892964 SIP_LAYOUT LOGIC Request that Edit Parts List use Dashes "-".
1 z! N3 T2 ~4 T# |893295 APD WIREBOND Why move wirebond command does not shove wirebonds? This result in drcs.
2 ? o' p9 h, t# c- |" e+ N: L. k893706 CONSTRAINT_MGR OTHER On line DRC hangs on partitioned board3 a/ y, _5 J `3 Z$ E: t3 b; H) b
893743 APD EDIT_ETCH Route behavior when spanning pads not as expected.: y g( W: |. @$ q, O- F
893783 SIP_LAYOUT OTHER Padstack Design Editing update File menu with a Update to Design and Close instead of 2 operation
% v* H7 }" h( n6 [7 S+ ?3 J894456 ALLEGRO_EDITOR REPORTS Request Net names be added to Propagation delay lines of the DRC report./ X# P' L' Q: o* q7 ^4 \& s
894499 SIG_INTEGRITY LIBRARY Tool crashes when moving a cline or selecting the Info icon with OpenGL on.) p4 q; {" I f1 t
894582 APD SHAPE When making a dynamic xhatch Via shapes surrounding are abnormal.+ e8 [6 |* _! N$ _, ]0 u3 m: r
895542 SIP_LAYOUT WIREBOND SIP design crashing when moving bond finger using blur mode BLUR_BONDFINGER_PRESRV_CON
" l) d( Y- L# c% U3 N/ u4 m# X895591 ALLEGRO_EDITOR PCAD_IN Importing PCAD file fails to get to the point where we can map layers
1 D, ]$ U6 F: T$ f8 G9 R895757 APD ARTWORK Import Gerber command could not be imported Gerber data
* v2 o5 J) [. b {& Q895964 CONCEPT_HDL CHECKPLUS The CheckPlus command getFileSubstrings is not working correctly; _# G1 K$ W( t4 @7 p
896428 SCM UI Changed Ref Des value not maintained in DEHDL block when part is replaced3 N$ {: K3 O/ }! q
896655 CAPTURE EDIF Import/Export Design of Hierarcy design with OrCAD Capture: k6 v7 D. R% C: w: e
896846 CAPTURE IMPORT/EXPORT Import edif2cap and capture is crashing$ E( ]& I. {0 s( H& ^( v( v
897155 ALLEGRO_EDITOR REPORTS Copper coverage in L2 and L7 looks like the same but film area report had large gap.# [1 t, c" [3 L
897654 CAPTURE EE_INTERSHEET_RE Capture crashes on adding intersheet refernces in abbreviated format on attached design.% ]" j0 ^4 k3 ^
899344 RF_PCB BE_IFF_EXPORT dlibx2iff does not provide the component boundary drawing A2 |2 S( k: o+ |9 S3 q
899629 CONSTRAINT_MGR OTHER ECset for Total Etch Lenght is not present in OrCAD Prof
3 s9 E f, t9 y) i8 l9 m900175 CONCEPT_HDL CONSTRAINT_MGR Few Xnets are lost from Match Group after packaging and importing the netlist to board file.
! {" n- {0 P( F, ]% V900481 CONCEPT_HDL CORE Genview creates a larger symbol without taking the no. of pin in consideration
$ H8 o) z) I& E. C0 a* @ g900813 ALLEGRO_EDITOR DRC_CONSTR With rotated pads, pad (pin - via) soldermask spacing DRC is unreasonable.
7 J, G( c, j S; n" t900905 PSPICE STABILITY Simsrvr crash and RPC Server unavailable error while running simulation.* a! |3 C7 G+ L8 ]& Y. S3 h7 s! v/ Z
901783 CONCEPT_HDL CORE CDS_PART_NAME is annotated on the schematic canvas after running back annotation in 16.5
5 ?3 u# A8 I1 d% w/ w( \: ?; o' ~901909 APD EXPORT_DATA The "package_pin_delay_length.rpt" with Z-axis delay turned on seems wrong
# ]: ~( K4 }$ F9 \901987 CONCEPT_HDL OTHER SPB16.5 zoom fit does not center the page while ploting the schematic page
0 W( f1 k6 R* G+ L! k( y902133 CIS OTHER The visible part property value are being shown very distant from part graphics on schematic
: c3 l: e' i3 Y6 ^% j902166 SPECCTRA ROUTE Specctra crashes when reading in "bestsave.w" file
; ?* E# o* Z) U7 y$ Z! w0 w8 p2 F902170 ALLEGRO_EDITOR DATABASE Diffpair Issues with OrCad PCB Designer Professional
2 u1 n, S# p' \902177 CONSTRAINT_MGR CONCEPT_HDL Option to view the layer thickness in CM worksheet through worksheet customization8 d! ]1 d0 }$ J; }# X
902463 ALLEGRO_EDITOR INTERACTIV APD crashes when we click ( show element ) on certain components2 f! ^0 U$ i z" |- O& A
902621 CONCEPT_HDL OTHER Design Differences (vdd) Crashes4 F( N# N2 ?* {) ~% ?5 g4 Q
902909 APD WIREBOND die to die wirebond crash
& X+ M" l3 o; h' D8 C: _5 C* k. m) X902933 ALLEGRO_EDITOR PADS_IN Pads_in fails while reading PADS ASCII file body' m4 D# t+ i1 ], V4 K
903284 PDN_ANALYSIS PCB_STATICIRDROP IRDrop voltage gradients are plotted outside of the PCB outline
9 n6 ~# |5 b3 { R1 g4 f/ r903680 CONSTRAINT_MGR ECS_APPLY Constraint Manager not passing all hiearchical member objects to a custom measurement.# ?/ b$ B2 G, Q1 E8 U- R
904403 ALLEGRO_EDITOR DATABASE Allegro crashes when refreshing module |
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发表于 2012-2-21 14:58
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