|
|
EDA365欢迎您登录！
您需要 登录 才可以下载或查看，没有帐号？注册
x
2 j1 {" O7 {) c- F. X9 E0 l+ l0 ZDATE: 02-17-2012 HOTFIX VERSION: 016
, b9 ^/ }, j" S% B3 G===================================================================================================================================/ N6 z6 `2 K! Y+ V9 W4 S+ {& ]
CCRID PRODUCT PRODUCTLEVEL2 TITLE! I+ \7 x6 v3 @ W q. \
===================================================================================================================================
( S1 B. m, R3 |$ \; F7 F5 L/ w* d840105 PCB_LIBRARIAN USABILITY PTF subtype is getting changed when Save As option is used in PDV5 N& d" C' E2 d7 o! ^2 {
873075 Pspice PROBE Decibel of FFT results are incorrect.. E9 J, F2 J8 Y4 g8 c1 _
938744 ADW COMPONENT_BROWSE Need ability to customize shopping cart columns to include any Part property
% M! A' [& o: o) l1 s7 b6 K$ G943003 SCM REPORTS The dsreportgen command fails with network located project
x t* p2 U5 Y L$ Z5 J961530 allegro_EDITOR INTERACTIV The problem of Display measure command
& r5 ?/ `: N4 w" _: M) D( `0 W962157 concept_HDL CORE Where is the setting for enabling the Enable PSpice Simulator menu?
9 `$ t9 `5 P6 f Y962206 CONSTRAINT_MGR CONCEPT_HDL Import physical not passing all constraints from the board to frontend
) Q* ?% c1 p w3 i3 v, K! o1 ?968205 PSPICE DEHDL_NETLISTER Change SPLIT_INST property to PSICE_SPLIT_INST for Quad Switch type of design.' s- R6 W$ ]+ p; v
968509 PCB_LIBRARIAN METADATA Incorrect pinlist.txt was generated if DIFF_PAIR_PINS_POS/NEG was set.
( I# T5 l1 h. ^8 t1 \5 M( p" @969450 LAYOUT TRANSLATORS orcad Layout to Allegro Translator crashes/ |/ l! P# C$ j3 z
969997 CONSTRAINT_MGR CONCEPT_HDL ERROR(SPCOPK-1053): Cannot find a ppt part that matches the instance pro~
% ?0 c) x+ ^4 r _971193 CONSTRAINT_MGR UI_FORMS Copy and pasting a formula causes the application to crash on windows.3 y! c# i5 w) F$ C5 h* d& X- C0 K
971601 CONSTRAINT_MGR CONCEPT_HDL ERROR(SPCOPK-1053) and WARNING(SPCODD-66) because of directory structure7 X B, X) ~+ D
973398 CONCEPT_HDL OTHER It should be not packaged with error while working the packaging process if the design has a ERROR
1 I! p8 G( e; l5 _( _/ u/ k973859 PSPICE ENCRYPTION Pspice crashes with encrypted model
* l, l7 y+ w4 Z( y5 z. g973938 PCB_LIBRARIAN VERIFICATION pc.db is missing7 L, F& P+ Z$ n l5 T( M! Y( l
974540 CONCEPT_HDL CORE Graphics updates are real slow
% b1 ? ~! B" \7 {0 K# {. }974791 F2B DESIGNVARI Variants are not back-annotating to schematic and turning to ?, K$ O3 l& J% l s3 @2 d
974818 ALLEGRO_EDITOR NC Backdrilling produces 0 plunges yet no errors reported.) g2 ]+ @/ }8 T
974945 ALLEGRO_EDITOR skill Why is axlPolyOperation is giving different result and not working
~2 b9 h5 h3 [! `: H$ @974946 MODEL_INTEGRIT TRANSLATION ibis2signoise returns the error - Delay measurement fixture must contain V for ECL technology, D: R$ p1 s+ }$ g
975396 CONCEPT_HDL CONSTRAINT_MGR Constraints are dropped after migrating from 16.3 to 16.5
4 d5 q$ U9 L, K. V- \( `975633 ALLEGRO_EDITOR GRAPHICS 'dynamic_layer_visibility' option in 3D Viewer when checked or unchecked should not change (until next change)
! f p$ f( d0 }" z0 P0 P" a$ b( L975720 ALLEGRO_EDITOR DRAFTING Datum dimension lines not adjusting to text move3 i3 o) o+ B' ~/ I9 u* | b8 _
975745 ALLEGRO_EDITOR SKILL cdsServIpc different 16.2 vs 16.5 when Allegro exits- L) r6 p" h# R( A
976013 CONCEPT_HDL INFRA Power pin connection of FPGA symbol is missing in netlist.
# p S5 ^+ C( _/ `& t976058 CONCEPT_HDL COPY_PROJECT SCM Copy project does not create the con and dcf files in tbl_1 views
8 c ?, n! h" X976073 CONCEPT_HDL COPY_PROJECT All the constraint data is lost in the SCM copied design
7 S& [* i1 y+ }7 ^5 h! ^976160 CONCEPT_HDL CREFER Cref fails due to some Caeviews error in the design
7 m+ i# `$ l* b- P976204 ALLEGRO_EDITOR DRC_CONSTR Application falsely reporting Mechanical Pin Antipad to Shape Spacing DRC
3 t+ a2 U* Y0 F' d5 D; ~3 f8 S976448 F2B PACKAGERXL ERROR(SPCOPK-1069): Invalid POWER_GROUP property value
) u- @9 i9 ` M7 z1 i; M9 f976521 ALLEGRO_EDITOR DRC_CONSTR multi-thread update DRC causes the application to crash
# y8 v% E" x; _* M, H( w976838 SIG_INTEGRITY OTHER Unable to create XNET for highlighted nets on attached database even after assigning proper Signal Models.2 o) Z% s0 \8 V" R' j3 v7 t
977517 F2B PACKAGERXL Export physical fails after update to 16.5 from 16.3
/ _8 `% n" m* N ~0 F0 L977902 ALLEGRO_EDITOR DATABASE generate module is crashing allegro, Q3 T* s6 y6 P+ U
978652 ALLEGRO_EDITOR pads_IN PADS_IN fails with ERROR: Finished with errors.! H6 F* g% O1 l& T- @- S
978744 APD DEGASSING Some shapes will not DeGas on this design4 [3 }0 Q. H* X: `5 r1 s
979940 SIP_LAYOUT OTHER SiP Layout Leadframe autobonding with profile selection* J' m. x7 H( h* t0 ~) S
981699 CAPTURE HELP Start Page still shows Hotfix 14 after installing Hotfix 15
7 _, L4 ~9 s5 P/ Y- r3 x6 x$ n8 W8 o- I7 U3 ^0 O' b6 S s4 v
DATE: 02-03-2012 HOTFIX VERSION: 0154 V8 [" V! t; m8 o
===================================================================================================================================
0 L5 Z9 ]& w9 KCCRID PRODUCT PRODUCTLEVEL2 TITLE; J7 t+ v9 U4 M9 w' `
===================================================================================================================================
( g1 n% m* |) K. B871567 CONSTRAINT_MGR SCHEM_FTB Ability to filter out Single Node Nets from Constraint Manager
* f) `. s) N7 B% e: c; w8 _ }( O8 R9 ?921436 ALLEGRO_EDITOR MANUFACT Change in 'decimal place' for new dimension changes the already placed dimension
3 `2 t& r! b; B u9 y" a3 R941433 CONCEPT_HDL COPY_PROJECT 16.5 Copy Project should warn if trying to copy a 16.3 design
3 i) F) Z$ @8 c: K# Y5 L0 ]* Y1 {954375 ALLEGRO_EDITOR MANUFACT Change dimension accuracy for few instaces of associative dimensioning% ]' ]( G0 g Z' l/ A- H6 c
961646 PDN_ANALYSIS EMVIEWER EMViewer Help > About shows wrong version# f4 ]8 Q# ^. n+ B6 ~
964912 CONCEPT_HDL COPY_PROJECT ASA project crash after using copy project
. C' W: b4 \: R5 `: v967223 ALLEGRO_EDITOR MANUFACT Bug:Oval slots orientation in one direction only" Q c( X& o$ |* l1 w' O' E
968865 SIP_LAYOUT DIE_ABSTRACT_IF load of die abstract fails due to differences between component and symbol
( F$ a" w9 x9 a N969485 ALLEGRO_EDITOR SHAPE Shape does not update correctly in 16.5
4 H% N t+ ?* {# H970331 CONSTRAINT_MGR ANALYSIS Impedance worksheet shows a zero value for impedance
* O1 d5 F7 V: C3 }970600 SIP_LAYOUT SYMB_EDIT_APPMOD Option in Die Editor to be able to "physically swap" pins
1 { J, m# i& M; O& i970910 F2B PACKAGERXL Our customer has problem with pin color after pxl 16.5.
+ w5 U1 R2 h- z( H970970 SPECCTRA FANOUT Fanout Vias is placed far away from decaps and does not change the Fanout length even when max_length is reduced.
& N2 ` E9 Z3 i% X2 r970985 SIP_LAYOUT OTHER Importing a .spd2 database file using NA2 will cause the APD/SiP tool crash2 e/ R; C, d2 l* {, c- s7 \
971757 CONCEPT_HDL INFRA Crash while Saving/Packaging the Design
) j. z8 h# {& r2 `1 O! d! r: W971923 ALLEGRO_EDITOR MANUFACT Allow to change decimal accuracy for dimension instances K: U7 g" D$ ?0 X. Q
972568 CONSTRAINT_MGR UI_FORMS Tools >Excel missing from CM+ E( o( y; L* R g+ h
972821 CONSTRAINT_MGR CONCEPT_HDL connectivity server warning: Unable to add property WEIGHT
9 K0 N3 ]7 t" {) `4 G, X973185 SCM CONSTRAINT_MGR ASA2 block not seeing all instances in a package.# m6 R4 k+ r0 R- c
973211 ALLEGRO_EDITOR INTERFACES IDX Object Type Change not recognized
8 z+ h& `" G8 i5 y* @973214 ALLEGRO_EDITOR INTERFACES IDX import package keepout height value change assigns incorrect value o ] k. y4 `; W
973384 CONCEPT_HDL CHECKPLUS The multiple SIG_NAME has to be occurred an ERROR at the SPB16.5.5 M* }7 K" |. l1 z
973514 SIG_INTEGRITY OTHER Mapping error when Ecset is updated to constraint manager from extracted net
9 N0 U% r9 X* B4 x! |973950 ALLEGRO_EDITOR SHAPE Update to smooth crashes application
; _( U" k/ x3 J0 p; C. N4 {+ @% I974533 SIP_LAYOUT OTHER Crashes in Edit > Die Properties and obviously has a setup problem.+ X) c, C/ m6 Z i
974809 ALLEGRO_EDITOR SKILL argument available for hiding a property with function axlDBCreatePropDictEntry is not working
5 A4 p; |- k( m; S, w976179 INSTALLATION ISR Installation of ISR S014 to 16.5 on windows is breaking the documentation index Y) U4 ]( [. `8 C
) [) e; j) u; W. v# T3 Y# pDATE: 01-20-2012 HOTFIX VERSION: 0149 v. \) X' V; X1 T5 n, I$ |
===================================================================================================================================' u) {" v$ U' J; V
CCRID PRODUCT PRODUCTLEVEL2 TITLE
! X9 R" B B$ W* w. b& b===================================================================================================================================1 ~; a6 u) B! R1 y* X) F6 l A
733285 PSPICE SIMULATOR Enhancement:In server-client installation use existing index file from server
" ~; b, H' H, E2 K0 K6 [941020 SIP_LAYOUT OTHER Soldermask enhancement9 G' g- k& T' a9 O
946407 CONSTRAINT_MGR TDD When is it safe to open a 16.5 design in 16.3?; U$ C8 ~9 V$ @( ^. G
953067 CONCEPT_HDL OTHER Variant Editor "Error/Warning messages" form is unusable& Z) s6 K7 r" d# ?$ P
954818 CONCEPT_HDL COMP_BROWSER Replace button turns to Add in component browser when a component replace is done on the schematic
, X9 t1 j/ g' e s# X3 s$ T956450 ALLEGRO_EDITOR DRC_CONSTR Analysis always shows analysis failed in uncoupled length in some diffpairs
' l6 v0 T! w9 W958259 F2B DESIGNSYNC ds.exe crashes on a big design when accessing the design from network drive
% h) M( [ O; L8 E' u& v958395 ALLEGRO_EDITOR SHAPE shape voids won't merge
" O; M, P+ c7 h959212 MODEL_INTEGRIT PARSE Attempting to use "Mark qualified" option on DML File results in dmlcheck and Modelsim wanrings.
& H% j+ M8 ], o6 y2 i) M959940 APD AUTOVOID Void all command gets result as no voids being generated.. I( T2 \) H. }6 ]1 D
960252 PCB_LIBRARIAN CORE Splash screen in PDV prevents showing error message0 V$ M+ V: I( i( }0 i* Q0 }
961634 PDN_ANALYSIS EMVIEWER Cannot launch PDN EMViewer from withing PCB SI+ }8 J# |( E- H6 b& x. @4 h
961645 PDN_ANALYSIS EMVIEWER Standalone EMViewer will crash when opening any result file in the form of *.emv file.
/ ~; Q. A2 s/ E9 s7 r961700 ALLEGRO_EDITOR SHAPE dbdoctor reports ERROR(SPMHUT-144): Illegal arc specification
5 b! O( v( i0 T. a961733 ALLEGRO_EDITOR SKILL Allegro crashes. Appears to have a memory leak.
5 _! P5 S8 n, R" I4 v961758 ALLEGRO_EDITOR DRC_CONSTR DFA check produces no DRC when the dfa bounds are not a rectangle.
: [! \# M* u: Y4 r5 Y961887 CONCEPT_HDL CONSTRAINT_MGR Match Group created from ECSet cannot be deleted in the same session of CM# |" u& c4 j; A; r: {5 P9 I- L
962552 APD EDIT_ETCH BUG:APD crashing when we try to slideget information but move works fine
' E r" h7 u* _/ ^* L& B0 @7 ~962869 CAPTURE STABILITY Capture crashes after RMB click on rotated parallel wires8 _: E4 v' E( e# {# O' o7 P
963232 CAPTURE MACRO Macros not being played in Windows7
& P+ R$ z) V% w' K. E- Z7 n+ c; ?963300 ALLEGRO_EDITOR DATABASE Create > Module crashes in 16.5 but not in 16.3
7 A" W$ U' u K7 M" W; f963651 CONSTRAINT_MGR CONCEPT_HDL ECsets are renamed after packaging on linux8 ]$ T# k. x: S, u- ?0 P
963663 CONSTRAINT_MGR ANALYSIS Q- Why the customized worsheet for Diff pair Impedance not analysing at all for this SIP design
1 `- I/ s) S# z2 v963715 SIG_INTEGRITY OTHER Application only adds the bottom conductor thickness for the via z-axis length
; ~. a2 ]6 |. S3 V3 ]; n1 a964068 ALLEGRO_EDITOR INTERACTIV Allegro crash when using move alt sym mirror alt sym...; Z F: q; M6 U) ]# e6 Y! L E
964267 CIS PART_MANAGER Capture become non-responsive, working on Part Manager and creating CIS BOM, for large designs
^ @8 d2 O/ U- y" Y0 D1 s2 d964597 ADW LRM Issue of LRM license checkout after renewal license by 16.5 (ADW15.5_S23+SPB16.3), l) L: {5 q& O& K. c, q. X f# q
966148 APD INTERFACES Character Limit for DIE Files (*.die) Import
+ {7 Y3 n$ \9 Z/ J966416 F2B PACKAGERXL Cannot package this design9 Z! b8 L* S+ J7 A% y* Z1 p
966421 CONCEPT_HDL CORE DEHDL Crash when applying property on components in duplicated blocks
4 t! k, a8 H6 n$ D( G. ^966693 CONCEPT_HDL CORE DEHDL crashes when doing model assignment if CM is open* g3 A9 q* o, S) v2 L
966795 ADW ROLLBACK rollback utility does not honor -product option from command line$ Q; Y7 S$ f+ }- O
967089 SIG_INTEGRITY OTHER Matchgroups created by ECSet not deleted when ECset is removed from object.
' x/ i) \/ U' d. R& p/ E967222 ALLEGRO_EDITOR OTHER PDF export is leaving data off the drawing
* `+ X# u* Q l+ d8 K0 m967240 SIP_LAYOUT WIREBOND Change default bond fingers selected on multi-site leads during "bond to leads" program
! d$ n7 R' {$ h. Y9 o+ h967297 ALLEGRO_EDITOR OTHER Dynamic Fillet&Eliminate unused stacked vias cannot be used as the Miniaturization option., }4 y4 \; }( B; Z+ k# y
967576 CONCEPT_HDL CREFER Occurrence location property values do not appear in flattened schematic generated by CreferHDL
3 ^. c+ W+ N: t% t968096 ALLEGRO_EDITOR DRC_CONSTR Mechanical Pin to conductor spacing is not followed.
+ e& h! s+ f! m! l8 f9 E) a7 W968222 SIP_LAYOUT DIE_EDITOR die pin loses IC net for a co-design die with multiple ports within IO-cell' j$ u2 n ?: p9 t) u4 C7 D1 Y. G4 P
968358 CIS PART_MANAGER Capture crash on removing a part from subgroup in part manager" C& y0 ^% v. I4 K0 ?# O: D( A6 y
969594 CONCEPT_HDL CORE The dcf file is not updated with schematic changes" F' J) x6 M/ M4 g4 U1 ?: b
$ H9 @$ \ m- I' R; j MDATE: 12-16-2011 HOTFIX VERSION: 013
) T1 c# ^5 V4 B$ |1 z! ]===================================================================================================================================, {6 l. P! Z9 ^$ a* ~) B/ A0 @
CCRID PRODUCT PRODUCTLEVEL2 TITLE
( s# j8 B0 a* K6 _===================================================================================================================================
# Q9 }6 P. Y$ j d( \* F875695 SIG_EXPLORER INTERACTIV Enforce Causality check box doesn't work.& L' X- z& f6 k6 f. ~. F. j
927148 CAPTURE PROJECT_MANAGER Capture crashes on creating scehmatic folder with name which already exists in design
0 f) Q: {/ @; J7 a3 V4 b+ t6 R938013 CAPTURE NETLIST_OTHER The netlist in RINF Format contained two identical lines for PCB FOOTPRINT) c1 W V2 Q* t2 `2 g
941409 PSPICE PROBE BUG : Search accuracy wrong in new cursor window
; n/ f. X T+ _1 ^* `7 K945242 SIG_INTEGRITY SIMULATION Unable to select "shapes" in find filter for 'show parasitic ' command
7 l! \! w, l' @4 d; z5 ~0 M- j946293 CONCEPT_HDL ARCHIVER Archiver hangs if there is a whitespace at the end of the path of cref.dat
: o1 y& z! G4 U$ _+ f0 U+ Y1 z/ K' d946770 CONCEPT_HDL CORE 揤iew Design� function is missing in Windows Mode after reseting the menus.
6 B0 Z( A7 \* d7 e950994 CAPTURE NETGROUPS Problem in expanding the netgroup in Auto Connect to Bus function
, F6 O z; S+ T: c" `+ [/ n953530 SIG_INTEGRITY GEOMETRY_EXTRACT Display Parasitics is displaying wrong results for EMS2D Field Solver compared to topology extraction using Probe.
& q7 h6 k# m# _( c953713 CONCEPT_HDL PAGE_MGMT Random page replacement/duplication in block4 X: D5 N5 L" ?. ?) ~
953917 CONCEPT_HDL ARCHIVER archcore should handle errors correctly
) T3 N! C9 o) g953971 ALLEGRO_EDITOR MANUFACT NC Drill files not generated correctly when using the option "搒eparate files for plated/nonplatedholes�
- P5 T+ X" C5 O954400 CAPTURE NETGROUPS BUS members of NetGroup are getting converted to Scalars in Export-Import NetGroup.# H2 j) {6 v) z
954498 SCM B2F SCM crashes when importing physical
- K2 g0 b k/ |1 A- O5 `954623 ALLEGRO_EDITOR EDIT_ETCH Unable to complete connection with Add Connect - related to soldermask to cline check?0 q- h/ o8 J) _* q; `. c3 A
954894 ALLEGRO_EDITOR MANUFACT Dimensions disappear when opening database in v16.5 from v16.3
0 |, f; I- u3 R2 q: c& V) J" h3 v955029 CONCEPT_HDL CORE custom text font size not recognized in symbol view' q& a& w% f" @3 m1 r0 q0 Y
955133 SIG_INTEGRITY FIELD_SOLVERS The Field solver creates the differential trace model which is reversed T(D1) and T(D2) of bottom side.
2 i, B. S$ C$ E, b955290 CAPTURE DRC Description for UPD0014 missing in the Browse DRC markers window
* {3 C( |( u* X, n- Y; i955299 ALLEGRO_EDITOR DRC_CONSTR drc text to smd pin does not work any more on this database in 16.3 S039
/ H* N+ P6 S5 a; N6 R& s8 s. \955338 CONCEPT_HDL CHECKPLUS Need to change PART_NAME& B" [3 F3 P" B2 W0 o
955447 SIG_EXPLORER OTHER Model path set in DE HDL Model Assignment not used by SigXP from CM in DE HDL
% _$ a& g0 P! x& |) g) u5 p' B# t955740 SIG_INTEGRITY GEOMETRY_EXTRACT Crosstalk with Timing Windows does not work correctly
1 Y6 {- t3 K n5 u0 p955749 ALLEGRO_EDITOR MANUFACT show element Info shows symbol dimensions on incorrect subclass- y w9 J% v% `3 }) f9 W2 }5 b6 h9 y
955912 ALLEGRO_EDITOR OTHER Shapes with voids that are exported to PDF have gray filled area over the void3 z4 T; E( X! i6 |8 B+ e
956129 CONCEPT_HDL INFRA DEHDL uprev hierachical design from 16.2 to 16.5 packaging failure.3 g! z) R1 s# X! h. j9 s Q! \ z
956373 ALLEGRO_EDITOR NC drawing name doesn't display in the log file
& i6 Z" {4 e% I1 F* o6 J/ j956393 CAPTURE PROJECT_MANAGER "GENERAL" and "TYPE" tabs are missing from " roperties" dialogue box.
% ]9 F9 u) i8 H6 u, g9 N956448 PSPICE MODELEDITOR Can not generate a DEHDL symbol from Model Editor, because no Capture license found
9 o: u: @- C1 H) J) F \& ^0 N0 Q956456 CAPTURE NETLIST_OTHER OrTelesis netlist not transferring user properties defined under combined7 V& X3 |% M3 ~% @! W* V/ `- N) B4 a
956489 ALLEGRO_EDITOR MANUFACT dimensions lost when symbol with diemnsions attached to symbol origin placed on board( o) E7 N+ @$ L/ e1 U
956603 CONCEPT_HDL OTHER Part Manager "has stopped working" after changing a component, Z) v( [ S* a
956751 ALLEGRO_EDITOR ARTWORK Import Gerber command does not work correctly: o A0 u& F/ q, y' A+ R" q' M
956847 PCB_LIBRARIAN METADATA PDV - Partdeveloper symbol to function linkage broken/changed in 16.5' K- t; J6 H0 _0 H I2 ]
956987 CAPTURE OTHER Find from "Search toolbar" doesn't gives complete results
! E0 b* `% J V8 f; e1 Z9 @956996 CONCEPT_HDL INFRA Correction to ERROR(SPCODD-7): Following Primitive instance causes CM to empty
$ t1 v/ @ u) ^( u) S# @, q957009 CAPTURE NETLIST_OTHER Problem getting database property in mentor PADS PCB netlist
7 }- |7 ]- q/ C5 S+ ^# L/ |957137 APD DXF_IF DXF out command dose not work correctly.
+ |* A% U8 M4 i9 A3 y957167 APD GRAPHICS Highlighting for Static shape with display_nohilitefont environment variable.' c) p# w9 Y, {$ U o# ^
957232 SIG_INTEGRITY OTHER Allegro crash during Model Assignment.
: X4 O* l W. O* d9 o957267 CONCEPT_HDL INFRA Packager Error after Import Design
& @/ t- K! u- o0 u7 Z6 V; |+ M957866 SIP_LAYOUT DATABASE Cavity outline is not getting deleted from symbol file
! k8 }- C6 k' G( @" @958010 ALLEGRO_EDITOR REPORTS Wants the ability to extract "Batch" reports from Partition ".dpf" files.
. d3 }# f0 e6 J1 L; D9 n958252 ALLEGRO_EDITOR TESTPREP Resequence testprep with the option - Delete probes too close crashes the design
0 W* l5 l+ d5 X5 d958253 ALLEGRO_EDITOR REPORTS Shape did not have thermal relief connected to pin but unrouted nets still shows zero.
3 T* P1 ?0 n( n7 Q" W4 l7 r958433 ALLEGRO_EDITOR DRC_CONSTR False embedded component DRCs
" l0 Q( x" ^" }* x) j. b/ i* q958753 ALLEGRO_EDITOR SHAPE Dynamic shape is getting corrupted in 16.56 z) d2 ~7 v# k: j0 f4 l$ H1 \
959011 ALLEGRO_EDITOR OTHER copy problem of via and cline4 u4 Z! v6 B. p. G) H" j/ c
959101 ALLEGRO_EDITOR EXTRACT Using extracta with excluding Thermal reliefs
9 I$ t, I( J i) j959253 CONCEPT_HDL INFRA Design will not open1 {& u$ i( ?/ W
959299 APD MODULES Getting ERROR(SPMHDB-279) when trying to update modules placed on the Top side" s$ I) e. Z6 `- _0 q+ x
959884 CONCEPT_HDL INFRA Design Uprev/concept2cm crashes with Application Error/Out of Memory Error.
, r7 |7 c# x1 U2 o: R+ f, q* a959909 ALLEGRO_EDITOR SCHEM_FTB Site level propflow.txt file is ignored property is transferred
# _2 z3 y: E! ~5 ?960067 SIP_LAYOUT PLATING_BAR Creation of plating bar removes "NODRC_ETCH_OUTSIDE_KEEPIN" property from the clines.
7 h, q$ u7 o- J& @9 ? q* V960126 SIG_EXPLORER EXTRACTTOP Allegro PCB SI license is used automatically at Topology Extraction of Allegro Physical Viewer.
! ^/ e0 j* x2 L" f/ L960143 SIG_INTEGRITY GEOMETRY_EXTRACT Running simulation in Bus sim happened crash while enable Coulpled Via model to S parameter
- t8 o% l/ w$ ~961349 CONCEPT_HDL HDLDIRECT Motorola designs have broken connectivity compared to 16.3) U) k$ r+ a; p" b* ~9 m8 \9 Y
961816 ALLEGRO_EDITOR INTERFACES Normal Export > DXF fails and offsets the pins of the BGA symbol; U* A6 S3 k3 z+ K/ V- M% s; V: T
962519 SIP_LAYOUT WIREBOND Align option doesn't work for wb_tackpoint fingers
, Q1 d p' Y9 B
% ?* K4 A& x; J( MDATE: 11-30-2011 HOTFIX VERSION: 012
. D! U( z4 x- {2 E5 e' n===================================================================================================================================
& ]& f& F$ k uCCRID PRODUCT PRODUCTLEVEL2 TITLE3 n9 k0 }" V, C% W
===================================================================================================================================
9 A" t4 T+ ^! o: j( P959581 CAPTURE NETLIST_OTHER PCB Footprint is getting replaced by VALUE in OTHER netlist formats
4 ~/ B; h9 v& Z. L$ V) }1 O# W9 D# D9 K: G, l' }
DATE: 11-18-2011 HOTFIX VERSION: 011/ D2 S# N9 X/ ~+ W
===================================================================================================================================
5 c' m! }/ W$ c8 s+ @+ c' [CCRID PRODUCT PRODUCTLEVEL2 TITLE# D) a i8 A! v
===================================================================================================================================
. O4 ~) N+ J' P4 }+ u3 |735439 PCB_LIBRARIAN CORE PDV Moving line-dot pinshapes by arrow keys breaks the pinshape, e) q: R5 u) x. ~. V
894815 CONCEPT_HDL COMP_BROWSER Why does genlibmetadata command give 'Aborted $PROG' Message?9 I& [2 u" n* g! j7 {& Q% Q
903073 ADW COMPONENT_BROWSE datasheetl_url directive should support a display string for URL
( W% G) _. w1 p6 }4 q909919 CONCEPT_HDL OTHER Why is the PublishPDF UNIX command line looking for "true" script?
" v2 g { Y! t911561 CAPTURE CORRUPT_DESIGN Capture crashes on trying to save the design.# ]1 ~5 S' C8 }" f+ ^2 z
919579 CAPTURE PRINT/PLOT/OUTPU Print mode be selected based on schematic mode
+ U2 Y, y" B+ p921247 CONCEPT_HDL COMP_BROWSER genlibmetadata.bat file does not have err defined
( _) q/ z4 N" J1 _% k- M925182 CAPTURE PROJECT_MANAGER ENH: Feature to run update cache on all the parts in design cache at once.
( `, ~5 A _) _; F1 \9 O. m926858 CONCEPT_HDL CORE Usability- Modify Component dialog forces user to do 'Reset Filters' to see other ppt rows
7 g2 i3 D8 s0 C5 h- J& ]927657 CAPTURE NETGROUPS Enhancement: Placement of netgroup definitions under design cache list2 l3 a7 v+ \6 H5 K( [2 z H+ i, |
934684 ALLEGRO_EDITOR MANUFACT The relation between the linear dimension and the symbol breaks.
( z* D/ ~& J3 d7 ^935836 SCM SCHGEN ASA crashes when generating Flat Document Schematic5 u; h1 w& Z# U/ @6 N
937165 SCM SCHGEN Can't generate Schematic
! @4 \* C1 }) M/ l& B937292 CAPTURE GENERAL Memory usage keeps on growing and finally gets exhausted while search
& f1 t0 K9 V" I$ L! y937322 CONCEPT_HDL CORE Master.tag file alters the sequence of the files and Genview fails" G6 t& A2 z, F9 V
939135 CONCEPT_HDL CORE Unable to uprev a 16.3 Design to 16.5 with DEHDL-L License6 L& f2 A. O7 ~
940373 CAPTURE TCL_INTERFACE Enhancement: TCL command to add nets to Netgroup+ u1 s4 Z4 u7 S# d: [, G5 P9 M1 ]- E
940547 TDA CORE ERROR(SPDWSD-69): highspeed cannot be checked in, @+ S% q6 k. |1 O3 `5 B4 p
940607 SIG_EXPLORER OTHER Inconsistancy in License usage for opening sigxp -orcad7 H7 p0 Q& e) l( \
940790 F2B PACKAGERXL User doesn't want to display pin numbers after Export Physical 16.5.
, j0 u4 y3 x' ~3 g6 b C940944 SIG_EXPLORER OTHER Inconsistant license usage while opening Orcad PCB SI using allegro -sq -orcad and allegro -sq
% f- }5 v' I6 [2 @5 s" L941354 CAPTURE NETGROUPS Enhancement: Option to rename the unnamed NetGroups
: X( P0 o. r; U% m" J- o941455 ALLEGRO_EDITOR MANUFACT The Dimensioned mechanical symbol when placed in the board does not show all the dimensions.3 Y( t8 O- y+ q+ B& n$ Z
941863 ALLEGRO_EDITOR EDIT_ETCH Different behavior of design in v16_3 & v16_5 when add connect is executed on a segment thru script
2 l, D& L+ S: m5 `& W941881 CONCEPT_HDL COMP_BROWSER How can I suppress the dialog from universalbrowser -genlibindex?
$ u. I$ m' p* h9 |8 a942474 CAPTURE NETGROUPS NetGroup member type of last added member must be remembered by Capture
- t3 Q; c; \ f& a4 ]/ V# G942522 CAPTURE GEN_BOM Export in excel check mark doesn't invoked BOM in Excel! Y2 J; w; d- {7 H
942557 PCB_LIBRARIAN EXPORT_OTHER PDV Export to Capture crash
/ [: G, W7 t5 ^. N: ?! O0 K942569 ALLEGRO_EDITOR MANUFACT Dimension move and change text deletes leaderless balloon; c/ e9 K! l, r* b6 u) h/ b
942573 ALLEGRO_EDITOR MANUFACT Balloon type parameter has no effect on leaderless balloon.
5 f% t# J6 R: v# k/ M: b942613 CONCEPT_HDL CORE Genview supports only SCHEMATIC/SYMBOL/VERILOG/VHDL views as input type. .xcon not recongnised
9 X( G/ X% y# `2 h% V( B: y5 f943032 SCM OTHER ASA is not passing the correct reuse_module name to Allegro PCB layout.
4 [) d7 m }' l0 X# S5 _& W943401 CAPTURE NETGROUPS Alphabetical ordering of NetGroups in Place NetGroup
( X6 A+ a1 i7 P6 q. q944006 ALLEGRO_EDITOR EDIT_ETCH Vias added to shapes behave differently
& a: p3 J0 ?' f# C: P3 d944367 CONCEPT_HDL OTHER Too late to do Model Assingment in conceptHDL 16.5
6 k7 P. |0 d+ q- S# _944788 ALLEGRO_EDITOR GRAPHICS Oblong Pad shows unexpected lines
& \& a- m7 r5 W$ ^; N9 H945221 CONSTRAINT_MGR RETAIN_CNS CM Conflict Resolution fails on more complex designs using ECSets and constraints
: `/ [4 j5 v! I0 E+ @) ^946270 ALLEGRO_EDITOR PLACEMENT The Rotation Type was changed to "Absoute" if the "iangle 90" use at placementedit mode of spb16.5
, v% K) h% q& R946350 F2B DESIGNVARI Variant Editor rename function removes all components
' P7 d1 }9 Z/ w% P7 n946380 F2B DESIGNVARI Some VARIANTX properties are hard some soft - why?
' n6 L) u: F2 i946419 SIG_INTEGRITY SIMULATION Cannot select component on BoardModel for controller in bus setup form( |2 w9 w4 V& `3 b
946458 SCM SCHGEN Schematic generator adding an unnecessary page
- ^: ]% h5 c/ f# ]. n/ \4 a3 a947667 ALLEGRO_EDITOR PADS_IN Need support for PADS-POWERPCB-V9.3-BASIC6 y" u1 c; _" c T `: E) V7 \3 Q
947789 ALLEGRO_EDITOR MENTOR mbs2brd crashes during translation on the attached design./ l1 r; Z& N! W8 G# k8 I* Y! E5 _
948110 CONCEPT_HDL CONSTRAINT_MGR Concept HDL craches when opening SigXP from CM" [4 Z h5 p; O+ D
950970 ALLEGRO_EDITOR MANUFACT Unable to generate artwork, dbdoctor fails to fix errors.6 k, D2 L' S5 |) X5 @
951901 ALLEGRO_EDITOR EDIT_ETCH In 16.5 add connect to same net is shoved. `. J; Z& ]& C- u' ?: `
951919 ALLEGRO_EDITOR OTHER Exported package symbol soldermask and pastemask padstack locations not the same as original* F+ M! u; }; {& `
951926 CONSTRAINT_MGR OTHER What is MaestroNotifyNotSetReport.txt file?
$ g) }/ \! Z) _* _3 _7 [951939 F2B PACKAGERXL Uprev to 16.5 is changing refdes for some pages
+ }1 e: ~0 h* m9 ]9 `951983 CONCEPT_HDL INFRA Problems converting an Allegro design from 16.3 to 16.5
K Z8 V6 {9 ?0 b952057 SCM PACKAGER Export Physical does not works correctly from SCM
% Y8 P+ C% C j2 c8 U952217 ALLEGRO_EDITOR GRAPHICS crash when opening 3d viewer in PCB Editor8 ^0 o0 _2 n X; a4 }5 G2 r. ?
952634 CONCEPT_HDL CHECKPLUS Checkplus logical rule fails on a design which packages fine in 16.5
t/ h( f( l! B& t& f; h `953018 APD REPORTS Shape affects Package Report result.
* O( R- Y3 ?, g+ J4 ?& u953337 ALLEGRO_EDITOR OTHER Allow netname and padstack names to be visible for testpoint vias when viewed in Allegro PDF Publisher.
8 }6 C& E g% Z8 A0 u953827 ALLEGRO_EDITOR EDIT_ETCH Snake Breakout function crashed Allegro* M i9 F" V- F, o! y) r
953918 GRE CORE GRE cannot route second and third row of pad in die symbol.8 [8 L, @/ p/ g6 [3 p
954055 CONCEPT_HDL CREFER Crefer fails with UNC install path+ }9 O6 B9 B9 c8 \6 c5 z
954920 SIG_INTEGRITY CIRCUIT_BUILDER Each neighbor crosstalk simulation crashes or returns blank report
8 G: J( U$ h% c% M a
4 t' { H, C& ?3 ^+ tDATE: 11-7-2011 HOTFIX VERSION: 010
2 R$ `2 N$ f: o" y: i( y; S: T===================================================================================================================================
0 v% W& w" q Y- q6 l4 P# s. aCCRID PRODUCT PRODUCTLEVEL2 TITLE, t& x# Q+ ?% n0 S- w( H
===================================================================================================================================
) H3 X" t7 D% y' i658866 ALLEGRO_EDITOR EDIT_ETCH enhancement option - so that Sliding a via inside a pad does not create a cline3 W2 d# |' J b8 Y( h
928624 ALLEGRO_EDITOR GRAPHICS Layer visibility control for 3D Viewer/ c a; }. {! t' m% e# b: [
934991 SPECCTRA LICENSING Specctra_adv option is not working correctly for PA3100 plus PS3500 license in v16.5 tiering profile, N. j/ O8 S& @" U! c3 D7 f8 R2 Q
938073 ALLEGRO_EDITOR PLOTTING Plot Page size A0 and A1 with problem! H, D4 o9 m* T/ X _( Y F
938128 ALLEGRO_EDITOR DRC_CONSTR DRC changes when do update DRC.
- d7 T* p2 U) K# O! |6 U938648 ALLEGRO_EDITOR GRAPHICS Enh - Requesting a way such that Package keepout appears transparent in 3D Viewer6 ^$ W3 R% j" w0 a' s( S
940518 SIP_LAYOUT SYMB_EDIT_APPMOD Swap pins command doesn't complete
# i- _: D7 I3 |3 U941426 CONCEPT_HDL COPY_PROJECT Copy Project fails - Updating opf view This can't happen!. l: y" V" y) F) i6 O1 W
941499 ALLEGRO_EDITOR DRAFTING BUG imit Tolerance isnot working for Dimensioning
8 `! H% B7 D) _$ O& `* `. D941814 CONCEPT_HDL CREFER CreferHDL crashes during ScheGen o/ D# D* W6 S5 j- U
942914 SIG_INTEGRITY OTHER ZAxis delay calculation* L- ^ j1 L% j
943053 ALLEGRO_EDITOR SHAPE Modifying the Board Outline shape will cause the tool to crash8 T- }/ c! ~+ @8 A2 C4 N3 W' Q9 q; L- W
945321 SIP_LAYOUT EXPORT_DATA generation of a xml file from cdnsip for shrunken die
) [, E+ `8 E0 y* a7 L, t" g945350 ALLEGRO_EDITOR SHAPE iPick does not work on shape boundary edit.
+ `) U0 g$ j4 {6 ?945449 APD SKILL When they create a new menu entry with skill APD crashes with next menu selection.9 b i4 t0 w6 d
946390 ALLEGRO_EDITOR DRAFTING refresh_symbol crash when trying to refresh mech sym that has dimensions! f& }/ n5 _0 d! \3 F9 J
946401 APD EXPORT_DATA stream out gdsII results in shorting of PWR/GND nets due to elongated etch4 \1 o+ w$ r) [, `# ?6 ^. W$ r
946819 SIP_LAYOUT DEGASSING Shape degass command2 V' S1 l; W* C- \2 Z; y+ r E6 ?$ o
946869 ALLEGRO_EDITOR OTHER Allegro PDF arc representation needs cleaned up
9 n+ u3 c% C, g8 t' j8 o+ i947230 ALLEGRO_EDITOR SKILL Skill execution crash Allegro 16.5 but work correctly with Allegro 16.32 C: F% A! |" H# B
947603 ALLEGRO_EDITOR OTHER Component Properties (Default or User Defined) not transferred to PDF file" k; S. e) I7 J+ U% r# x9 H
950995 SIG_INTEGRITY OTHER Netrev fatal error when importing logic
$ d1 ~+ W% u0 q6 m6 \$ f951123 ALLEGRO_EDITOR INTERFACES IPC fails to output drill hole info in columns 33-37/ r. u( x( Y) @0 W: E; \
951557 CONCEPT_HDL CORE Cannot create the entity folder for old plumbing symbol
5 v& N' n- u* G4 N0 H
7 @1 r0 [3 X+ F' ~DATE: 10-26-2011 HOTFIX VERSION: 009& ~. D% m+ f7 b
===================================================================================================================================3 D# M, z" i* P8 |& {% Z/ c
CCRID PRODUCT PRODUCTLEVEL2 TITLE4 s6 y. y7 w( N4 X1 {% I
===================================================================================================================================8 a3 z/ `" d" C1 {9 c D
945788 CONCEPT_HDL CORE Some component properties on the parts are incorrectly changed after Import Sheet( C) j5 ~( h" [
945789 ADW LRM Some component instances are not updated by LRM even though cache ptf is updated from reference, A. |- \6 Z, g1 p( e* S2 p" [
" `7 F' u" |5 B: \
DATE: 10-21-2011 HOTFIX VERSION: 008
8 s$ M- U4 `& m% C7 g===================================================================================================================================
; A. H8 S6 r0 n3 ]1 k0 ?CCRID PRODUCT PRODUCTLEVEL2 TITLE& w3 a& q+ c& N7 B
===================================================================================================================================2 p( }# [# E( b: J
906827 ALLEGRO_EDITOR DATABASE Logic > Parts logic does not work correctly.6 G! H+ L% u" x2 z8 [
923346 CONCEPT_HDL CORE Not able to move the reference designators inside hierarchal blocks after uprev to 16.56 A& _3 V9 s. T. U3 ^6 c
926347 ADW COMPONENT_BROWSE Usability- Libflow Part check in comment should end up in Comments attribute for UCB/Designer to see it
1 ?6 B* _- ]3 C* j% u7 x7 ~5 G929348 F2B BOM Warning 007: Invalid output file path name' {0 A3 o% A/ t* K
929777 CONCEPT_HDL OTHER Component Revision Manager gives internal error
: g& c* c. p( Z5 t8 q5 E9 W930783 CONCEPT_HDL CORE Painting with groups with default colors
8 m2 ~+ l5 }" x# M& B" Y4 c1 D936748 ALLEGRO_EDITOR INTERACTIV "Unplace Component" menu inconsistent between General Edit and Placement Edit Mode.
' T! q1 A* e' G# H) k1 ~938143 ALLEGRO_EDITOR CREATE_SYM Why is this Extra Property 'ECSET_MAPPING_ERROR) I8 \, C% E% N& k! ]6 k+ Z
938281 SIP_RF OTHER export_chips creating bad data when symbol is split and contains V- V+ pins, O' ^1 b; f) U
938812 ALLEGRO_EDITOR SYMBOL Cannot create a BSM with this DRA, errors out but does not state a reason.* J( J& C; l" }' ?
939075 CAPTURE TCL_INTERFACE Texts are getting garbled in command window. U# y4 Z5 b- p
939193 F2B PACKAGERXL ERROR(SPCODD-439): Connectivity server is unable to load the design.
$ C' {" c, v6 P; x. h3 Y/ D939199 CONCEPT_HDL DOC "Retain electrical constraint on net" mismatch between schematic (YES) and design (NO)3 G4 Z/ s1 q* B- l
939346 ALLEGRO_EDITOR SHAPE Shape disappears when updating with variable shape_rki_autoclip set.& ]- p; ?" E+ {/ Y& x3 q$ j+ v
939901 CONCEPT_HDL INFRA NET_SPACING_TYPE shows �?� on lower hierarchy level nets after Upreving to 16.5 version.
) s; H) i" K' B6 p- F- y939918 PSPICE PROBE Print > Preview for output file causes Pspice crash.2 @/ L* q B j" c6 Z% J
940217 CONCEPT_HDL COMP_BROWSER UCB reports 'No Symbol found for the part'3 [8 o, \9 n( o5 _# T# a
940835 CONCEPT_HDL INFRA Desing package different after uprev to 16.5 where comp instance propeties are lost lost
4 }7 b$ l9 v' M( E* v6 T5 F941125 ALLEGRO_EDITOR DATABASE Performance advisor doesn't skip non plated slot padstacks+ S/ d5 N0 Z1 X( ^8 z
941876 SIG_INTEGRITY OTHER Illegal model name cause pxl fail in 16.3
# f C, k* R% E" }0 E7 y T942210 SCM OTHER Is the Project File argument is being correctly passed? A' g5 b1 y, I' }" ]
942274 CAPTURE PROJECT_MANAGER Crash on renaming a Design Cache part in Project Manage after doing replace cache: S9 }9 c6 y2 F' t2 Y3 t% S( t
942839 ALLEGRO_EDITOR GRAPHICS Graphics Issue- Pads are not visible) A; [& k$ I8 |3 `( c
943055 ALLEGRO_EDITOR SKILL axlDBCreatePropDictEntry causes application to crash
: V: ]" s# m/ I3 a0 |7 ]
2 g d( c) P+ s& _: qDATE: 10-21-2011 HOTFIX VERSION: 007# Z1 ]2 `* N3 q/ H4 U" i/ H
===================================================================================================================================+ |0 ?5 {+ ~" j% F
CCRID PRODUCT PRODUCTLEVEL2 TITLE
* k$ @% A4 g+ Z9 ?# y; u===================================================================================================================================
2 y3 R# O* Z& ]3 G% H+ A7 i841096 APD WIREBOND Function required which to check wire not in die pad center.' A( h9 W. a x* m( z
903263 CAPTURE SCHEMATIC_EDITOR ENH: Selecting parent netgroup must select the underlying netgroup bits.
3 C7 ?7 a @7 g* \; X& [$ i906692 ADW LRM LRM window is always in front when opening a project
2 J1 X' Z( }" K912942 APD WIREBOND constraint driven wire bonding- U1 E0 O2 `% o
912951 CONCEPT_HDL CONSTRAINT_MGR Need to manage temporary files on Linux systems
: l; m) }2 i, G8 J915178 SIP_LAYOUT DIE_STACK_EDITOR Die Pad names changing when updating Die in a design h( U# e2 Q. p+ `. r3 b
917887 PCB_LIBRARIAN VERIFICATION Part should not be released if the alt_symbols has errors; p! C! s5 F% d6 \' w
923315 SIG_INTEGRITY GEOMETRY_EXTRACT crosstalk simulation fails with TMP popup failure! u% V, s' L8 _6 d* w _1 y; F" b
927382 CONCEPT_HDL CHECKPLUS 'Verify Symbol' forces the use of 'Concept_HDL_Studio' license
0 k' @$ N: J. D) D927664 CONCEPT_HDL CONSTRAINT_MGR Internal Error disposeipsp
2 f+ g3 U. Y' {930152 CAPTURE NETGROUPS Scalar net names when being connected to net group overlap when connections are made one by one! H6 W( e/ c+ y/ A( s3 N# E
930180 CIS LINK_DATABASE_PA Visible property position on schematic get reset on "link database part" operation+ d1 c9 m! j- L" K9 [
930188 CAPTURE DATABASE Capture 16.5 crashes in being re-invoked.- A& F7 P) x7 L. b" g q3 L
930541 CAPTURE NETGROUPS NETGROUP element renaming doesn' renames the associated net ?; A2 v9 h: @! m6 c: s
930866 PDN_ANALYSIS SETUP OrCAD PCB SI Session crashes when we open PDN Analysis with "OrCAD PCB SI" license.
/ d, m: U8 u9 `6 u- W# Q) E930926 ALLEGRO_EDITOR GRAPHICS Via and Holes not visible eventhough set to Visible in Color form8 O8 h% r, N$ \
931274 ALLEGRO_EDITOR DRC_CONSTR Negative Plane Islands waived DRCs reappear after performing update DRC.
4 j' v3 k J+ W: F932091 CONCEPT_HDL CORE Prop attached to SIG_NAME property5 C4 P" S( u1 R) j- Z
932255 ALLEGRO_EDITOR GRAPHICS Change in Zoom level makes arc segment to disappear* x4 p+ |4 a/ h. o
932292 ADW LRM LRM crashes during Update operation on a customer design. h, `; C0 I6 S5 Z& U3 N
932639 SIG_INTEGRITY OTHER Add Connect command hangs for about 14 seconds and then returns.
6 [3 j! ]# Y0 E }932704 APD DEGASSING Shape > Degass never finishes on large GND plane6 D4 i0 t/ W: d
932871 APD GRAPHICS could not see cursor as infinite* h' L& L, z, Y I, g: m/ R* j
932882 CAPTURE SCHEMATIC_EDITOR Capture crash with FIND command - ISR05
1 v/ m8 d6 U/ }/ h+ h$ d932969 CONCEPT_HDL CORE ConceptHDL crashes when you save the design in 165 > hotfix #05
$ N* O, F5 D. b* u3 [- Z933024 CAPTURE NETGROUPS Naming restrictions for NetGroup members/ E# F0 M7 n S! Y; U
933145 F2B PACKAGERXL Add Subdesign list is truncated in Force SubDesign Design Name pulldown
6 \) O$ r2 R0 E: D; e7 C933214 APD ARTWORK Film area report is larger when fillets are removed
, ]3 Z ]# j$ `2 A9 t3 ~3 V933356 CONCEPT_HDL CORE Net prop display size become 0 if it was attached to SIG_NAME prop.
6 a5 A/ o) }) Q3 k p G933532 ALLEGRO_EDITOR COLOR Bad color assign and initialisation during creation of new subclass
# W$ ?2 e" B$ r4 t' ]! d0 I v933549 ALLEGRO_EDITOR OTHER Chart text missing in export PDF file. \/ n; n2 [1 p1 b) i5 I$ A
934008 ALLEGRO_EDITOR REFRESH refresh symbol updates symbol text to some unexpected values
1 q3 k. b) e" L934031 ALLEGRO_EDITOR DRC_CONSTR Bug : Update DRC removes Waived status for some DRCs6 W7 j: X4 P7 ^! B
934087 CONCEPT_HDL CORE Opening DEHDL and Model Assignment before design loads causes crash/ g% g7 c2 j! a- r
934396 CAPTURE SCHEMATIC_EDITOR Find operation is not searching power symbols with + or - signs.- ^ l# M# }8 r6 L9 e
934533 F2B DESIGNVARI The Variant Editor errors are not written to the variants.lst file4 ~$ F! G+ e) }5 x `2 r
934811 SIP_LAYOUT UI_FORMS CDNSIP should not hang if contraction value in z-copy command is out-of-bound! ~7 G* D$ _" C2 u4 m0 w
934909 SCM UI Require support for running script on loading a design in SCM
, j: y: o) @' I) g ?935632 CAPTURE SCHEMATIC_EDITOR SHIFT+Mouse wheel scroll(horizontal) of page is not working in Auto Wire Mode.
8 n. U' v3 Z% H: D+ i935794 ALLEGRO_EDITOR SHAPE BUG:Shape not filled in 16.5 but it does in 16.3
4 a" {. t1 A6 f# K% S; U9 j% o) S935988 ALLEGRO_EDITOR INTERFACES When attempting to downrev this 16.5 design to 16.3 the tool will crash
3 k9 T |( m7 L, J" w1 ^936056 ALLEGRO_EDITOR DRC_CONSTR place_manual crash while moving mirrrored symbol
* V% l( W$ i$ C# Q" u936098 ALLEGRO_EDITOR SKILL axlDBCreateCloseShape does not work correctly.9 T( M7 c) N6 v* x! @! |
936212 ALLEGRO_EDITOR INTERFACES DXF not created if Blocks created for Symbol and padstack- K9 J+ d& M1 x' {
936797 CONCEPT_HDL COPY_PROJECT Copy Project crash
& m4 E" H5 r6 {3 ]. G. g0 O936808 ALLEGRO_EDITOR DATABASE Allegro crash replace mechanical symbol' j5 J m" w& g& s
936853 CONCEPT_HDL CONSTRAINT_MGR DEHDL crashes when trying to extract net from CM
3 L3 O! [/ f% S/ l" v" H937087 CIS DESIGN_VARIANT Upreved design becomes very slow in Variant view mode. DELEET THE DESIGN AFTER RESOLVING THE ISSUE* c, l, [: l7 \$ C
937173 CAPTURE OTHER Wrong license information "UNLICENSED" in Capture >> Help >> About; ]$ c% y" ^8 D) m$ m1 N9 u
937290 APD PLATING_BAR Plating Bar checks does not recognize connection made through etchback through shape. ^) U, t7 h0 {% U, U3 _) ^
937411 ALLEGRO_EDITOR DATABASE downrev_library reading from one directory and writing to another hangs the command.+ v7 _! R% p! }/ e; o3 o5 e. ?( ^1 s
938235 SIP_LAYOUT STREAM_IF Die Orientation is not correct after importing a stream file.: t! s8 z: j3 Z
938273 ALLEGRO_EDITOR OTHER PDF export is is not opening viewer with ads_sdlog variable set
9 j$ e/ q4 U9 e3 p9 ?( B& V1 `7 z, f. D
DATE: 09-16-2011 HOTFIX VERSION: 006% Z. I8 U+ J3 I; K# S8 u' o
===================================================================================================================================
7 A4 v7 Z/ G! `8 ^$ M" FCCRID PRODUCT PRODUCTLEVEL2 TITLE y% g0 C5 }& `
=================================================================================================================================== }+ B/ v; f( z. Y- e+ |
820131 CONCEPT_HDL OTHER Moving symbols to other page will make Allegro components unplaced because logical_path changed.- z1 j7 M2 k/ V- [/ U, D2 S6 T+ x
863860 CONSTRAINT_MGR SCHEM_FTB CM should display or Local Interface and Global nets to help defining low level constraints8 _: w/ q2 { A0 X8 Z2 t; Z8 h
919822 TDA CORE Cannot configure LDAP to only list the login name
% R% @6 `3 L1 ^! z* P' A0 H922907 ADW TDA 搇ast_callout_file� directive in the BOM section is empty causes tda for show Access Denied error
U) {- L1 }: H/ K" F& b924322 ADW COMPONENT_BROWSE Random - No instance properties are added on Add To Design (RMB or double click) from Search Results
3 v) q4 d+ L! O9 M( M! I$ ~924448 F2B DESIGNVARI Design does not complete variant annotation
( w/ i3 V5 G* e5 k925584 CONSTRAINT_MGR SCHEM_FTB 16.3 upreved Design passes the SLOT/Function Properties to PCB& {! a) v/ {1 ~1 ]
927102 ALLEGRO_EDITOR OTHER Question of Conductor Detailed Length Report
9 S4 }! z' {' B# `% d927104 F2B DESIGNVARI Tools > Annotate variants crashes when there are ASCII characters in the property values9 a+ \! r* n1 H7 K$ x+ J( w3 L
927142 F2B DESIGNVARI Incorrect pop up asking while executing variant editor from the command line* u: }8 G2 R: a
927166 CAPTURE NETLIST_ALLEGRO ENH: Feature like NET_SHORT in Capture Allegro flow which allows user to short 2 or more power nets' W. W/ i! y6 o3 b( O4 x2 o
927410 ALLEGRO_EDITOR DATABASE ERROR(SPMHUT-144): Illegal arc specification error when Run DBDoctor! I8 [1 V# J& f( K
927475 CONCEPT_HDL CORE About forcereset command of nconcepthdl
: q+ ^4 m! y) ]; m- |/ R927498 CONCEPT_HDL CORE Pin_Name starting with minus causes incorrect behavior for $PN display7 o# Z3 {2 i9 v+ L- T
927608 ALLEGRO_EDITOR PADS_IN Import PADs fails with error message: Failed to close the Allegro database
! R' [& O7 J C) k" |927637 SCM CONSTRAINT_MGR ASA crashes on change root and also performance is too slow.
# v+ x, v' _+ e9 H1 q2 _928429 SIG_INTEGRITY OTHER Request - Package Wizard to work in PCB SI.+ W' S/ p( _& \' |. F% M
928483 ALLEGRO_EDITOR DRC_CONSTR Running Update DRC removes Via List DRC Error when via is actually not in the list
: T& e; _( K8 x6 \928738 PSPICE PROBE Y-axis grid settings for multiple plots
4 V8 a6 K$ Z+ B H928748 PSPICE PROBE Cursor width settings not saved0 b$ H2 a1 r5 v8 V3 N* j
928779 CONCEPT_HDL CORE Error (1053) occurs on a copied part in SPB165 release& Y$ J6 o f$ R
928838 CONCEPT_HDL CONSTRAINT_MGR ECSets not migrated in 16.5& X) G! r$ `7 n% V' z V
928885 SIG_EXPLORER EXTRACTTOP PCB SI crashes when extracting a net from Probe
( g. T2 _% S N1 {) g* k0 Q7 |9 x929284 CONCEPT_HDL ARCHIVER archive does not create a zip file) q8 K% {8 a) L% u# n
929542 SIP_LAYOUT DIE_ABSTRACT_IF net issue of multiple ports of co-design die in SiP
. C6 i# ?% Z' h0 G: Z929656 ALLEGRO_EDITOR PADS_IN PADS translation fails with Microsoft Visual C++ Runtime Library error
0 F) F/ ~) V+ o7 m r9 j" \930063 ALLEGRO_EDITOR TESTPREP Test prep crash Allego when it can not create pin escape
. A. R! b+ A3 c C930217 CAPTURE NETGROUPS Net aliases doen't gets assigend to bus bits if bus name is checked in NETGROUP.
0 s, Q6 E1 f/ @7 ~* e# C930355 SIP_LAYOUT WIREBOND about "wirebond add nonstandard" command
) i- U. k, [+ K3 ~3 M930607 APD OTHER Layer mapping information is reomved from Layer conversion file upon exporting DXF from board file.
# ?7 Z A+ p: t- W$ z930646 ALLEGRO_EDITOR DRAFTING Bug - Adding Linear Dimenstion for ISO standard add the Angle information as well$ s, V4 Z3 ~8 f# o- \ v& o
930894 CAPTURE TCL_INTERFACE PDF export doesn't creates property file if some symbols are used in page name/folder name) a. m4 N$ \/ _2 Q* ]/ y, P
930944 ALLEGRO_EDITOR OTHER Setting variable 'appmode' equal to 'none' is not changing the Application Mode when reinvoked; n+ B2 K5 u' D, B7 O8 t$ c: W
930978 ALLEGRO_EDITOR SCHEM_FTB 3rd party netin error - Pin is connected to net <netname> not reconnected no longer happens
1 y* {- u; N. f5 \# y6 o. x( S931248 ALLEGRO_EDITOR DRC_CONSTR Match Group was removed if member nets became xnets.
$ l( J( Z, m+ n0 T931278 CONCEPT_HDL INFRA $PN gets copied when upreving design from 16.2 to 16.5 version$ a! G4 I; J) |! N. P2 ^
931349 CONCEPT_HDL COMP_BROWSER DEHDL craches and corrupts connectivity file when using Modify command extensivly.% A& t% K$ W2 y& H; ?* j
/ m1 D# f4 ]( G8 ADATE: 08-31-2011 HOTFIX VERSION: 0052 a k! x9 J4 h7 y; G- p% w9 K& H" ^4 [
===================================================================================================================================' J4 v, u' V* L
CCRID PRODUCT PRODUCTLEVEL2 TITLE! F6 l2 E: ]% P5 f
===================================================================================================================================
2 ~4 p- L5 w5 {2 l825848 ALLEGRO_EDITOR SHAPE Shape not filled when edges from 2 RKO shapes touch around mouting hole% C% w# C9 s/ b& G3 s4 w! m3 W
837723 CAPTURE PROPERTY_EDITOR Occurrences of external design not related to current root should not show
& X& ^8 X5 v9 R1 A9 J m4 A$ d) h891079 CONCEPT_HDL CORE DEHDL crashes with large number of commands in Winodws mode
8 N8 {! w2 T6 S910908 SIG_EXPLORER OTHER Cannot open top if Tx AMI dll name contain more than 2 dot.
7 w/ k3 C# L3 K! K: x6 t- A. a Y914036 CAPTURE LIBRARY ENH: Option to delete a corrupted part from a library and leaving other parts intact in the library.1 l% X+ f6 G! [1 w* x: M7 J
914679 ALLEGRO_EDITOR INTERACTIV Custom toolbars are not retained when switching between brd to dra and back to brd file using the File > Recent Designs
/ d. u# N5 Z# x7 H. T0 a5 u* b2 \: U% E914870 MODEL_INTEGRIT OTHER mergedml fails to merger 2 DML files from the model integrity$ E' O! g! u; w* t
915645 ALLEGRO_EDITOR MANUFACT Allow the user to place the cross-section chart at a desired location& g2 y6 K/ c }. y' K% w1 _
915653 ALLEGRO_EDITOR INTERACTIV unable to delete non-etch shape7 }" p5 ?* R0 j
915711 ALLEGRO_EDITOR MANUFACT dimensioning tolerancing by limit not working) V% e0 V# S. @) V" r; O- x: x
916321 CAPTURE GEN_BOM letter limitation in include file
, Q9 a" `! B* x5 V# i l3 L916907 CAPTURE SCHEMATICS 揂uto Connect to Bus� should place the wire through non-connectivity objects
6 e( {$ f5 N/ @6 ` B6 u920327 CONSTRAINT_MGR ANALYSIS The TotalEtchLength predicate in Constraint Manager does not work for a netclass with a bus.
+ K2 M3 t( ^ E1 r0 Y; E* q8 a920753 ALLEGRO_EDITOR GRAPHICS If I confirm to padshape with zoom-in after install the s002 It was changed to wrong shape.
& ~# V# t' Q: o921097 ALLEGRO_EDITOR GRAPHICS Padstack seen partail filled when Zoomed in even "static_shapes_fill_solid" is set
1 A; Y8 p$ K- t9 C4 C5 B0 h( }; k921226 ALLEGRO_EDITOR DRAFTING Unable to select Package Geometry class when dimensioning in the symbol editor.
. o3 \- s" h, }1 T% v# M, M921623 ALLEGRO_EDITOR GRAPHICS Bug : Symbol not visible when zoomed in 16.5 S002! ~ Z2 ?, f- X
921891 ALLEGRO_EDITOR DRAFTING dimensions are lost after downrev(ing) a SPB 16.5 design with associative dimensions
3 n/ \' Y4 E+ V e& A. t* h921937 ALLEGRO_EDITOR COLOR Padstacks with shape symbol are not showing correctly
9 E6 M, ]- E- s5 c/ o922066 CONSTRAINT_MGR ANALYSIS Custom measurement Actual not being cleared when layout changes.
: Q$ V* D. J% L% y* z) T1 i+ A/ `922117 PSPICE PROBE Label colors are not correct in Probe2 l& \, m$ n6 `- M1 k' m
922519 ALLEGRO_EDITOR SKILL add_bviaarray command fails for some clines but not all
; a1 L2 G6 H6 G- p, h8 u923224 ALLEGRO_EDITOR GRAPHICS Thermal flash Display problem in Allegro v16.5 Hotfix S002! M" j- z% @" b# P
923286 CAPTURE DRC DRC markers not reported for undefined RefDes
) ]- h4 N1 \! Z) X923362 ALLEGRO_EDITOR PLOTTING Print to Postscript file not correct in 16.5
) f# y t2 A. E6 i923416 ALLEGRO_EDITOR PAD_EDITOR Pad Designer crash on clicking on the Arrow before Soldermask_top3 z( t- F" r9 |3 ^0 J$ \
923507 CONCEPT_HDL CONCEPT-PCBDW The function of Import Design in the SPB16.5 Design Entry HDL (for data of ADW15.5_S23 + SPB16.3)
; M/ U4 {* u i7 d923910 CIS PART_MANAGER Copy & Paste operation from Part Manager copies properties only to first section of the part., b# C0 |. m8 }1 ~! C) A5 J
923913 CAPTURE PROJECT_MANAGER Capture runs slow on attached design
2 P, b' @0 D$ K0 X1 x' Q; N$ z923937 CONCEPT_HDL CORE Back annotation time significantly increased with the metadata generation on
. k: Z6 E' v. f# ?% m, F% z923949 ALLEGRO_EDITOR INTERFACES Incremental DXF_IN gives 'Invalid subclass' error% D0 M3 U5 {3 m- @. G' M
924458 SCM OTHER Project > Export > Schematics crashes
% N% m% b. c, Y' s& _( x, |' [924621 ALLEGRO_EDITOR SHAPE Dynamic shapes are disappearing upon updating them to smooth.4 Z0 @' W8 Y0 c8 }* X. g# n
925193 SIG_INTEGRITY FIELD_SOLVERS Diffential Impedance (DiffZ0) values computed in the layer stack-up is incorrect
6 z9 `6 g; ^9 [0 t& \1 F9 J% h925195 ALLEGRO_EDITOR DRC_CONSTR Incorrect pin to shape DRC error" I8 a: J; |( Y' z6 K' q. {
925338 CONCEPT_HDL CORE This application has requested the Runtime to terminate it in an unusual way
/ B; ~" i/ E, @$ X9 s925435 CAPTURE TCL_INTERFACE Capture crashes if 揝ave design as UPPERCASE� option is disabled.# e! O3 G5 h. I& d; v; I5 y
925530 SIG_INTEGRITY OTHER Why the single line impedance value for Top and Bottom layers are different for this design?
) d4 N0 `9 s7 x925864 ALLEGRO_EDITOR DRAFTING Ability to add dimensioning to different CLASS/SUBCLASS& m- {2 H4 N. ]9 j/ J
925976 ALLEGRO_EDITOR MENTOR mbs2brd fails to import data. p2 S7 X+ A$ Y% y; W7 f/ d0 o% x5 }
926409 SIP_LAYOUT DRAFTING Exporting a 16.5 design to 16.3 will cause the leader/dimesion lines to be removed.
+ U, ?' o% ^' ?- E" N4 |: {926443 CONCEPT_HDL CONSTRAINT_MGR In new 16.3 "035" ISR Concept2cm will crash with error.
+ Y7 U9 S6 n6 Y926503 CAPTURE GENERAL Memory leak Capture/Pspice/ e: B$ y& ~( }: Q6 ?
926553 CONCEPT_HDL CONSTRAINT_MGR CMGR ERROR There is no net in the Cset that has pins matching those in net 1 in the Xnet4 t `8 b5 f$ u0 J
926691 ALLEGRO_EDITOR OTHER Crash while Importing Technology File in CM, with Overwrite Constraints.0 d8 {# O# Z/ M) F, K4 I
926887 CONSTRAINT_MGR CONCEPT_HDL Pin pairs lost after Export Physical
$ F3 C3 V+ g8 v1 g6 Z927159 CONCEPT_HDL CONSTRAINT_MGR Export Physical fails due to errors in ConCM.log when SIGNAL_MODEL injected property is ''
- @" J/ ^5 t1 L$ g) {( ~, G, x, M6 m* }% O
DATE: 08-19-2011 HOTFIX VERSION: 004" ?! v8 ~/ J4 [! {; e
===================================================================================================================================
0 S6 P$ G8 g2 [* a4 `CCRID PRODUCT PRODUCTLEVEL2 TITLE1 R V+ E9 G& P; T
===================================================================================================================================& F( |# j9 h7 D4 E
785417 CONCEPT_HDL COPY_PROJECT copyprojectui crashes with a Windows runtime error8 {, R4 }( Z' G" ]* M8 [+ [
851044 CAPTURE GEN_BOM "Export BOM report to Excel" does not appear in the Standard Bill of Material Window.
; l6 i3 t6 u- A4 S0 y0 _6 S868216 PSPICE MODELEDITOR Encryption of subckt names, internal nodes, comments
- ~& [; d0 ]; h870247 PSPICE SIMULATOR Encrypt a model and simulate it, info about inside nodes being dumped in the probe file/ m* H$ P, j$ R3 _% j$ P
877091 CAPTURE SCHEMATICS Save JPEG, GIF, PNG and other image formats in the database in its compressed form
# R, T/ E+ Q" W7 o894059 CAPTURE OTHER Enhancement: Adding column in edit>browse>parts window
( I. z4 t1 @; u) X895902 RF_PCB OTHER Alphanumerical allegro pin numbers are unusable in ADS 2009 Update 14 A* F( r9 @+ B- L, {+ m
895919 RF_PCB OTHER Round trip Allegro to ADS to Allegro requirement" d% u" n( {! p: R3 @8 R
903102 ALLEGRO_EDITOR OTHER Zcopy shape command for cline seems not to work correctly.: |& v1 ^3 ~' N# s& K. L
905562 SIG_INTEGRITY SIGWAVE Noise margin seems not to be measured correctly with Eye Measure function.
- N# P; o- c5 p2 `* T909469 SCM TABLE ASA crashes when opening project$ f J6 ^6 \( p% C8 v
909595 APD LOGIC Inconsistency between export die text out and show element after pin swap
" f0 x( |2 ?$ t/ f4 _' d911123 CONCEPT_HDL CORE 16.2 Design uprev to 16.5 fails with ERROR SPCOCD-1527 g" m* w, S5 Q) z) y
911569 CAPTURE EE_INTERSHEET_RE Q: Why is capture assigning incorrect Irefs in attacehd design ?3 Y% B, D6 d( n0 T( q
915657 ALLEGRO_EDITOR OTHER Allegro PDF Publisher Mirror capability
1 D: Z H, j" T; @6 j0 J% c, O& d915755 CONCEPT_HDL CONSTRAINT_MGR Cannot view net in SigXP
( u, X% k. i h! V+ @916062 CAPTURE GENERAL Auto Wire Crashes Capture1 e) p2 B7 J8 u6 ~8 D) l
916820 F2B OTHER RF create netlist with problem3 K1 G+ V7 j. _/ M9 k
917967 ALLEGRO_EDITOR REFRESH Update symbol resets refdes location for bottom side components only.8 O' s+ V k# y3 ^* ^& W( s
919343 ALLEGRO_EDITOR PLACEMENT Place Manual is crashing the board file
; m% c, [. R* }919481 CONCEPT_HDL CHECKPLUS CheckPlus isGlobal function is not working2 ^( A" _* `) q( Q
919510 CONCEPT_HDL PAGE_MGMT takes 10 min to insert page in DE HDL J; L# W; u; D3 q$ G
919976 APD DATABASE Update Padstack to design crashed APD.8 G+ m" \ [; ^, ?
920418 SIP_LAYOUT OTHER SiP enhancement to Auto Assign Pin Use to add ability to change the pin use definition6 o! ^' X$ @1 W# F4 P! _
920420 SIP_LAYOUT LOGIC SiP enhancement to Logic Auto Assign Net to display a dialouge Auto Pin Use assignment should be run- p! P0 @6 i1 u
920712 ALLEGRO_EDITOR ARTWORK Program has encountered a problem ... error when creating artwork
. p3 y3 d; E! T$ @7 \920763 ALLEGRO_EDITOR ARTWORK Soldermask gerber missing thru-hole pins
a% Z2 k2 V0 g! t, q! O920976 ALLEGRO_EDITOR GRAPHICS Question regarding the difference in the behavior of 3D Viewer w.r.t. height_min
* e5 T! ]& R' D# y; Q. d7 [- {+ E920993 ALLEGRO_EDITOR DRC_CONSTR Minimum Metal Spacing Error is detected on Same Net
1 m: @0 o* ~0 `) _ y2 Q* A: w921727 ALLEGRO_EDITOR DRC_CONSTR Pad Boundary causing P/P drc to adjacent symbol.4 F5 T4 U U" i5 T
922579 CONCEPT_HDL CORE Xcon file gets corrupted upon Save of Hierarchical design with Global nets tied to interface nets
' M* \- n' Y i2 n8 k, | x/ w922592 CONCEPT_HDL CORE DE-HDL does not report illegal connection when Global Net tied to interface net using an Port symbol and named
5 \3 O: P6 k% v7 N+ G i922758 ALLEGRO_EDITOR DATABASE Allegro crashes while placing second mechanical symbol with route keepin, C! I9 e- b' \4 J ]- ?* j/ e
922839 ALLEGRO_EDITOR DFA The DFA drc display is unstable.
! ] H! c$ C0 {923293 ALLEGRO_EDITOR INTERFACES File> Export> IDX is failing for this design while creating an empty error log.
: O% e4 g* G. Q' r924772 ADW PCBCACHE Import Sheet is not bringing in Parts used in the source pages into target cache ptf
* e1 a+ t; D( z9 u$ Z
8 G5 O. [: s* a+ f$ S I/ A$ YDATE: 08-4-2011 HOTFIX VERSION: 003- e E1 \. v9 H0 n! w! r2 Y
===================================================================================================================================
. Q/ f% K4 {/ f) f; k0 NCCRID PRODUCT PRODUCTLEVEL2 TITLE9 w0 I: k# y$ i+ s! O+ `
===================================================================================================================================
( E4 s7 E8 b# l9 g/ o' X3 O$ P787414 CAPTURE PROPERTY_EDITOR Part value can抰 be moved on schematic if a part has been copied to a new design and not saved yet.1 T4 H6 Z* b3 l' J( v
903898 PCB_LIBRARIAN GRAPHICAL_EDITOR PDV move symbol graphics and Undo causes corruption in graphics
3 t# x9 B# c6 `& r904287 ALLEGRO_EDITOR ARTWORK some cline with arc is missed, when creating artwork.* O# I2 Y" ]: ^
904418 CHANNEL_ANALYS SIMULATION channel analysis sim does not give valid result* m$ _1 W3 H- b7 t
905777 SIG_INTEGRITY SIMULATION User gets popup message that halts an analysis until it is acknowledged: r! k: d1 W; l* L% U% s
906139 SIG_INTEGRITY OTHER Bus sim result were cleared at the next run even if no preference changed.3 n3 P& x& ? e r) O
908680 SIG_INTEGRITY OTHER Extra prop delay due to resistance ]2 R- w, ?3 ]- n4 H+ u6 y+ U$ C
909583 ALLEGRO_EDITOR SKILL axlPolyOperation AND operation is not working correctly.8 ^1 `4 d0 }, |: J5 b4 s
910315 ADW LRM Import Design with ADW causes partmgr and pxl errors( f: k( t& O+ N4 z
910689 CONCEPT_HDL CONSTRAINT_MGR NO_SWAP_COMP warning after uprev to 16.5
7 H, }2 B+ V0 ?" z0 R. B( e7 O911684 CONCEPT_HDL CONSTRAINT_MGR Attribute Definitions are incompatible for attribute 'HEADER'. when attempting to place in 16.5$ A4 l5 u% a) J$ n( z: s& q
912343 APD OTHER APD crash on trying to modify the padstack
r6 d' c3 x( ?: |% {912384 PCB_LIBRARIAN CORE PDV Symbol Editor often freezes when moving groups objects by arrow keys$ p; V/ w9 I, j W
912853 APD OTHER Fillets lost when open in 16.3.
. S: M, b) n7 v8 F. v8 t913586 ALLEGRO_EDITOR ARTWORK Cannot create the drill figures in this design.
+ j1 A# r! N3 s# t/ Z: P914009 ALLEGRO_EDITOR DRC_CONSTR Diff impedance worksheet showing almost zero impedance for differential pair in attached testcase.- o, e/ T5 ?& h. J) Q1 I
914110 CONCEPT_HDL OTHER DEHDL 16.5 Uprev overides property values on hierachical blocks
" N- w" i! I5 M914264 F2B OTHER Cross Probing from DEHDL for global nets present inside block doesn抰 highlight in PCB Editor.% |7 l7 |3 Y; A7 e# g
914309 CONCEPT_HDL CORE 16.5 DEHDL crash on saving the user design' _5 `: o2 }& q& w8 U
914558 ALLEGRO_EDITOR ARTWORK Gerber6x00 output creates unpainted niche in a shape
% J2 s) `* j' O3 r! J914633 ALLEGRO_EDITOR ARTWORK Artwork failing in v16.5 while the same design when downrev'd to 16.3 is working fine.+ Z2 R( ^, q- i+ q
914634 ALLEGRO_EDITOR SKILL IsThrough flag for a padstack is reset; u p1 j7 v3 N+ p% h4 A
914746 ALLEGRO_EDITOR DRC_CONSTR DRC Update repeats takes longer on each successive pass.
@- j" E/ A3 P0 r914962 ALLEGRO_EDITOR SHAPE Corruption with Shape filling. n; s7 U3 e2 W* \2 X
915583 CONCEPT_HDL CORE performance issues in 16.5 compared to 16.3
4 t) N. m2 I2 M4 {915630 PCB_LIBRARIAN OTHER Error when running SI Model Interface Comparison using IBIS models
5 X- h1 ?: z6 G* f+ ]915742 CONCEPT_HDL HDLDIRECT I get a newgenasym error and crash when trying to save the symbol
" v+ D1 ^$ S5 S916154 SCM NETLISTER scm crashes when exporting physical database to allegro
. L0 m4 Z+ C! Z/ o: \6 H* v916448 CAPTURE NETLIST_LAYOUT Capture 16.5 Layout netlist contains errors. x8 Q+ J6 Q0 s
916462 ALLEGRO_EDITOR DATABASE Edit>Split_plane>create hangs Allgro PCB Editor
8 f6 E. I+ u, ]& G# \0 ^' `0 l916469 ALLEGRO_EDITOR REPORTS One Unrouted pin does not show in Unconnected Pins Report, i+ s6 I: c2 h% s1 j
916495 ALLEGRO_EDITOR INTERACTIV Pick selects components from invisible (Off ) layer
4 E2 @2 a7 W, B1 ]916889 CAPTURE NETGROUPS How to change unnamed net group name?' i' I: ^# Q/ e& O/ e
917002 ALLEGRO_EDITOR OTHER Allegro PDF Publisher creates extra circles not available on film4 ?4 e: j; R9 }) q8 {7 g
917434 APD OTHER Stream out GDSII has more pads in output data.
0 Z7 c0 _: M# N2 `) p$ [; ~917739 CONCEPT_HDL INFRA Global Net tied to port is getting split into 2 nets in 16.5, in 16.3 it is treated as a single net
; P ? [ D T+ D- e# k4 e918187 CONSTRAINT_MGR OTHER Missing acGetTotalEtchLength predicate.
- h: N$ U8 I4 {: ]! w0 j; o6 b6 {918576 CAPTURE DRC Incorrect DRC is reported for visible power pins which are connected to power symbol$ q2 P/ U" L6 S" A
* X/ U( w% l0 D
DATE: 07-24-2011 HOTFIX VERSION: 002, k" r6 x- ^, C+ K. A2 y
===================================================================================================================================. e- V; c# @- d
CCRID PRODUCT PRODUCTLEVEL2 TITLE
; k, n- B: z( a4 z===================================================================================================================================3 G8 ?/ s8 O1 j5 M
527444 ALLEGRO_EDITOR EDIT_ETCH Slide command needs to be enhanced for same net spacings
' `5 {% F( u2 D$ {( {! s583257 ALLEGRO_EDITOR EDIT_ETCH Add Connect and slide command needs to be enhanced for same net spacings.
9 [0 P" i; k- t& w( m! t9 I592956 ALLEGRO_EDITOR EDIT_ETCH Same net traces will not push and/or shove each other.; B8 z' j# w U* E4 c6 E5 l
745285 ALLEGRO_EDITOR EDIT_ETCH Requesting a true "shove" in Route > Slide for Same net routing.
8 }+ n% d' ~& t* u773503 CAPTURE OTHER Doing "Mirror Horizontally" creates extra un-connects or extra junction dots in Capture V16.3., }4 u0 V8 f5 c5 W; w& ?4 x
774270 F2B PACKAGERXL Require to ignore space in Pattern setting to prevent duplicated Refdes.( f! x# g% \$ b3 ]9 ^
799984 ALLEGRO_EDITOR INTERACTIV Enhance the Fix command to select just cline segs
8 k7 s8 X8 p# v/ B. C809008 CAPTURE SCHEMATIC_EDITOR New nodes get appeared within the design when we select the design and do "Mirror Horizontally".
* R3 Z, f# g9 }: o0 ^! m810058 CAPTURE SCHEMATIC_EDITOR New nodes get appeared within the design when we select the design and do "Mirror Horizontally".
0 Y' k e( {( y6 L! N+ \! F+ M) i821133 ALLEGRO_EDITOR MANUFACT Output artwork for pad data that are suppressed unconnected pads with Gerber 6x00 format
& g" P. \/ G8 G0 ~/ z7 n( c% V831710 CAPTURE SCHEMATIC_EDITOR Capture adds extra junctions to design by itself
4 y3 ~) S( ]5 `% ~& a! F+ E/ O, Y842410 ALLEGRO_EDITOR EDIT_ETCH Ability to slide with "Shove" for "Same Net" segments/vias.
( z" a4 C, r/ K& j854971 ALLEGRO_EDITOR INTERACTIV Capability to add cline segment in a temp group
! L, u# y% d5 c, y860772 ADW PCBCACHE Save Shopping Cart (pcbcache) is crashing component browser: ]: ?1 x1 ^( A5 z
867842 CAPTURE PROJECT_MANAGER Capture crash with 'Open File Location"' c. _. n; k) H$ l% M2 R
868306 CAPTURE CONNECTIVITY mirror vertically removes junction creates extra nets. W! P) D) V+ }( V; x1 C
882677 EMI RULE_CHECK bypass_plane_split fail if BYPASS_XXXX_EFFECT_DISTANCE
& K, q$ N8 W2 e891439 ALLEGRO_EDITOR INTERACTIV moving cline segments3 |" Z) d5 y1 ?5 S
893544 ALLEGRO_EDITOR INTERFACES IPC-D-356A netlist issue with BB vias.
: J/ O' Z d; w# A893765 ALLEGRO_EDITOR PARTITION Mail command not sending out email on Linux platforms.0 _7 F0 K. ^5 |9 N2 K* s! r5 v
894390 SIP_LAYOUT EXPORT_DATA Generate all balls in the xml file for export to EDI's readPackage command
8 ^6 p4 I/ K8 _1 l" Q" b895933 APD DATABASE Update Symbol shifts the center of the Dynamic Fillet and creating DRCs
* q* x8 D& S2 j896598 ALLEGRO_EDITOR PLACEMENT error message is misleading, G6 q r; R$ w2 x! @
897196 CIS LINK_DATABASE_PA Schematic Contents are not shown in CIS window while link Dbase part for parts placed from library; H. I: i3 p4 ]2 x7 [2 b, K6 |4 l
898598 ALLEGRO_EDITOR MENTOR Negative planes from Mentor Board Station not being translated.
) z7 h' A, o7 y+ N% A' a5 {899556 ALLEGRO_EDITOR ARTWORK Import artwork seems not to work correctly.0 J- q/ O9 z1 R u$ j
900501 ALLEGRO_EDITOR PLACEMENT "lace Replicate Apply" is showing lot of DRC's during placement of replicated circuit in 16.5
* ^" @7 P7 @' v: X/ _2 w; }901141 CIS EXPLORER Japanese character appear garbled in CIS explorer window.- }; ?4 O) g9 }' s
901666 CAPTURE OTHER Home page of Flowcad-Switzerland and Flowcal-Poland is not preserved on captre restart on start page
2 J/ v+ [" v: E8 H& W/ `2 s902066 ALLEGRO_EDITOR DRC_CONSTR Shape in Region not follow the constrains
: Q) Y8 G6 |; |: y! \902349 CAPTURE LIBRARY Capture crashes while closing library% W* T+ e" z( Q9 |2 v+ P) S
902508 F2B PACKAGERXL SPB16.5 Packager-XL consumes much more memory than 16.3
' }5 w+ |0 {' `) b% M7 Y0 [+ y4 X902841 CAPTURE GENERAL Capture Start page does not show' y0 J3 V0 u) Q$ N
902876 F2B PACKAGERXL Packager fails on the design upreved in 16.5
% l( p& G- z/ ^2 z' X902959 CONCEPT_HDL HDLDIRECT HDLDirect Error while saving design0 p& U* w1 ^( N* X' P
903171 PSPICE NETLISTER Why Capture is treating hierarchical power ports as floting nets in complex heirarchy designs?
2 j* o& l& [/ \, R' x; _: m x) z1 Z903713 ALLEGRO_EDITOR PARTITION Placement Replication do not work fine in the Design Partition
! _& v P o4 y. z9 P3 D4 P903799 SIP_LAYOUT DIE_EDITOR Disappear die pins after exiting co-design die editor5 X- f" [, C1 h: O" }8 ~0 O, x$ F
904021 ALLEGRO_EDITOR OTHER Export PDF from SPB 16.5 produces a file not text searchable% D, @/ a4 M4 T( t O. V1 B
904339 CONCEPT_HDL CORE new design crashes using the attached CDS_SITE
; G' v! H1 T) A$ I904522 F2B PACKAGERXL Part will not package in 16.5 but packages in 16.3
* r4 Z" ~" }9 |- q$ z904764 APD OTHER Enhance Scale Factor of Stream Out to support 4 decimal places
- M0 v `, ~6 Y904771 ALLEGRO_EDITOR MANUFACT Pin Number display issue.
$ D" i) q3 N) Y7 ^& j: p- r! c8 b& ?, s904853 ALLEGRO_EDITOR GRAPHICS Enhancement for showing Static shape as it was seen in 16.3
+ I; a" g. n. j905144 CONSTRAINT_MGR ECS_APPLY Min Line Spacing is larger than Primary or Neck Gap less(-) Tolerance but No Warning in CM* j$ ?* O* ^, ~" z! [
905314 F2B PACKAGERXL Import physical causes csb corruption
i8 g( a( f1 T% p% j: f& Z! n905337 CONCEPT_HDL CORE ConceptHDL crashes after Import Design process.: J% C1 b' G* x* a
905533 ALLEGRO_EDITOR INTERACTIV Pin numbers for components on BOTTOM Side are moved in Preselect mode,when the BOTTOM layer is invisible; h+ o! S# @7 X1 s/ C6 A2 t% {
905796 CONCEPT_HDL CONSTRAINT_MGR Fujitsu CM issue inaccurate concept2cm diff pair issues9 D) H7 j/ I9 w$ P& d3 n2 X- z
905811 CAPTURE EE_INTERSHEET_RE interesheet references in the form of grid grid page number instead of page number grid2 C& | } `/ `/ H) v# _
906118 CONCEPT_HDL CONSTRAINT_MGR Cannot open CM if SIGNAL_MODEL value was not assigned in ptf.- o' L; R% W2 N; A2 F# ?
906153 ALLEGRO_EDITOR SCRIPTS Unable to run allegro script in batch mode on the attached board.
' v4 b4 q$ k: e. E8 R( A906182 APD EXPORT_DATA Modify Board Level Component Output format
0 q5 G+ O$ X1 j5 W906200 ALLEGRO_EDITOR DFA Enh- DFA drc invoked in Batch mode returns false constraint value in Show Element. Z. P5 l8 L. k* C
906517 PSPICE PROBE PSpice new cursor window shows incorrect result.7 X" E; C; L8 _ H
906627 ADW COMPONENT_BROWSE ppt options are not read if ucb is launched from FM. works fine if launched from dehdl./ J( ]! X/ C" K+ v; p2 P
906647 SIG_INTEGRITY LIBRARY lib_dist creates a signoise.log in current directory (with backup files like ,1 ,2 etc.) on each run
8 M, o$ J4 \" k1 U- G F V& y906673 F2B PACKAGERXL Ignore the signal model validity check during packaging9 g& M+ [2 i+ R8 v3 t9 }+ r' p
906688 ADW LRM A copy of source design gets created in worklib of target design after 'Import Design'
: m. |- ]& G8 c1 x3 I3 }& p; q: Q906750 ALLEGRO_EDITOR PARTITION Importing design partition removes the testpoint reference designation
! j7 j1 U B9 Z K& }3 g906874 PSPICE NETLISTER Error less than 2 connections for unconnected hierarchical pin
% \3 b- @, A- A$ j# d907095 F2B OTHER Part Manager does not show Error as Undefined when directive ptf_mismatch_exclude_inj_prop is used
: h1 C# \+ u S7 S# h: I9 _4 _907424 ALLEGRO_EDITOR GRAPHICS Allegro add option for pre 16.5 shape display* G. I% C- z! g" Z* ~5 t
907490 CAPTURE NETLIST_LAYOUT 16.5 Layout netlist is not correct. It differs form 16.3 layout netlist.
$ V. ]2 I6 H: A0 \$ s907884 SIP_LAYOUT MANUFACTURING Need to add an "NC" pin text option for "Manufacturing Documentation Display Pin Text"3 H+ B# x9 G. f$ f0 j* g# N
907885 SIG_INTEGRITY OTHER Matchgroup targets lost when importing netlist to Allegro layout in HF31
3 x! v' Q# s( a( s: G0 |907929 CAPTURE TCL_SAMPLE TCL command to delete a property from parts in a library is not working correctly; h3 P0 J2 K" O" Y! v" b
907933 SIG_INTEGRITY OTHER Single line impedence not working in OrCad PCB Professional# X9 w2 C7 V6 h, G6 Y; w
907963 CONCEPT_HDL CORE Design uprev issue when moving from 16.2 to 16.5
) O/ X2 u! B1 p, Z908000 SIG_INTEGRITY OTHER Inconsistence z-axis delay reported on Tpoint when define at via location., J) a% `- Z5 q6 |( l6 P5 K
908057 CONCEPT_HDL CORE DE HDL crash with the cut and paste of a signal name
& E: `. T9 F! H; F) A908060 CONCEPT_HDL CORE CTRL+LMB Option not working correctly in 16.3$ D0 U1 h5 |' [# W" x: B
908210 CAPTURE CONNECTIVITY Connection is being lost while dragging a component8 R) L9 w8 C$ |1 e; T
908241 CAPTURE DRC DRC error column is blank in DRC markers window in 16.5 D$ Q; n; O! B/ _
908339 RF_PCB BE_IFF_IMPORT mechanical holes VIAFC are not at the right place
# u' q. a0 g5 S f# u5 o1 t908534 SIP_LAYOUT SYMB_EDIT_APPMOD issues with symbol editor and copying pin arrays
( v2 P8 M& O/ d& }# c! Z908535 F2B DESIGNVARI When I try to view my variant file the variant editor crashes, ^5 s5 O$ |) g2 ?/ W
908595 APD 3D_VIEWER cadence Design 3D viewer" screen pops up and is all black because the colors have all converted to b
# I6 a. h" j4 E+ o8 B' b908849 CAPTURE ANNOTATE Getting crash while annotating the attached design! M Y f! r3 H, O3 K6 ]
908874 CONCEPT_HDL CORE Part Manager - No Part Found error when using CCR# 775788 feature
& g' I" h2 K9 r' B6 j909077 CONCEPT_HDL CORE After packaging pin numbers remains invisible even when $PN
: n& \9 J% l* \909104 ALLEGRO_EDITOR SYMBOL Warning message needs to be modified. It does not save the symbol and also not tell the actual problem.8 F7 b# Z4 N2 ]. ?- I
909417 ALLEGRO_EDITOR REPORTS "report -v upc" returns 'Segmentation fault' on Linux) z/ Q/ p7 x: V' z& t1 o. o
909635 SIP_LAYOUT DIE_STACK_EDITOR Add Interposer crashes in SiP Layout( S+ v) R z, C; |
909749 ALLEGRO_EDITOR MANUFACT Allegro Crash during dimensioning, A' [7 A1 T) G, f9 W: \# E5 u6 H
909760 SIP_LAYOUT MANUFACTURING Create bond finger solder mask doesn't follow the mask opening as defined in the padstack) x. y7 m! |* c7 m5 o" ^
909861 F2B PACKAGERXL NetAssembler broken within the latest 16.30.031
; }' r( S5 [& l: F1 {/ `910006 CONCEPT_HDL INFRA Motorola design fails to uprev from 16.3 to 16.5, xcon file is getting corrupted.
8 n, B# j$ u$ J* k8 t910141 CAPTURE NETGROUPS Modify NetGroup definition does not update Offpage Connector- a+ Q* h' O/ R' K$ y+ R
910340 ADW LRM Import design in schematic, only 1 page import, the entire block is getting imported.
: K) S4 j. F2 z" q9 {% D910678 SIG_INTEGRITY OTHER The Analyze> Model Assignment> Auto setup is not creating/assigning models to discrete components in 16.58 N$ a2 O' W4 o# @
910713 F2B DESIGNVARI Variant Editor crashes when you click web link under Physical Part Filter window.
1 D+ @, I: n1 w910936 F2B PACKAGERXL ConceptHDL subdesign net name is inconsistent5 q6 r& Y* o' Z1 |4 ?5 m
911530 ALLEGRO_EDITOR SYMBOL Package Symbol Wizard does not create symbol with the name given
+ P( d: p, L: H911631 CONCEPT_HDL CORE DEHDL crashes when opening a design
- R/ E* G% j) C8 {912001 ALLEGRO_EDITOR OTHER option_licenses entries are made in allegro.ini even when not set as default4 c. I$ P8 B; Q4 s" \4 j7 M
912459 F2B BOM BOMHDL crashes before getting to a menu
! a5 W% A, v6 k9 w, b) U- Q4 |. z913359 APD MANUFACTURING Package Report shows incorrect data
1 M5 H' E ~. c( X- P7 o" i6 H G9 J0 C w- _
DATE: 06-24-2011 HOTFIX VERSION: 0011 T8 t7 z% M0 ]# B. m& D
===================================================================================================================================
! G4 n; z& g) n, i+ lCCRID PRODUCT PRODUCTLEVEL2 TITLE
" m( q' `. r5 E& n===================================================================================================================================. y6 c* X9 Y9 ]5 u/ y! t
293005 ALLEGRO_EDITOR DATABASE Allegro crash when attempting to move mech. symbol' C% D" n c* s i2 \: g( l
298289 CIS EXPLORER CIS querry gives wrong results
( j; K+ M8 x- v E8 D6 _366939 ALLEGRO_EDITOR OTHER Cannot attach refdes on silk subclass with add text6 P0 i2 t J" w; |' I
432200 ALLEGRO_EDITOR MANUFACT Fillets with an arc are required for Flexi designs
, h) R) P, T9 p2 D" u443447 APD SHAPE Shapes not following the acute angle trim control setting.0 J5 p4 z# ~' u0 ^ Q f2 ]) c6 S
473308 PSPICE AA_SENS Passing variables to lower level blocks using subparam2 S3 k. [: B0 o
517556 PSPICE AA_SENS Advanced Analysis does not support variables being passed down the hierarchy
3 {: u% [6 G2 B) I2 ]548143 ALLEGRO_EDITOR SHAPE Dynamic shpe on Etch TOP will not void properly.
) f* B( g0 H/ \9 H' ]606959 ADW COMPONENT_BROWSE Key properties with blank values are not getting read in shooping cart& w" S7 g! `) b* O; U/ j7 x2 v
616466 ALLEGRO_EDITOR SHAPE Solid shapes are not getting filled) ?% h! q" Z; p- p1 ^1 e; Z: f
641358 SIP_LAYOUT DIE_STACK_EDITOR Request for Via and Multi Layer Pin support for DIE stack Area (blue region)$ q- _; P2 ^) Z8 b- J5 u
644122 SIP_LAYOUT OTHER SiP Layout - xsection - ERROR Adjacent conductive layers are not allowed, but these are diestack layers not conductor$ w! y+ }% N) Q: W+ z( S$ g+ D
645816 ALLEGRO_EDITOR SHAPE Slide a cline all removes gnd shapes on board
" P; D# L9 d& i4 f' y725355 ALLEGRO_EDITOR SHAPE User can not voided Logo correctly.
% R. T8 q6 Y6 n& z# [4 J! c/ W763569 CONCEPT_HDL CORE Display status of Hide/Show unconnected pins icon in DE HDL UI( R5 I; C) l" m( F
770021 CAPTURE BACKANNOTATE Changing pin group property after pin swap resets pin numbers
- X$ r+ a1 B$ k7 o! X* a+ E/ C792126 CAPTURE PROPERTY_EDITOR Attempt to change display for occ prop resets4 A9 h' W& o: G* C0 d" L
799014 CONCEPT_HDL CONSTRAINT_MGR concept2cm errors not shown in export physical after hier_write2 o* ?! j T% X' E# u
803147 CIS LINK_DATABASE_PA Link DB part should not change RefDes of multi package part+ x- { H1 i+ b/ i
804240 PSPICE DEHDL Problem in simulation result for a multi-section split part.9 B2 i" R9 `$ a* I& J
809118 CAPTURE NETLISTS ENH to compare two schematic Capture designs! Q, s9 f6 H7 N3 O
816568 ALLEGRO_EDITOR SHAPE shape disappears when update to smooth.. State no etch0 \* N, { Z/ K6 u5 ?# `. v2 V
830053 CAPTURE STABILITY DXF export fails if schematic folder name as /. Q5 r% Z& ]' l# t
832108 ALLEGRO_EDITOR SHAPE Shape void incorrectly.. _9 `" _; s& J8 ^+ L0 f
833542 CONCEPT_HDL CORE PDF publisher font is NOT WYSIWIG with respect to what seen in DE HDL: L/ Q0 s B7 p$ g' t5 c. o
835777 CIS DERIVE_NEW_DB_PA For XLS, donot display table as worksheetName$worksheetName to avoid 8012 error
, ]* B* L2 a3 s( [837640 CIS GEN_BOM date format of CIS BOM has broken macros of 16.2 in 16.3 version. b/ @& Y" J" S1 q* V* V5 G9 w
844074 APD SPECCTRA_IF Export Router fails with memory errors.. ?+ B0 O' _0 R! h7 F6 Y
851595 CONCEPT_HDL CORE Pin numbers overlap on the pin and increase in size
9 p8 X; @2 s! x4 A3 [1 m: k852832 CAPTURE BACKANNOTATE Why is Capture crashing with Mentor back annotation?" C3 y$ r3 Y7 F4 H9 S
855015 ALLEGRO_EDITOR OTHER The rats are NOT connecting to the ends of the clines like they should be.: F6 Q* A, F8 d5 A- c8 G+ X
859883 CAPTURE NETLISTS ENH to compare two schematic Capture designs
, {8 _+ p( S9 y) }3 K$ e8 N, l: C866009 SIG_INTEGRITY OTHER Net with Pull-up/down should not be used for Diff-pair.
4 e9 H4 ~) s& |! ^; V* j866830 SCM REPORTS Multiple lines added as separator between title block and report header instead of single line
9 Z8 k/ Z4 h2 z& L. X+ L/ T) M! X866833 SCM REPORTS Extra indentation is left in the left side of the report when the Line Numbers are set to OFF* v6 P* z2 \* @: Q9 l$ @9 m& r0 h1 B
868618 SCM IMPORTS Block re-import does not update the docsch and sch view; V8 ~1 N! b5 Z0 [; \
873402 SIP_LAYOUT LOGIC pin swap for co-design die in SiP
' D: L$ S, \/ A5 V) |874010 SIG_INTEGRITY OTHER PCB SI crashes when the Xnet is extracted with VARIANT_TO_IGNORE property.) s4 I. _; i; r% z
874400 ALLEGRO_EDITOR INTERACTIV Flip mode issue with move command; t, b1 N; Q: q2 C0 ~- M8 g
874966 ALLEGRO_EDITOR INTERFACES Placed mechanical component do not get Ref Des or part number in IDF file
! e& o' @- r4 R875709 ALLEGRO_EDITOR REPORTS Film area report generated incorrect data at l16 s% `, T# P$ ~8 @
876275 CONCEPT_HDL CONSTRAINT_MGR Constraint Manager not retaining target net
% }6 w. I7 x- x& v7 ~879361 SCM UI SCM crashes when opening project
8 K8 d( T7 r' _0 g* X5 l; r879496 CONCEPT_HDL OTHER Customer wants to have the tabulation� key as separator in HDL BOM.; p& g+ v" ]/ r& O2 c) W
879514 PSPICE AA_MC Monte Carlo to handle equation as comp VALUE.
! h( G1 |) p: f881845 ALLEGRO_EDITOR SHAPE Delete island deletes complete shape
, v* m3 h, l3 y, }882413 PDN_ANALYSIS PCB_PI PDN Analysis should support routed power nets% D; K1 U1 A* t8 r* V
882427 PDN_ANALYSIS PCB_PI PDN Analysis target impedance should have a variable multiplier
0 l) I5 b2 n5 y# A- a882567 SIG_INTEGRITY OTHER PCB SI crash if boolean type prop was specified to VARIANT env.
6 h8 T4 Q! L. Z882644 ALLEGRO_EDITOR PLACEMENT PCB Place Replicate Function automatically match Enhancement
2 O- L9 _! I9 {0 a0 J883164 ALLEGRO_EDITOR INTERACTIV Vias marked fanout moves away from position when moving component
1 \, J% @4 F. v883224 SIG_INTEGRITY SIMULATION crash while reflection simulation from Constraint Manager
5 O0 L/ A. D% n7 Q$ U883760 PCB_LIBRARIAN METADATA Incorrectly formatted revision.dat file in the metadata folder; Q$ r( i% i$ S9 A* X
885391 SIG_INTEGRITY SIMULATION RLGC data sampling algorithm and w-element interpolation.
2 c( Y1 }; B2 \. x885849 ALLEGRO_EDITOR MANUFACT Silkscreen Audit cannot find Solder mask for the text string
! D9 ] r3 `- k+ G/ y: |+ U5 w) T% }6 l885996 SIG_INTEGRITY OTHER The effect of sn_maxwidthlimit user preference is not seen in cross section impedance calculations
, d; R- l( u/ U886090 ALLEGRO_EDITOR INTERACTIV Add Arc w/Radius does not snap to grid
" p5 O! I( s5 M4 b887180 CAPTURE SCHEMATIC_EDITOR Signals Navigation window doesnt get updated for Buses3 o. W7 ]7 m, U& x9 t
887442 APD SHAPE Copper pour of Dynamic shapes on Top layer which contains many existing signal traces fails./ _4 v+ l9 u% F3 N8 v2 I1 j
887578 SCM AUTO_UI Component Replace pops-up the DSPANE-204 Message) m7 e9 ?: M$ n& m/ @$ \4 a( k
887926 SIG_INTEGRITY GEOMETRY_EXTRACT Field solution failed if diff trace on bottom doesn't have reference plane.
+ {2 N! F# ^, x( ?888414 SIG_EXPLORER OTHER View Trace Parameter display the thickness of dielectric incorrectly./ C0 w& ]8 l" b
888600 CONCEPT_HDL CREFER Cross References not added to Schegen schematic
* z6 ?! p# ]! [+ X! b# }, m& N888679 SIP_LAYOUT SHAPE Can't create the Dynamic shape on layer M1_sig without unwanted horizontal openings appearing.* r6 t+ N# }( [
888804 ALLEGRO_EDITOR OTHER Fillet will become static shape after import from partition board.
, c4 r9 X: g$ m; w( J888945 CONCEPT_HDL OTHER unplaced component after placing module( \7 p- m# d+ r! j0 `
889222 ALLEGRO_EDITOR SHAPE Allegro freezes/hangs when adding shape as Polygon with OpenGL ON.' @) `7 B3 ?6 l% v
889365 SIG_INTEGRITY GEOMETRY_EXTRACT top/bottom trace impedances extracted to sigxp are wrong in 16.3
- ]6 K' w- Y7 T: w @9 i" j# R889404 ALLEGRO_EDITOR OTHER Incorrect pad size for Top conductor padstack written to column 59-62.3 Y) N$ q( j8 O6 n$ j: H& N
889426 CONCEPT_HDL CHECKPLUS CheckPlus does not find single node net5 l) t) X* l" N: _
889636 ALLEGRO_EDITOR MANUFACT Incorrect spelling of "Visibility" in "Film Control" tab in the Artwork Control Form
: B/ `/ K; ^2 o h891235 F2B PACKAGERXL Packager crashes without creating a pxl.log file/ Q/ U5 _# g0 J- t
891292 ALLEGRO_EDITOR SHAPE arc routing causes weird undesireable shape fill performance
1 P3 ?: m/ S8 @$ Z/ Q' R0 P891856 ALLEGRO_EDITOR EDIT_ETCH crash when sliding diff pairs
( \. O0 `0 v& a: m892375 ALLEGRO_EDITOR PLACEMENT Place Replicate Update disband other groups, irrespective Fixed property added or not.
4 r& e! u3 |8 _% e892455 ALLEGRO_EDITOR SYMBOL Why the overlapping pins are not reported with DRC?6 C- J/ T6 d3 E
892541 SIG_EXPLORER OTHER Export/Import layerstack through the technology file is changing the layer thickness ^* n" x( ^9 n7 c
892766 APD WIREBOND Excuting Finger moving cannot push aside finger to move with together by shove all mode" ]4 r2 P A- N* I9 ~, {( I) J0 U
892907 ALLEGRO_EDITOR DRC_CONSTR DRC not reported for etch_turn_under_pin violations4 ^" S' r1 ^9 V+ }# p' M& z' a
892963 ALLEGRO_EDITOR SKILL Bad shape boundary created after axlPolyOperation 'OR
& b! v2 {8 M/ M1 y: n892964 SIP_LAYOUT LOGIC Request that Edit Parts List use Dashes "-".6 W% K% r7 x7 t; E
893295 APD WIREBOND Why move wirebond command does not shove wirebonds? This result in drcs.
# v. I9 i7 X4 ?1 K0 n893706 CONSTRAINT_MGR OTHER On line DRC hangs on partitioned board& z" ~4 w- p# ~
893743 APD EDIT_ETCH Route behavior when spanning pads not as expected.9 j1 z/ h7 A" G3 v+ O
893783 SIP_LAYOUT OTHER Padstack Design Editing update File menu with a Update to Design and Close instead of 2 operation5 a5 f; e. ?8 E0 o( Z+ k4 j4 K1 M
894456 ALLEGRO_EDITOR REPORTS Request Net names be added to Propagation delay lines of the DRC report.
0 q& F$ l5 d4 D894499 SIG_INTEGRITY LIBRARY Tool crashes when moving a cline or selecting the Info icon with OpenGL on.& P7 ~7 E" {: P
894582 APD SHAPE When making a dynamic xhatch Via shapes surrounding are abnormal.
X K3 r# C4 y1 `7 V6 q' O895542 SIP_LAYOUT WIREBOND SIP design crashing when moving bond finger using blur mode BLUR_BONDFINGER_PRESRV_CON
0 e- {5 o* F" y- M# I: h0 ~895591 ALLEGRO_EDITOR PCAD_IN Importing PCAD file fails to get to the point where we can map layers7 E$ Y" E& L: \5 I: S1 O7 c; Q
895757 APD ARTWORK Import Gerber command could not be imported Gerber data
. n; K2 K9 g8 r& A895964 CONCEPT_HDL CHECKPLUS The CheckPlus command getFileSubstrings is not working correctly4 U$ j+ X @) D
896428 SCM UI Changed Ref Des value not maintained in DEHDL block when part is replaced
* g: \2 H$ O# {) G9 f896655 CAPTURE EDIF Import/Export Design of Hierarcy design with OrCAD Capture# E4 Z" {8 D$ b/ L5 ]& v1 ~
896846 CAPTURE IMPORT/EXPORT Import edif2cap and capture is crashing
! _- s5 g0 w9 S% K; T$ x897155 ALLEGRO_EDITOR REPORTS Copper coverage in L2 and L7 looks like the same but film area report had large gap./ h1 v0 V5 c) H8 V+ h8 v
897654 CAPTURE EE_INTERSHEET_RE Capture crashes on adding intersheet refernces in abbreviated format on attached design.: w/ z& L) a# V A6 w2 z
899344 RF_PCB BE_IFF_EXPORT dlibx2iff does not provide the component boundary drawing/ n' F" U- ^5 r7 @+ B
899629 CONSTRAINT_MGR OTHER ECset for Total Etch Lenght is not present in OrCAD Prof
7 e% p. o( i# R* [900175 CONCEPT_HDL CONSTRAINT_MGR Few Xnets are lost from Match Group after packaging and importing the netlist to board file.
% ?; J4 }. n- Y2 k: O6 M900481 CONCEPT_HDL CORE Genview creates a larger symbol without taking the no. of pin in consideration- T! W0 e$ x4 I& j" C% E1 \
900813 ALLEGRO_EDITOR DRC_CONSTR With rotated pads, pad (pin - via) soldermask spacing DRC is unreasonable.$ I* V) t3 n( v7 J# ]- |
900905 PSPICE STABILITY Simsrvr crash and RPC Server unavailable error while running simulation.9 }2 g; O: ~( k9 O
901783 CONCEPT_HDL CORE CDS_PART_NAME is annotated on the schematic canvas after running back annotation in 16.50 ]( ~5 U$ R& f# I; q
901909 APD EXPORT_DATA The "package_pin_delay_length.rpt" with Z-axis delay turned on seems wrong, |& I' Q' R: G2 c' r5 R
901987 CONCEPT_HDL OTHER SPB16.5 zoom fit does not center the page while ploting the schematic page# I6 v6 k$ `' W; K1 q' f7 p7 j
902133 CIS OTHER The visible part property value are being shown very distant from part graphics on schematic
3 j0 G: q0 i5 s6 n+ I- _902166 SPECCTRA ROUTE Specctra crashes when reading in "bestsave.w" file
3 a3 G0 Y: Y! o) P {. c1 h' T" q, y N902170 ALLEGRO_EDITOR DATABASE Diffpair Issues with OrCad PCB Designer Professional
9 l- a2 b+ m% I! H$ a) B902177 CONSTRAINT_MGR CONCEPT_HDL Option to view the layer thickness in CM worksheet through worksheet customization
) { m9 f# d7 a; b* a, N+ @902463 ALLEGRO_EDITOR INTERACTIV APD crashes when we click ( show element ) on certain components
+ r! a# m4 Z) w$ r3 v. Y902621 CONCEPT_HDL OTHER Design Differences (vdd) Crashes
. h C6 U" N7 b2 M902909 APD WIREBOND die to die wirebond crash+ H2 V4 ?) }% G# N) ?- t
902933 ALLEGRO_EDITOR PADS_IN Pads_in fails while reading PADS ASCII file body
4 N a, p/ ] [7 p: o, T903284 PDN_ANALYSIS PCB_STATICIRDROP IRDrop voltage gradients are plotted outside of the PCB outline
; \$ L& L; H; E903680 CONSTRAINT_MGR ECS_APPLY Constraint Manager not passing all hiearchical member objects to a custom measurement.0 x8 C! a. }) k# W2 o
904403 ALLEGRO_EDITOR DATABASE Allegro crashes when refreshing module |
评分
-
查看全部评分
|
[复制链接]
/1 
发表于 2012-2-21 14:58
收藏
淘帖
支持！
反对！
