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DATE: 02-17-2012 HOTFIX VERSION: 016/ W* R( [) H b' _7 Z# E7 ~" h
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0 k' u9 k9 }! kCCRID PRODUCT PRODUCTLEVEL2 TITLE4 }! f4 }) k0 `6 ?: _7 m$ A
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/ ?% l5 c% K# T7 r, {3 I) _6 b$ R8 k840105 PCB_LIBRARIAN USABILITY PTF subtype is getting changed when Save As option is used in PDV
% M! V8 J H; f. U) o& T873075 Pspice PROBE Decibel of FFT results are incorrect.
2 }$ q! b( V% W5 O) _. o938744 ADW COMPONENT_BROWSE Need ability to customize shopping cart columns to include any Part property9 D7 M. z* h; A: N
943003 SCM REPORTS The dsreportgen command fails with network located project
# P3 y) b, f3 t- c7 X961530 allegro_EDITOR INTERACTIV The problem of Display measure command
7 M3 |0 {/ l5 G& X% Y: x. U4 w, U962157 concept_HDL CORE Where is the setting for enabling the Enable PSpice Simulator menu?" d; ?2 z. {2 t& y; j5 [
962206 CONSTRAINT_MGR CONCEPT_HDL Import physical not passing all constraints from the board to frontend
D* Z. ~, [+ t$ H968205 PSPICE DEHDL_NETLISTER Change SPLIT_INST property to PSICE_SPLIT_INST for Quad Switch type of design.
0 I) l# g; x% H% G. W968509 PCB_LIBRARIAN METADATA Incorrect pinlist.txt was generated if DIFF_PAIR_PINS_POS/NEG was set.
7 C: \# Z! o& y8 ~969450 LAYOUT TRANSLATORS orcad Layout to Allegro Translator crashes
, d* a6 J( g) x969997 CONSTRAINT_MGR CONCEPT_HDL ERROR(SPCOPK-1053): Cannot find a ppt part that matches the instance pro~
, T3 O$ V5 k" m971193 CONSTRAINT_MGR UI_FORMS Copy and pasting a formula causes the application to crash on windows.
' V ?9 K0 P5 t971601 CONSTRAINT_MGR CONCEPT_HDL ERROR(SPCOPK-1053) and WARNING(SPCODD-66) because of directory structure
: V- g$ h; f. a7 [/ K7 v) J973398 CONCEPT_HDL OTHER It should be not packaged with error while working the packaging process if the design has a ERROR
6 C6 q; i1 @% A7 | [9 j2 j2 l973859 PSPICE ENCRYPTION Pspice crashes with encrypted model
* `, _6 k, b) |2 x( \, V9 s973938 PCB_LIBRARIAN VERIFICATION pc.db is missing5 b: K6 J$ d- s) [
974540 CONCEPT_HDL CORE Graphics updates are real slow
4 f1 [/ D) F$ G/ T S# M974791 F2B DESIGNVARI Variants are not back-annotating to schematic and turning to ?
, I" M& I- \' ~. V974818 ALLEGRO_EDITOR NC Backdrilling produces 0 plunges yet no errors reported.% t% X$ s0 N6 M O1 ?1 `
974945 ALLEGRO_EDITOR skill Why is axlPolyOperation is giving different result and not working# J$ T/ E% g. L, w; m6 F
974946 MODEL_INTEGRIT TRANSLATION ibis2signoise returns the error - Delay measurement fixture must contain V for ECL technology
; t: b/ E5 r; G, ^# q7 s975396 CONCEPT_HDL CONSTRAINT_MGR Constraints are dropped after migrating from 16.3 to 16.5- `3 }! {) ~! e- }* g
975633 ALLEGRO_EDITOR GRAPHICS 'dynamic_layer_visibility' option in 3D Viewer when checked or unchecked should not change (until next change)' O$ Y" X5 v5 y) S) ]
975720 ALLEGRO_EDITOR DRAFTING Datum dimension lines not adjusting to text move
( o) J% T$ b; }# B2 T975745 ALLEGRO_EDITOR SKILL cdsServIpc different 16.2 vs 16.5 when Allegro exits, q5 B b/ m5 n- h9 F
976013 CONCEPT_HDL INFRA Power pin connection of FPGA symbol is missing in netlist.
/ g, M$ a+ ]1 m3 P: N2 a6 N976058 CONCEPT_HDL COPY_PROJECT SCM Copy project does not create the con and dcf files in tbl_1 views3 V* X4 e1 c) Z6 ]6 M* b
976073 CONCEPT_HDL COPY_PROJECT All the constraint data is lost in the SCM copied design0 M$ d; A* ^5 G( y
976160 CONCEPT_HDL CREFER Cref fails due to some Caeviews error in the design
8 `- r" |/ S6 \ k976204 ALLEGRO_EDITOR DRC_CONSTR Application falsely reporting Mechanical Pin Antipad to Shape Spacing DRC( N( U9 r" A. q
976448 F2B PACKAGERXL ERROR(SPCOPK-1069): Invalid POWER_GROUP property value
$ {4 U* S# v- O0 ^+ D; z976521 ALLEGRO_EDITOR DRC_CONSTR multi-thread update DRC causes the application to crash
/ A& T o/ T. P0 k976838 SIG_INTEGRITY OTHER Unable to create XNET for highlighted nets on attached database even after assigning proper Signal Models./ K4 D2 F# r ~+ _6 G# K
977517 F2B PACKAGERXL Export physical fails after update to 16.5 from 16.3
, r: o, E, H, x5 [4 ]6 Q$ F/ c977902 ALLEGRO_EDITOR DATABASE generate module is crashing allegro
. X( w* g: b1 a7 y9 E978652 ALLEGRO_EDITOR pads_IN PADS_IN fails with ERROR: Finished with errors.
) m' `( C3 t* I1 R6 v) l978744 APD DEGASSING Some shapes will not DeGas on this design
; V" p, r4 c- s& K! q8 [% Y9 Z3 I979940 SIP_LAYOUT OTHER SiP Layout Leadframe autobonding with profile selection- A- ^4 V# I/ U: h
981699 CAPTURE HELP Start Page still shows Hotfix 14 after installing Hotfix 15
a5 n% d# f4 Q
. x+ W& H1 F4 T; {4 g4 H, GDATE: 02-03-2012 HOTFIX VERSION: 015- f" O! o! A- J* E" j+ N
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CCRID PRODUCT PRODUCTLEVEL2 TITLE) K/ R% f" _9 O& g, Z; F
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871567 CONSTRAINT_MGR SCHEM_FTB Ability to filter out Single Node Nets from Constraint Manager
o& n% h C- [! a( n' v7 o921436 ALLEGRO_EDITOR MANUFACT Change in 'decimal place' for new dimension changes the already placed dimension( l' `* \ w1 G+ R, E
941433 CONCEPT_HDL COPY_PROJECT 16.5 Copy Project should warn if trying to copy a 16.3 design
: j3 e& ^6 r- E& {! L, h$ S954375 ALLEGRO_EDITOR MANUFACT Change dimension accuracy for few instaces of associative dimensioning
! [# J6 l/ p! t! E' O. p, Z961646 PDN_ANALYSIS EMVIEWER EMViewer Help > About shows wrong version0 C/ j2 u3 X$ v, {" ]
964912 CONCEPT_HDL COPY_PROJECT ASA project crash after using copy project
" s& R. V, [7 ^* K2 W* A967223 ALLEGRO_EDITOR MANUFACT Bug:Oval slots orientation in one direction only6 X: L. E' M4 ~7 D0 Y) h
968865 SIP_LAYOUT DIE_ABSTRACT_IF load of die abstract fails due to differences between component and symbol
2 Q1 d/ f. Q% N$ M W/ F& q969485 ALLEGRO_EDITOR SHAPE Shape does not update correctly in 16.5
V9 r' r; w8 D6 S. V+ \970331 CONSTRAINT_MGR ANALYSIS Impedance worksheet shows a zero value for impedance
8 U% g1 F" [1 }0 U/ H, e. ?; V970600 SIP_LAYOUT SYMB_EDIT_APPMOD Option in Die Editor to be able to "physically swap" pins, q+ Q! T! h3 v) a1 c
970910 F2B PACKAGERXL Our customer has problem with pin color after pxl 16.5.
0 t& G- H1 F( L7 P3 ~& e g970970 SPECCTRA FANOUT Fanout Vias is placed far away from decaps and does not change the Fanout length even when max_length is reduced.
) n2 x; s- R. s! o3 U0 s, C# d& K970985 SIP_LAYOUT OTHER Importing a .spd2 database file using NA2 will cause the APD/SiP tool crash
4 a; F' |" U0 R0 g! n0 h971757 CONCEPT_HDL INFRA Crash while Saving/Packaging the Design
0 Z; L: U) P7 T! p4 q4 @; K6 `& K971923 ALLEGRO_EDITOR MANUFACT Allow to change decimal accuracy for dimension instances
$ r; m6 c( G: s- I972568 CONSTRAINT_MGR UI_FORMS Tools >Excel missing from CM7 y6 A! K3 N" e9 Y( o' H) x
972821 CONSTRAINT_MGR CONCEPT_HDL connectivity server warning: Unable to add property WEIGHT' @, N, ^- n2 v2 \3 e9 L
973185 SCM CONSTRAINT_MGR ASA2 block not seeing all instances in a package.
) Z( k- r S& L% S0 ~& D0 v973211 ALLEGRO_EDITOR INTERFACES IDX Object Type Change not recognized
/ A8 F+ i9 d- y0 X7 H973214 ALLEGRO_EDITOR INTERFACES IDX import package keepout height value change assigns incorrect value Z/ n* Y0 d- _2 }+ R
973384 CONCEPT_HDL CHECKPLUS The multiple SIG_NAME has to be occurred an ERROR at the SPB16.5.
* _! Z, O% R6 ?8 f5 Z$ m973514 SIG_INTEGRITY OTHER Mapping error when Ecset is updated to constraint manager from extracted net
9 K7 P4 E+ s4 V. k+ M973950 ALLEGRO_EDITOR SHAPE Update to smooth crashes application
! n) q% ^' U8 Z974533 SIP_LAYOUT OTHER Crashes in Edit > Die Properties and obviously has a setup problem.) {! o5 k1 H. G, N& F
974809 ALLEGRO_EDITOR SKILL argument available for hiding a property with function axlDBCreatePropDictEntry is not working
! l! H1 V' Z; v5 H2 L& R# T976179 INSTALLATION ISR Installation of ISR S014 to 16.5 on windows is breaking the documentation index
' P+ @1 _* W# F3 h- D8 b4 f" @; Z4 C3 D# l( H/ P8 k
DATE: 01-20-2012 HOTFIX VERSION: 014; g2 J, E, J% O( A O
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CCRID PRODUCT PRODUCTLEVEL2 TITLE6 r( }/ ~) |4 X3 d5 i! R0 `; C3 P
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" o/ x+ C5 l* ~733285 PSPICE SIMULATOR Enhancement:In server-client installation use existing index file from server
+ [* X' U. d* k, S5 o1 O& X941020 SIP_LAYOUT OTHER Soldermask enhancement1 u0 x/ p) h; o5 `' |+ ?; Q" b
946407 CONSTRAINT_MGR TDD When is it safe to open a 16.5 design in 16.3?
% F8 K; ?) W1 J) x9 e$ U. P953067 CONCEPT_HDL OTHER Variant Editor "Error/Warning messages" form is unusable
( s. C2 k8 [$ m954818 CONCEPT_HDL COMP_BROWSER Replace button turns to Add in component browser when a component replace is done on the schematic
) x, f1 ~ v/ g1 ]956450 ALLEGRO_EDITOR DRC_CONSTR Analysis always shows analysis failed in uncoupled length in some diffpairs! O [; Z) P4 Z- K5 U
958259 F2B DESIGNSYNC ds.exe crashes on a big design when accessing the design from network drive# N- G5 b1 A9 g
958395 ALLEGRO_EDITOR SHAPE shape voids won't merge
2 t5 t3 g. D. F5 Z0 [959212 MODEL_INTEGRIT PARSE Attempting to use "Mark qualified" option on DML File results in dmlcheck and Modelsim wanrings.) A0 X, ]) \6 k
959940 APD AUTOVOID Void all command gets result as no voids being generated.0 \) ?: g& G( ]. p' i% j! P2 |
960252 PCB_LIBRARIAN CORE Splash screen in PDV prevents showing error message* W7 y( T ~( R0 k
961634 PDN_ANALYSIS EMVIEWER Cannot launch PDN EMViewer from withing PCB SI6 @# [5 a) d3 P9 f( Q4 x# p, Q0 y
961645 PDN_ANALYSIS EMVIEWER Standalone EMViewer will crash when opening any result file in the form of *.emv file.6 F. s) y1 V) F% {: v
961700 ALLEGRO_EDITOR SHAPE dbdoctor reports ERROR(SPMHUT-144): Illegal arc specification `* l7 c; o% A
961733 ALLEGRO_EDITOR SKILL Allegro crashes. Appears to have a memory leak.
, T2 t, l' C; ?$ X961758 ALLEGRO_EDITOR DRC_CONSTR DFA check produces no DRC when the dfa bounds are not a rectangle.' s& d; Q) I6 S) [# _5 B7 Q2 A
961887 CONCEPT_HDL CONSTRAINT_MGR Match Group created from ECSet cannot be deleted in the same session of CM
2 [4 _# f2 F( l3 _- s. g1 s/ `: `, @962552 APD EDIT_ETCH BUG:APD crashing when we try to slideget information but move works fine
. N2 \& k( F4 ]$ s& D& x4 A962869 CAPTURE STABILITY Capture crashes after RMB click on rotated parallel wires/ {! G7 h' N% J$ v/ t+ |- s
963232 CAPTURE MACRO Macros not being played in Windows7
" A7 W$ O6 f7 p& ^4 r8 K! z963300 ALLEGRO_EDITOR DATABASE Create > Module crashes in 16.5 but not in 16.3. F: \0 e2 w7 L
963651 CONSTRAINT_MGR CONCEPT_HDL ECsets are renamed after packaging on linux: X, m- P' E- y: \- K; e
963663 CONSTRAINT_MGR ANALYSIS Q- Why the customized worsheet for Diff pair Impedance not analysing at all for this SIP design( C, f, {$ R: G$ e$ f* r3 o
963715 SIG_INTEGRITY OTHER Application only adds the bottom conductor thickness for the via z-axis length- X# B+ k) o* R1 M
964068 ALLEGRO_EDITOR INTERACTIV Allegro crash when using move alt sym mirror alt sym.... e" n, r$ [* C$ j) t
964267 CIS PART_MANAGER Capture become non-responsive, working on Part Manager and creating CIS BOM, for large designs
$ }# H: l: R. K- _3 V5 A& j964597 ADW LRM Issue of LRM license checkout after renewal license by 16.5 (ADW15.5_S23+SPB16.3)
: K1 ]+ D# F k6 Y' u3 d5 S966148 APD INTERFACES Character Limit for DIE Files (*.die) Import
2 J2 k# \* o4 ]7 o" ?966416 F2B PACKAGERXL Cannot package this design& h6 z N; O7 u+ \* H* i/ \
966421 CONCEPT_HDL CORE DEHDL Crash when applying property on components in duplicated blocks
) W7 i- P1 g4 h, j; e966693 CONCEPT_HDL CORE DEHDL crashes when doing model assignment if CM is open" _' G$ a" Z/ l; x5 W
966795 ADW ROLLBACK rollback utility does not honor -product option from command line" r9 \/ a& { X( I- q) B
967089 SIG_INTEGRITY OTHER Matchgroups created by ECSet not deleted when ECset is removed from object.2 @% |8 S3 ?: ~
967222 ALLEGRO_EDITOR OTHER PDF export is leaving data off the drawing
- N+ ?1 ?; Q; `& p: s967240 SIP_LAYOUT WIREBOND Change default bond fingers selected on multi-site leads during "bond to leads" program
4 ^. O) N5 [ J% l2 w; j967297 ALLEGRO_EDITOR OTHER Dynamic Fillet&Eliminate unused stacked vias cannot be used as the Miniaturization option.3 |0 e2 u$ |8 N P# N6 o, J# R
967576 CONCEPT_HDL CREFER Occurrence location property values do not appear in flattened schematic generated by CreferHDL1 |: n8 Z5 [: r3 t) U; `& w
968096 ALLEGRO_EDITOR DRC_CONSTR Mechanical Pin to conductor spacing is not followed.
/ c4 R4 y% i3 Z3 I968222 SIP_LAYOUT DIE_EDITOR die pin loses IC net for a co-design die with multiple ports within IO-cell% \3 \; q7 d7 E0 q3 H: M
968358 CIS PART_MANAGER Capture crash on removing a part from subgroup in part manager$ h. u% h2 Q6 J! _( E" \& `
969594 CONCEPT_HDL CORE The dcf file is not updated with schematic changes) u/ p- T, i0 b+ T2 p
$ {- r1 H( }' S6 H
DATE: 12-16-2011 HOTFIX VERSION: 013* e& s8 h8 \, S% B7 }
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+ I( u2 r( g* p2 M& d875695 SIG_EXPLORER INTERACTIV Enforce Causality check box doesn't work.
! A, {& a6 e/ b( R ?927148 CAPTURE PROJECT_MANAGER Capture crashes on creating scehmatic folder with name which already exists in design4 V V2 Q/ V% ?. T! q [
938013 CAPTURE NETLIST_OTHER The netlist in RINF Format contained two identical lines for PCB FOOTPRINT, g* w4 e3 Z! T- Z, F" g- X" B
941409 PSPICE PROBE BUG : Search accuracy wrong in new cursor window
1 X' g) b H9 b* `' j+ L2 d945242 SIG_INTEGRITY SIMULATION Unable to select "shapes" in find filter for 'show parasitic ' command
, R) f S: D9 a4 h* x$ m946293 CONCEPT_HDL ARCHIVER Archiver hangs if there is a whitespace at the end of the path of cref.dat \0 R/ D' s( P7 x
946770 CONCEPT_HDL CORE 揤iew Design� function is missing in Windows Mode after reseting the menus.
' ]0 h* I# h+ C. J950994 CAPTURE NETGROUPS Problem in expanding the netgroup in Auto Connect to Bus function
; e$ U7 @; Z) u9 ?4 w953530 SIG_INTEGRITY GEOMETRY_EXTRACT Display Parasitics is displaying wrong results for EMS2D Field Solver compared to topology extraction using Probe.
/ M" [ f4 I3 C. m& Q. W. b0 l953713 CONCEPT_HDL PAGE_MGMT Random page replacement/duplication in block/ M+ ~) b, N! m( P9 O _* F
953917 CONCEPT_HDL ARCHIVER archcore should handle errors correctly) E" F* v8 Z, y* W8 M
953971 ALLEGRO_EDITOR MANUFACT NC Drill files not generated correctly when using the option "搒eparate files for plated/nonplatedholes�
# l2 P3 _" z5 ^5 a954400 CAPTURE NETGROUPS BUS members of NetGroup are getting converted to Scalars in Export-Import NetGroup.
J0 e8 O2 O0 Y. N( Y% e954498 SCM B2F SCM crashes when importing physical
9 b% u6 W- y. L* O% I# z4 V954623 ALLEGRO_EDITOR EDIT_ETCH Unable to complete connection with Add Connect - related to soldermask to cline check?
8 f0 K5 c2 I9 |8 R954894 ALLEGRO_EDITOR MANUFACT Dimensions disappear when opening database in v16.5 from v16.3
8 l; P, w% a2 F S! r9 i+ N- S955029 CONCEPT_HDL CORE custom text font size not recognized in symbol view+ S n) X4 [5 E @
955133 SIG_INTEGRITY FIELD_SOLVERS The Field solver creates the differential trace model which is reversed T(D1) and T(D2) of bottom side.7 P+ v4 }2 t+ D7 E- D2 m
955290 CAPTURE DRC Description for UPD0014 missing in the Browse DRC markers window
9 g3 [- I& f+ z% g955299 ALLEGRO_EDITOR DRC_CONSTR drc text to smd pin does not work any more on this database in 16.3 S0398 [/ b4 }; f# R8 H9 S4 Y, V) s
955338 CONCEPT_HDL CHECKPLUS Need to change PART_NAME
) [: j$ t" P/ s; y- q955447 SIG_EXPLORER OTHER Model path set in DE HDL Model Assignment not used by SigXP from CM in DE HDL
% }) [3 g X$ P955740 SIG_INTEGRITY GEOMETRY_EXTRACT Crosstalk with Timing Windows does not work correctly
/ O' T9 d' R. v1 J ?6 C955749 ALLEGRO_EDITOR MANUFACT show element Info shows symbol dimensions on incorrect subclass; R2 A3 l0 c9 e, C4 R y
955912 ALLEGRO_EDITOR OTHER Shapes with voids that are exported to PDF have gray filled area over the void
; D9 e+ _2 S K956129 CONCEPT_HDL INFRA DEHDL uprev hierachical design from 16.2 to 16.5 packaging failure.
4 Y+ f+ }) f$ `956373 ALLEGRO_EDITOR NC drawing name doesn't display in the log file4 o4 Q4 f b- A* I9 t
956393 CAPTURE PROJECT_MANAGER "GENERAL" and "TYPE" tabs are missing from " roperties" dialogue box.' ~; \- D; b. E/ A5 g
956448 PSPICE MODELEDITOR Can not generate a DEHDL symbol from Model Editor, because no Capture license found( p6 P) P# }5 i! G/ X( \0 V& H. Z
956456 CAPTURE NETLIST_OTHER OrTelesis netlist not transferring user properties defined under combined9 l! R/ B d [; S( p: c7 P
956489 ALLEGRO_EDITOR MANUFACT dimensions lost when symbol with diemnsions attached to symbol origin placed on board
( C' G' i2 [7 s2 z956603 CONCEPT_HDL OTHER Part Manager "has stopped working" after changing a component3 D9 d# ?- o/ @
956751 ALLEGRO_EDITOR ARTWORK Import Gerber command does not work correctly, q" N8 D* e5 U
956847 PCB_LIBRARIAN METADATA PDV - Partdeveloper symbol to function linkage broken/changed in 16.5; Q" t2 b6 t! E$ B/ o c8 |- t
956987 CAPTURE OTHER Find from "Search toolbar" doesn't gives complete results1 p" n0 w6 r3 {7 W( [
956996 CONCEPT_HDL INFRA Correction to ERROR(SPCODD-7): Following Primitive instance causes CM to empty
$ N8 Q0 x" K9 ?7 z! R5 P+ U% z z957009 CAPTURE NETLIST_OTHER Problem getting database property in mentor PADS PCB netlist
: k) T% o9 E( R a4 h7 L957137 APD DXF_IF DXF out command dose not work correctly.# C+ I. A4 m) x
957167 APD GRAPHICS Highlighting for Static shape with display_nohilitefont environment variable.
, ~4 A5 J7 v& l" p957232 SIG_INTEGRITY OTHER Allegro crash during Model Assignment.
6 S, U: v$ G9 A* @957267 CONCEPT_HDL INFRA Packager Error after Import Design, t' G! E; r8 C# q
957866 SIP_LAYOUT DATABASE Cavity outline is not getting deleted from symbol file* g/ P- D* p- h
958010 ALLEGRO_EDITOR REPORTS Wants the ability to extract "Batch" reports from Partition ".dpf" files.$ c. i) S: q4 O0 n/ D! y) k4 o
958252 ALLEGRO_EDITOR TESTPREP Resequence testprep with the option - Delete probes too close crashes the design$ O4 C( K+ a% }& p& m% d: U8 s
958253 ALLEGRO_EDITOR REPORTS Shape did not have thermal relief connected to pin but unrouted nets still shows zero.
! J, T4 \* m2 t3 I. G% n1 ?2 {1 l ?958433 ALLEGRO_EDITOR DRC_CONSTR False embedded component DRCs
6 h9 c1 M( `; h I6 j/ e# N, U. `958753 ALLEGRO_EDITOR SHAPE Dynamic shape is getting corrupted in 16.51 \! \6 ]8 T, a
959011 ALLEGRO_EDITOR OTHER copy problem of via and cline3 E% }( O" U1 n# j( G' \3 l. D
959101 ALLEGRO_EDITOR EXTRACT Using extracta with excluding Thermal reliefs
1 Z- i) a2 E8 u959253 CONCEPT_HDL INFRA Design will not open8 e8 U( Q+ a* `1 T b
959299 APD MODULES Getting ERROR(SPMHDB-279) when trying to update modules placed on the Top side
( n+ E5 f( l' p1 u* r959884 CONCEPT_HDL INFRA Design Uprev/concept2cm crashes with Application Error/Out of Memory Error.5 I5 f V$ t! E# z
959909 ALLEGRO_EDITOR SCHEM_FTB Site level propflow.txt file is ignored property is transferred
! W( K' L7 ^* k3 K960067 SIP_LAYOUT PLATING_BAR Creation of plating bar removes "NODRC_ETCH_OUTSIDE_KEEPIN" property from the clines.
' s' F+ u$ v' k- @4 K4 ^* T! N960126 SIG_EXPLORER EXTRACTTOP Allegro PCB SI license is used automatically at Topology Extraction of Allegro Physical Viewer.
1 c; Z5 F! `: D960143 SIG_INTEGRITY GEOMETRY_EXTRACT Running simulation in Bus sim happened crash while enable Coulpled Via model to S parameter
9 }. m# |$ Q9 K# E1 e% t1 m; r' v" h961349 CONCEPT_HDL HDLDIRECT Motorola designs have broken connectivity compared to 16.3
4 L3 b$ s2 }! b4 a961816 ALLEGRO_EDITOR INTERFACES Normal Export > DXF fails and offsets the pins of the BGA symbol+ }$ R+ \2 i* f& x" N5 W- n# u
962519 SIP_LAYOUT WIREBOND Align option doesn't work for wb_tackpoint fingers
4 o" k) a. J6 v0 {/ }. B2 v4 l- f$ |+ Y) C
DATE: 11-30-2011 HOTFIX VERSION: 012 o3 y1 F# o' T1 i, v
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959581 CAPTURE NETLIST_OTHER PCB Footprint is getting replaced by VALUE in OTHER netlist formats% M1 ^5 ` r8 g# Y6 z! P
P4 I2 m1 r! U6 L3 S# @' eDATE: 11-18-2011 HOTFIX VERSION: 011
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CCRID PRODUCT PRODUCTLEVEL2 TITLE
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# Y- P. q9 R) q) w6 A735439 PCB_LIBRARIAN CORE PDV Moving line-dot pinshapes by arrow keys breaks the pinshape/ U+ d4 O# f/ u) q0 v5 F
894815 CONCEPT_HDL COMP_BROWSER Why does genlibmetadata command give 'Aborted $PROG' Message?
0 E' x T9 G! ^3 a4 p% Z903073 ADW COMPONENT_BROWSE datasheetl_url directive should support a display string for URL
0 `7 U$ R1 n3 i909919 CONCEPT_HDL OTHER Why is the PublishPDF UNIX command line looking for "true" script?; ^6 \6 @9 P6 \- o( x2 [2 f2 }
911561 CAPTURE CORRUPT_DESIGN Capture crashes on trying to save the design.6 t' E6 z, O- H$ L+ i
919579 CAPTURE PRINT/PLOT/OUTPU Print mode be selected based on schematic mode
0 s! ~8 A& ? g7 w& L+ a. I k921247 CONCEPT_HDL COMP_BROWSER genlibmetadata.bat file does not have err defined
9 j6 r' @; W; U' R925182 CAPTURE PROJECT_MANAGER ENH: Feature to run update cache on all the parts in design cache at once." a, `( D6 D# |! U
926858 CONCEPT_HDL CORE Usability- Modify Component dialog forces user to do 'Reset Filters' to see other ppt rows4 ~) E1 F3 j, y/ \( q# z! Y
927657 CAPTURE NETGROUPS Enhancement: Placement of netgroup definitions under design cache list% t1 T% O5 d: k, h5 I2 I
934684 ALLEGRO_EDITOR MANUFACT The relation between the linear dimension and the symbol breaks.
; b) Q) U3 j9 y* x935836 SCM SCHGEN ASA crashes when generating Flat Document Schematic
$ v* [: |; M; ]937165 SCM SCHGEN Can't generate Schematic
) A2 }" c. C) K( I937292 CAPTURE GENERAL Memory usage keeps on growing and finally gets exhausted while search
0 N# O/ x, T& d0 M937322 CONCEPT_HDL CORE Master.tag file alters the sequence of the files and Genview fails1 Y- S/ }- [$ m/ H0 N" y
939135 CONCEPT_HDL CORE Unable to uprev a 16.3 Design to 16.5 with DEHDL-L License# G s0 x, ?; ~' j
940373 CAPTURE TCL_INTERFACE Enhancement: TCL command to add nets to Netgroup
+ `& W; r( |" b3 ?3 V0 J7 M940547 TDA CORE ERROR(SPDWSD-69): highspeed cannot be checked in4 ?. l. o0 w1 }1 \0 M2 { Q: K
940607 SIG_EXPLORER OTHER Inconsistancy in License usage for opening sigxp -orcad
8 k1 B" K. f9 n. K N- |0 v* V( z940790 F2B PACKAGERXL User doesn't want to display pin numbers after Export Physical 16.5.
, v- f, U( p1 R2 ?" w; r! ]- }+ O940944 SIG_EXPLORER OTHER Inconsistant license usage while opening Orcad PCB SI using allegro -sq -orcad and allegro -sq
7 ?2 r5 g# ~# z+ Q941354 CAPTURE NETGROUPS Enhancement: Option to rename the unnamed NetGroups9 m3 ~% M- `2 [1 B
941455 ALLEGRO_EDITOR MANUFACT The Dimensioned mechanical symbol when placed in the board does not show all the dimensions.2 G3 A2 ]+ y. ?! v. M" x! V2 Y' P7 M
941863 ALLEGRO_EDITOR EDIT_ETCH Different behavior of design in v16_3 & v16_5 when add connect is executed on a segment thru script
/ |. O7 Z7 I( s% T8 D3 Y4 T/ `941881 CONCEPT_HDL COMP_BROWSER How can I suppress the dialog from universalbrowser -genlibindex?
3 B. k# ^! W% V t( I* N942474 CAPTURE NETGROUPS NetGroup member type of last added member must be remembered by Capture8 b/ F+ ?, v9 _& q' Z+ j
942522 CAPTURE GEN_BOM Export in excel check mark doesn't invoked BOM in Excel' F, H( _! O3 a: j0 J' v6 B
942557 PCB_LIBRARIAN EXPORT_OTHER PDV Export to Capture crash
# u. {; d% T% x; a! G4 w2 X' U% k: P942569 ALLEGRO_EDITOR MANUFACT Dimension move and change text deletes leaderless balloon
$ Q; K8 U5 p* L4 q/ V/ n942573 ALLEGRO_EDITOR MANUFACT Balloon type parameter has no effect on leaderless balloon.
. P+ L/ e+ S# i- ?- x942613 CONCEPT_HDL CORE Genview supports only SCHEMATIC/SYMBOL/VERILOG/VHDL views as input type. .xcon not recongnised* }4 [& {: Z6 d8 u0 e
943032 SCM OTHER ASA is not passing the correct reuse_module name to Allegro PCB layout.
0 n7 q5 `$ z7 ^! m7 H! H% \) |' m943401 CAPTURE NETGROUPS Alphabetical ordering of NetGroups in Place NetGroup
4 `: I# \6 r: L* E+ x" d$ M- f) m# u944006 ALLEGRO_EDITOR EDIT_ETCH Vias added to shapes behave differently: L# E6 P- o7 ]5 b2 k
944367 CONCEPT_HDL OTHER Too late to do Model Assingment in conceptHDL 16.53 [$ M) v8 k+ ~0 j# u
944788 ALLEGRO_EDITOR GRAPHICS Oblong Pad shows unexpected lines
' O% r9 w2 q, |' P945221 CONSTRAINT_MGR RETAIN_CNS CM Conflict Resolution fails on more complex designs using ECSets and constraints
9 _. e5 ~% @5 K0 [. R+ u1 X946270 ALLEGRO_EDITOR PLACEMENT The Rotation Type was changed to "Absoute" if the "iangle 90" use at placementedit mode of spb16.5
* _1 |+ C7 d5 e% f. S Z, V946350 F2B DESIGNVARI Variant Editor rename function removes all components
" L- [7 k- z) a" s& T946380 F2B DESIGNVARI Some VARIANTX properties are hard some soft - why?
; ~* D- E% e! k$ G! S; I- f& H946419 SIG_INTEGRITY SIMULATION Cannot select component on BoardModel for controller in bus setup form
# b* b+ X: u% n% q9 ?946458 SCM SCHGEN Schematic generator adding an unnecessary page
6 [7 N$ Q9 Q) e3 [. s1 n4 j947667 ALLEGRO_EDITOR PADS_IN Need support for PADS-POWERPCB-V9.3-BASIC
. i- B! u# u6 t- t947789 ALLEGRO_EDITOR MENTOR mbs2brd crashes during translation on the attached design.
: [; [- R0 @1 a. ^% X3 e948110 CONCEPT_HDL CONSTRAINT_MGR Concept HDL craches when opening SigXP from CM
3 N+ n$ l$ F$ N5 p8 I950970 ALLEGRO_EDITOR MANUFACT Unable to generate artwork, dbdoctor fails to fix errors.1 d; M, d& L! W
951901 ALLEGRO_EDITOR EDIT_ETCH In 16.5 add connect to same net is shoved: c( z5 s0 g7 a4 Z+ Y: _6 e3 G
951919 ALLEGRO_EDITOR OTHER Exported package symbol soldermask and pastemask padstack locations not the same as original
' [; x! N# o/ n- K! ?5 v951926 CONSTRAINT_MGR OTHER What is MaestroNotifyNotSetReport.txt file?
/ C# g+ e2 O" j$ m0 S( ?+ _9 B951939 F2B PACKAGERXL Uprev to 16.5 is changing refdes for some pages
4 W: p' ~; x: G2 G951983 CONCEPT_HDL INFRA Problems converting an Allegro design from 16.3 to 16.5
6 h1 q, r* v9 r9 o! z952057 SCM PACKAGER Export Physical does not works correctly from SCM$ u& O2 L3 ~& Q4 S) v. D- }
952217 ALLEGRO_EDITOR GRAPHICS crash when opening 3d viewer in PCB Editor
" ^" x+ [0 F' S! O& D0 Q2 w952634 CONCEPT_HDL CHECKPLUS Checkplus logical rule fails on a design which packages fine in 16.5
; f) r/ I) _9 D! ]: y8 \0 `3 o/ v5 y953018 APD REPORTS Shape affects Package Report result.; ]: K5 Q L( ^& _6 ^( K1 h) m
953337 ALLEGRO_EDITOR OTHER Allow netname and padstack names to be visible for testpoint vias when viewed in Allegro PDF Publisher.0 J3 o& V- o1 }$ K5 Q/ X L7 d9 O
953827 ALLEGRO_EDITOR EDIT_ETCH Snake Breakout function crashed Allegro
) ]4 y7 A* H& I; D6 Y953918 GRE CORE GRE cannot route second and third row of pad in die symbol./ r, Z8 i$ W3 {' M+ b6 E
954055 CONCEPT_HDL CREFER Crefer fails with UNC install path& V% H+ O/ j" d8 C3 h' X4 h9 G
954920 SIG_INTEGRITY CIRCUIT_BUILDER Each neighbor crosstalk simulation crashes or returns blank report3 ~( q6 Q* q8 j) z7 w2 t
& g" g% E. q0 R' R4 Y1 h
DATE: 11-7-2011 HOTFIX VERSION: 010
4 I2 Q. G4 n" e: I( S) @/ `, H===================================================================================================================================
$ n7 S& y, N8 T' u# z" j9 vCCRID PRODUCT PRODUCTLEVEL2 TITLE3 |1 u$ y* i! D; }% O' r
===================================================================================================================================
' N/ P! k2 `2 I. u. b7 Z; B6 v. p658866 ALLEGRO_EDITOR EDIT_ETCH enhancement option - so that Sliding a via inside a pad does not create a cline& k) V9 n7 @# r" O6 X/ J6 Q" {
928624 ALLEGRO_EDITOR GRAPHICS Layer visibility control for 3D Viewer
: Z7 j3 z1 e. y6 O9 ~2 y934991 SPECCTRA LICENSING Specctra_adv option is not working correctly for PA3100 plus PS3500 license in v16.5 tiering profile
6 {) y) o( B7 C4 @1 ]" l938073 ALLEGRO_EDITOR PLOTTING Plot Page size A0 and A1 with problem% Q. X; V; s( a2 t M
938128 ALLEGRO_EDITOR DRC_CONSTR DRC changes when do update DRC.5 L" |! Q) F- \; n1 o
938648 ALLEGRO_EDITOR GRAPHICS Enh - Requesting a way such that Package keepout appears transparent in 3D Viewer* I( P" M0 \$ V
940518 SIP_LAYOUT SYMB_EDIT_APPMOD Swap pins command doesn't complete4 ~4 v7 o0 s9 p2 l4 P
941426 CONCEPT_HDL COPY_PROJECT Copy Project fails - Updating opf view This can't happen!. U: t4 m/ k, X& _. `9 V x
941499 ALLEGRO_EDITOR DRAFTING BUG imit Tolerance isnot working for Dimensioning& S8 I. M. O- r" \3 s) j
941814 CONCEPT_HDL CREFER CreferHDL crashes during ScheGen7 ]7 V8 n$ s7 Y$ x% |
942914 SIG_INTEGRITY OTHER ZAxis delay calculation0 t9 T& K8 h1 U% G. t
943053 ALLEGRO_EDITOR SHAPE Modifying the Board Outline shape will cause the tool to crash$ ~) W6 M- ]% W0 f. p
945321 SIP_LAYOUT EXPORT_DATA generation of a xml file from cdnsip for shrunken die1 @9 q3 q, [+ A) w& P% R
945350 ALLEGRO_EDITOR SHAPE iPick does not work on shape boundary edit.- h9 T8 y" C2 h& K9 Z5 G# _1 C
945449 APD SKILL When they create a new menu entry with skill APD crashes with next menu selection.1 Z; l; F7 U4 w h }' _
946390 ALLEGRO_EDITOR DRAFTING refresh_symbol crash when trying to refresh mech sym that has dimensions9 H* c ~6 i2 n/ A
946401 APD EXPORT_DATA stream out gdsII results in shorting of PWR/GND nets due to elongated etch
' S2 ~& H' Z* \2 Q) }' @( {946819 SIP_LAYOUT DEGASSING Shape degass command4 f# U. W |' {
946869 ALLEGRO_EDITOR OTHER Allegro PDF arc representation needs cleaned up3 L7 \- j, r2 q* \5 z
947230 ALLEGRO_EDITOR SKILL Skill execution crash Allegro 16.5 but work correctly with Allegro 16.3
# u3 g& p7 y D7 h947603 ALLEGRO_EDITOR OTHER Component Properties (Default or User Defined) not transferred to PDF file
# Z8 I% V* K5 D3 d950995 SIG_INTEGRITY OTHER Netrev fatal error when importing logic
. \, m, `- m9 k& @4 r8 S951123 ALLEGRO_EDITOR INTERFACES IPC fails to output drill hole info in columns 33-37
3 \- R4 M" H' ?8 Q951557 CONCEPT_HDL CORE Cannot create the entity folder for old plumbing symbol
: y. k, _: y4 [% {1 E2 \
! `0 |7 j) W5 w& W- YDATE: 10-26-2011 HOTFIX VERSION: 009
' `5 S8 y% B% c: ~: W4 O7 M0 T% M===================================================================================================================================) Y/ H* K( B$ P" W
CCRID PRODUCT PRODUCTLEVEL2 TITLE
& s8 h: {* w% v===================================================================================================================================
- i/ s% j& Q7 c9 {: x945788 CONCEPT_HDL CORE Some component properties on the parts are incorrectly changed after Import Sheet
* y6 r0 U$ x8 c3 A& }, b+ x5 f1 U945789 ADW LRM Some component instances are not updated by LRM even though cache ptf is updated from reference$ u8 b8 T9 w3 q6 d5 ?
4 q1 X* S% y R/ s6 wDATE: 10-21-2011 HOTFIX VERSION: 008
1 t% F/ w x) _! A" }3 I6 y j( C===================================================================================================================================
% k7 @3 Y9 k& h" m; ^- [CCRID PRODUCT PRODUCTLEVEL2 TITLE; h3 A2 Z. D, Z! S; I- N! Z
===================================================================================================================================: O3 V/ t- O+ @# _& v
906827 ALLEGRO_EDITOR DATABASE Logic > Parts logic does not work correctly.. J7 h, i5 L1 ?6 l/ ~: L
923346 CONCEPT_HDL CORE Not able to move the reference designators inside hierarchal blocks after uprev to 16.5: f6 k: p: Z) u% X, U
926347 ADW COMPONENT_BROWSE Usability- Libflow Part check in comment should end up in Comments attribute for UCB/Designer to see it, n+ f6 c% D9 M8 y7 Z/ X+ A2 y. y9 `8 }+ G
929348 F2B BOM Warning 007: Invalid output file path name
: t) A9 P l4 w: ?/ j; W929777 CONCEPT_HDL OTHER Component Revision Manager gives internal error9 o- ~7 c/ T4 M; c- Y- ?9 F
930783 CONCEPT_HDL CORE Painting with groups with default colors! ]# @- f( @' W% I7 q
936748 ALLEGRO_EDITOR INTERACTIV "Unplace Component" menu inconsistent between General Edit and Placement Edit Mode.0 s. v E8 J" a& G% J
938143 ALLEGRO_EDITOR CREATE_SYM Why is this Extra Property 'ECSET_MAPPING_ERROR) z: w. }3 s' Y& t: ]# h
938281 SIP_RF OTHER export_chips creating bad data when symbol is split and contains V- V+ pins
! p( @8 n- @% C938812 ALLEGRO_EDITOR SYMBOL Cannot create a BSM with this DRA, errors out but does not state a reason.
4 T; P# {1 z2 _* p3 w939075 CAPTURE TCL_INTERFACE Texts are getting garbled in command window
/ C3 {; g! ~5 M. t939193 F2B PACKAGERXL ERROR(SPCODD-439): Connectivity server is unable to load the design.$ N1 k% ~9 c: Z( U( v% C
939199 CONCEPT_HDL DOC "Retain electrical constraint on net" mismatch between schematic (YES) and design (NO)/ S/ k3 D" N) I _ R
939346 ALLEGRO_EDITOR SHAPE Shape disappears when updating with variable shape_rki_autoclip set.
( \4 Z7 g& I" N) K; a3 f939901 CONCEPT_HDL INFRA NET_SPACING_TYPE shows �?� on lower hierarchy level nets after Upreving to 16.5 version.
. ~9 T3 l" g/ ^$ b939918 PSPICE PROBE Print > Preview for output file causes Pspice crash.& L$ R; k3 L) G0 v# F
940217 CONCEPT_HDL COMP_BROWSER UCB reports 'No Symbol found for the part'- Y% f( y9 O4 v* }0 X
940835 CONCEPT_HDL INFRA Desing package different after uprev to 16.5 where comp instance propeties are lost lost; a% ~# e9 C2 X% L$ }
941125 ALLEGRO_EDITOR DATABASE Performance advisor doesn't skip non plated slot padstacks
( o- I$ S' |. d941876 SIG_INTEGRITY OTHER Illegal model name cause pxl fail in 16.3 g, Q& Z3 i# a, B, z$ p' G& N
942210 SCM OTHER Is the Project File argument is being correctly passed?
2 x" Z0 U8 C, t* q$ n& B4 b942274 CAPTURE PROJECT_MANAGER Crash on renaming a Design Cache part in Project Manage after doing replace cache' t% _5 z/ s: r a3 r' N6 y b
942839 ALLEGRO_EDITOR GRAPHICS Graphics Issue- Pads are not visible. R) H4 ?# t0 Y2 p1 \, m
943055 ALLEGRO_EDITOR SKILL axlDBCreatePropDictEntry causes application to crash
# O/ I! o( W2 P4 X1 I/ x6 u C3 I! @: c C/ R8 h
DATE: 10-21-2011 HOTFIX VERSION: 007: m- R3 z; J8 m' [
===================================================================================================================================/ Y1 m. B9 r8 g1 M" _
CCRID PRODUCT PRODUCTLEVEL2 TITLE6 e) G) C) O+ u
===================================================================================================================================- w' ~/ f7 {6 ?0 |/ E9 Q: T' J7 t
841096 APD WIREBOND Function required which to check wire not in die pad center.* m7 J; X& y5 v; r# J* o# L
903263 CAPTURE SCHEMATIC_EDITOR ENH: Selecting parent netgroup must select the underlying netgroup bits.
/ H; S) J! N) k8 l4 A8 L4 | M" [906692 ADW LRM LRM window is always in front when opening a project! J6 Q6 i+ M% k0 {; q
912942 APD WIREBOND constraint driven wire bonding
$ ?: z9 s* H% T# i! h/ \) |912951 CONCEPT_HDL CONSTRAINT_MGR Need to manage temporary files on Linux systems
4 V! F @/ l& h; t; ^" f5 F915178 SIP_LAYOUT DIE_STACK_EDITOR Die Pad names changing when updating Die in a design# }3 t8 K2 o {, _! ^4 [1 E6 x
917887 PCB_LIBRARIAN VERIFICATION Part should not be released if the alt_symbols has errors0 K6 P. j7 @8 m
923315 SIG_INTEGRITY GEOMETRY_EXTRACT crosstalk simulation fails with TMP popup failure1 l6 ]8 E4 C4 g( e( x0 K5 `
927382 CONCEPT_HDL CHECKPLUS 'Verify Symbol' forces the use of 'Concept_HDL_Studio' license# `6 V& U5 i# f+ ?
927664 CONCEPT_HDL CONSTRAINT_MGR Internal Error disposeipsp& M5 r$ b2 m8 U' v! a. D) s
930152 CAPTURE NETGROUPS Scalar net names when being connected to net group overlap when connections are made one by one
! S5 O* ]6 R' Y- L% l930180 CIS LINK_DATABASE_PA Visible property position on schematic get reset on "link database part" operation! O7 r9 t% z7 D4 i
930188 CAPTURE DATABASE Capture 16.5 crashes in being re-invoked.# \/ g" Q1 U& B. r6 N: ]
930541 CAPTURE NETGROUPS NETGROUP element renaming doesn' renames the associated net ?
+ X) i( h8 z) V9 Z4 @930866 PDN_ANALYSIS SETUP OrCAD PCB SI Session crashes when we open PDN Analysis with "OrCAD PCB SI" license.
0 `0 b o' n# @$ ?" P930926 ALLEGRO_EDITOR GRAPHICS Via and Holes not visible eventhough set to Visible in Color form
$ _6 ^. I5 Z% { V931274 ALLEGRO_EDITOR DRC_CONSTR Negative Plane Islands waived DRCs reappear after performing update DRC.' Q3 q3 K7 x& [8 ?4 F) K
932091 CONCEPT_HDL CORE Prop attached to SIG_NAME property
: p& l3 X# o1 y' m; p932255 ALLEGRO_EDITOR GRAPHICS Change in Zoom level makes arc segment to disappear
4 t- g( v/ X2 k* C, J932292 ADW LRM LRM crashes during Update operation on a customer design
i8 f) j( @' P9 V; l932639 SIG_INTEGRITY OTHER Add Connect command hangs for about 14 seconds and then returns.! k/ [* ^3 V/ g8 b' n3 T
932704 APD DEGASSING Shape > Degass never finishes on large GND plane
5 ?# H$ s; Y6 F# I: V932871 APD GRAPHICS could not see cursor as infinite
) w9 z' X$ U% `( s9 m% D' m4 {932882 CAPTURE SCHEMATIC_EDITOR Capture crash with FIND command - ISR057 b) P: X/ S2 N
932969 CONCEPT_HDL CORE ConceptHDL crashes when you save the design in 165 > hotfix #05
/ { C+ p7 X8 r/ d+ ?933024 CAPTURE NETGROUPS Naming restrictions for NetGroup members3 W; S y! ^4 g( n, @1 e, k% N Y9 ?
933145 F2B PACKAGERXL Add Subdesign list is truncated in Force SubDesign Design Name pulldown, I' t/ }0 T. M/ t
933214 APD ARTWORK Film area report is larger when fillets are removed
4 L; y0 C( Q& N5 x933356 CONCEPT_HDL CORE Net prop display size become 0 if it was attached to SIG_NAME prop.5 E, t" m# D; `1 A' n* U/ k. i
933532 ALLEGRO_EDITOR COLOR Bad color assign and initialisation during creation of new subclass
) |0 C7 w+ x/ F# b933549 ALLEGRO_EDITOR OTHER Chart text missing in export PDF file.
8 Q& w. D5 |3 Z& P( g+ Q934008 ALLEGRO_EDITOR REFRESH refresh symbol updates symbol text to some unexpected values
" j0 l4 W0 T7 H934031 ALLEGRO_EDITOR DRC_CONSTR Bug : Update DRC removes Waived status for some DRCs. d* S& ?+ T4 G6 C% i$ Y, m
934087 CONCEPT_HDL CORE Opening DEHDL and Model Assignment before design loads causes crash; H* S1 B9 P) G' e/ s
934396 CAPTURE SCHEMATIC_EDITOR Find operation is not searching power symbols with + or - signs.
4 Z3 l: ^; S; W" c* @ b8 j+ J934533 F2B DESIGNVARI The Variant Editor errors are not written to the variants.lst file
' @$ f* ~! D& W2 `! y" F934811 SIP_LAYOUT UI_FORMS CDNSIP should not hang if contraction value in z-copy command is out-of-bound K1 J& j' [# G; T/ Z& T: S
934909 SCM UI Require support for running script on loading a design in SCM( R M9 U! g7 i
935632 CAPTURE SCHEMATIC_EDITOR SHIFT+Mouse wheel scroll(horizontal) of page is not working in Auto Wire Mode.
+ o0 v$ _7 h7 \4 N5 c935794 ALLEGRO_EDITOR SHAPE BUG:Shape not filled in 16.5 but it does in 16.3. t& g- _! p% V1 A
935988 ALLEGRO_EDITOR INTERFACES When attempting to downrev this 16.5 design to 16.3 the tool will crash+ d9 ^1 a& D( x: M$ b
936056 ALLEGRO_EDITOR DRC_CONSTR place_manual crash while moving mirrrored symbol$ k% d$ p J/ s; H: D( t
936098 ALLEGRO_EDITOR SKILL axlDBCreateCloseShape does not work correctly.: Z) Q# z% W& e8 d1 C0 ^7 c
936212 ALLEGRO_EDITOR INTERFACES DXF not created if Blocks created for Symbol and padstack
# A0 g1 [2 H: Z# Y9 ?. b936797 CONCEPT_HDL COPY_PROJECT Copy Project crash
# G5 I. l* O( ]: }936808 ALLEGRO_EDITOR DATABASE Allegro crash replace mechanical symbol
+ T2 a6 a) E1 V$ P- X4 D) u936853 CONCEPT_HDL CONSTRAINT_MGR DEHDL crashes when trying to extract net from CM
Q2 F$ f- W; L. T' @1 [: }" L937087 CIS DESIGN_VARIANT Upreved design becomes very slow in Variant view mode. DELEET THE DESIGN AFTER RESOLVING THE ISSUE
& D$ N: n9 R1 V1 `# u7 u937173 CAPTURE OTHER Wrong license information "UNLICENSED" in Capture >> Help >> About) }$ r& i* q/ d* m
937290 APD PLATING_BAR Plating Bar checks does not recognize connection made through etchback through shape.
/ w4 T0 j$ I: \ h' O) T/ L937411 ALLEGRO_EDITOR DATABASE downrev_library reading from one directory and writing to another hangs the command.
0 H* a. U5 X' @9 D. }( T3 u938235 SIP_LAYOUT STREAM_IF Die Orientation is not correct after importing a stream file.
& e( V; B5 y8 k3 ?( D938273 ALLEGRO_EDITOR OTHER PDF export is is not opening viewer with ads_sdlog variable set
4 `; m8 T d8 k# W5 s7 K C
% ?5 d* a( g6 \' u7 y( qDATE: 09-16-2011 HOTFIX VERSION: 006
4 [) g( }, J) u3 Y& b5 }===================================================================================================================================
) U; o% {% X2 |5 d6 wCCRID PRODUCT PRODUCTLEVEL2 TITLE
: W) [ T) @5 ~& I===================================================================================================================================2 R$ M$ a+ B. }8 e3 f( b3 ?
820131 CONCEPT_HDL OTHER Moving symbols to other page will make Allegro components unplaced because logical_path changed.+ Y l) C/ y6 p5 D" _5 K1 m
863860 CONSTRAINT_MGR SCHEM_FTB CM should display or Local Interface and Global nets to help defining low level constraints
) r/ ^' F2 s6 _* }7 N0 x1 y919822 TDA CORE Cannot configure LDAP to only list the login name
. a+ {) _0 H# i1 C* G922907 ADW TDA 搇ast_callout_file� directive in the BOM section is empty causes tda for show Access Denied error
# b7 i7 |- B. I) c, I( N& f0 A* ?924322 ADW COMPONENT_BROWSE Random - No instance properties are added on Add To Design (RMB or double click) from Search Results* D0 q" w# X5 P* V
924448 F2B DESIGNVARI Design does not complete variant annotation. i. m5 X: @" r
925584 CONSTRAINT_MGR SCHEM_FTB 16.3 upreved Design passes the SLOT/Function Properties to PCB
3 p* r- i$ }) |+ x) E927102 ALLEGRO_EDITOR OTHER Question of Conductor Detailed Length Report0 O4 Y, J) R. z) L+ N
927104 F2B DESIGNVARI Tools > Annotate variants crashes when there are ASCII characters in the property values
/ i2 g- ]9 K4 c1 g# c. w. g( z927142 F2B DESIGNVARI Incorrect pop up asking while executing variant editor from the command line
5 g, B! j' C) U1 E$ g8 k: ~7 W927166 CAPTURE NETLIST_ALLEGRO ENH: Feature like NET_SHORT in Capture Allegro flow which allows user to short 2 or more power nets
8 S% [$ ?- V1 i7 b3 X5 A' K927410 ALLEGRO_EDITOR DATABASE ERROR(SPMHUT-144): Illegal arc specification error when Run DBDoctor
5 l# X- ?7 A: m, v* D4 B* u: P927475 CONCEPT_HDL CORE About forcereset command of nconcepthdl
! o r( ^, G6 G8 {. P- Y# W927498 CONCEPT_HDL CORE Pin_Name starting with minus causes incorrect behavior for $PN display
) r* |' {, J* E: n) A% c2 m927608 ALLEGRO_EDITOR PADS_IN Import PADs fails with error message: Failed to close the Allegro database) _: X0 s& _; `% w( O; G# e
927637 SCM CONSTRAINT_MGR ASA crashes on change root and also performance is too slow." J" I' J) M6 e: s0 I% ^2 i
928429 SIG_INTEGRITY OTHER Request - Package Wizard to work in PCB SI.& o& P1 P- A& @! Z1 b+ v
928483 ALLEGRO_EDITOR DRC_CONSTR Running Update DRC removes Via List DRC Error when via is actually not in the list/ z! t% ^$ ]* K5 w( ]; T' {, m
928738 PSPICE PROBE Y-axis grid settings for multiple plots
& I3 B) Y3 K& J2 A: a928748 PSPICE PROBE Cursor width settings not saved/ s7 w' _3 o! R; n4 m1 z
928779 CONCEPT_HDL CORE Error (1053) occurs on a copied part in SPB165 release
a1 u6 J6 E) x. c3 z! _( b928838 CONCEPT_HDL CONSTRAINT_MGR ECSets not migrated in 16.52 z5 w: N/ P6 n1 {. R/ A
928885 SIG_EXPLORER EXTRACTTOP PCB SI crashes when extracting a net from Probe; r5 B: E. T0 P" J8 d
929284 CONCEPT_HDL ARCHIVER archive does not create a zip file& V3 L$ {0 i- U$ k# V- E
929542 SIP_LAYOUT DIE_ABSTRACT_IF net issue of multiple ports of co-design die in SiP
! C1 V5 U# ^8 @. B9 k" c929656 ALLEGRO_EDITOR PADS_IN PADS translation fails with Microsoft Visual C++ Runtime Library error0 e" ]$ b. e0 \6 @0 \& r
930063 ALLEGRO_EDITOR TESTPREP Test prep crash Allego when it can not create pin escape0 ~ Q! S* X8 i& h
930217 CAPTURE NETGROUPS Net aliases doen't gets assigend to bus bits if bus name is checked in NETGROUP.
3 n1 p9 s2 X$ l: {930355 SIP_LAYOUT WIREBOND about "wirebond add nonstandard" command# Z" S6 A. T' G/ P ?! ~9 R& I, ^
930607 APD OTHER Layer mapping information is reomved from Layer conversion file upon exporting DXF from board file.
- ]6 `: @/ S# x" e# A) a930646 ALLEGRO_EDITOR DRAFTING Bug - Adding Linear Dimenstion for ISO standard add the Angle information as well z, _' P2 c' B" Q, k. w
930894 CAPTURE TCL_INTERFACE PDF export doesn't creates property file if some symbols are used in page name/folder name6 H% R8 ~8 c5 E1 t2 x% X
930944 ALLEGRO_EDITOR OTHER Setting variable 'appmode' equal to 'none' is not changing the Application Mode when reinvoked$ n% I; m* p; C! O) t L3 i
930978 ALLEGRO_EDITOR SCHEM_FTB 3rd party netin error - Pin is connected to net <netname> not reconnected no longer happens
8 d Y, x- B$ S3 |$ C& }931248 ALLEGRO_EDITOR DRC_CONSTR Match Group was removed if member nets became xnets.
: U2 V8 d% n% G2 p: C3 Y& W931278 CONCEPT_HDL INFRA $PN gets copied when upreving design from 16.2 to 16.5 version
% [1 k5 I/ s( M W* J931349 CONCEPT_HDL COMP_BROWSER DEHDL craches and corrupts connectivity file when using Modify command extensivly.0 d6 z6 U+ P9 C6 Z- ~9 U8 S8 ~
w! H) H8 W4 k8 n F
DATE: 08-31-2011 HOTFIX VERSION: 005
2 O0 T4 a! c% V===================================================================================================================================
% ~- K: E. S1 A6 Z3 Q- QCCRID PRODUCT PRODUCTLEVEL2 TITLE
t; n5 t; o/ A7 I, O) {===================================================================================================================================
9 E8 m7 j* \3 M) @2 J- _" \825848 ALLEGRO_EDITOR SHAPE Shape not filled when edges from 2 RKO shapes touch around mouting hole1 R0 ?0 w9 q% @$ _, C3 A
837723 CAPTURE PROPERTY_EDITOR Occurrences of external design not related to current root should not show5 G8 u6 l9 Q" `& @9 x
891079 CONCEPT_HDL CORE DEHDL crashes with large number of commands in Winodws mode1 B8 ]* P! ^7 H7 M z. C8 O; \. m3 ]
910908 SIG_EXPLORER OTHER Cannot open top if Tx AMI dll name contain more than 2 dot.
2 y. p. i8 u5 v% q- R& u914036 CAPTURE LIBRARY ENH: Option to delete a corrupted part from a library and leaving other parts intact in the library.
, O6 o; N' l% l1 u( S8 ?, n914679 ALLEGRO_EDITOR INTERACTIV Custom toolbars are not retained when switching between brd to dra and back to brd file using the File > Recent Designs
% ^3 T {4 D. {( o914870 MODEL_INTEGRIT OTHER mergedml fails to merger 2 DML files from the model integrity$ a# I" b8 O7 R' }4 N8 _9 I
915645 ALLEGRO_EDITOR MANUFACT Allow the user to place the cross-section chart at a desired location* T, ]2 c" Y' D4 Q3 V. j
915653 ALLEGRO_EDITOR INTERACTIV unable to delete non-etch shape
& \& G, q+ Z6 P/ c915711 ALLEGRO_EDITOR MANUFACT dimensioning tolerancing by limit not working
+ v+ {. B* o7 n7 u; i" `% L916321 CAPTURE GEN_BOM letter limitation in include file. z0 x8 W( g- X4 Y _& d
916907 CAPTURE SCHEMATICS 揂uto Connect to Bus� should place the wire through non-connectivity objects; r- P$ N9 j7 l. Z- L. S r
920327 CONSTRAINT_MGR ANALYSIS The TotalEtchLength predicate in Constraint Manager does not work for a netclass with a bus.) ?& R' {8 \9 u% i- s- \
920753 ALLEGRO_EDITOR GRAPHICS If I confirm to padshape with zoom-in after install the s002 It was changed to wrong shape.
7 M: |+ I+ W) _921097 ALLEGRO_EDITOR GRAPHICS Padstack seen partail filled when Zoomed in even "static_shapes_fill_solid" is set7 D1 v4 n3 A6 O8 d1 f
921226 ALLEGRO_EDITOR DRAFTING Unable to select Package Geometry class when dimensioning in the symbol editor.- y) }5 j8 N1 C, [# n
921623 ALLEGRO_EDITOR GRAPHICS Bug : Symbol not visible when zoomed in 16.5 S002 N* f' W% S, |& K( {% `
921891 ALLEGRO_EDITOR DRAFTING dimensions are lost after downrev(ing) a SPB 16.5 design with associative dimensions
$ R/ s' h# ~8 a5 x2 s3 _921937 ALLEGRO_EDITOR COLOR Padstacks with shape symbol are not showing correctly3 Z3 l; d$ S# i6 M! J
922066 CONSTRAINT_MGR ANALYSIS Custom measurement Actual not being cleared when layout changes.
* q" P9 J. B i; V922117 PSPICE PROBE Label colors are not correct in Probe
) X# a0 R% Y3 h. l8 G; r b922519 ALLEGRO_EDITOR SKILL add_bviaarray command fails for some clines but not all
/ v8 C1 ]) W) p923224 ALLEGRO_EDITOR GRAPHICS Thermal flash Display problem in Allegro v16.5 Hotfix S002
/ }& |$ n! @( m0 u923286 CAPTURE DRC DRC markers not reported for undefined RefDes
9 v, I5 c u) X8 h$ d. U6 H! k923362 ALLEGRO_EDITOR PLOTTING Print to Postscript file not correct in 16.5
8 K m! j" d$ ~923416 ALLEGRO_EDITOR PAD_EDITOR Pad Designer crash on clicking on the Arrow before Soldermask_top( u; ?2 ?9 | L( r* h
923507 CONCEPT_HDL CONCEPT-PCBDW The function of Import Design in the SPB16.5 Design Entry HDL (for data of ADW15.5_S23 + SPB16.3)
n3 h7 k$ v) T0 Y( z* p923910 CIS PART_MANAGER Copy & Paste operation from Part Manager copies properties only to first section of the part.! I# Q; h3 X- B+ L6 p H3 V( F1 T
923913 CAPTURE PROJECT_MANAGER Capture runs slow on attached design
' y0 x/ Y7 b3 W: Y' M: H923937 CONCEPT_HDL CORE Back annotation time significantly increased with the metadata generation on# T5 f. r% b% a. a0 v
923949 ALLEGRO_EDITOR INTERFACES Incremental DXF_IN gives 'Invalid subclass' error
J; Z! q& p I! J f/ L3 z5 E- q924458 SCM OTHER Project > Export > Schematics crashes
/ V: X. H$ q/ I, N* J924621 ALLEGRO_EDITOR SHAPE Dynamic shapes are disappearing upon updating them to smooth.
_% W1 ?. p, e/ G2 ]) d925193 SIG_INTEGRITY FIELD_SOLVERS Diffential Impedance (DiffZ0) values computed in the layer stack-up is incorrect% @8 R9 r+ t3 x k6 S
925195 ALLEGRO_EDITOR DRC_CONSTR Incorrect pin to shape DRC error
& z; E$ V5 X; Y9 B925338 CONCEPT_HDL CORE This application has requested the Runtime to terminate it in an unusual way
" \! x+ Q: P; k1 b& z# ~925435 CAPTURE TCL_INTERFACE Capture crashes if 揝ave design as UPPERCASE� option is disabled.; ]6 }2 j$ U! \/ r x
925530 SIG_INTEGRITY OTHER Why the single line impedance value for Top and Bottom layers are different for this design?" g- c4 i! C# \( B& L
925864 ALLEGRO_EDITOR DRAFTING Ability to add dimensioning to different CLASS/SUBCLASS# F4 n& t, Z: b1 |( u
925976 ALLEGRO_EDITOR MENTOR mbs2brd fails to import data
! u- k5 I; X9 I926409 SIP_LAYOUT DRAFTING Exporting a 16.5 design to 16.3 will cause the leader/dimesion lines to be removed.
% U' |" N2 s) }5 x8 \* {926443 CONCEPT_HDL CONSTRAINT_MGR In new 16.3 "035" ISR Concept2cm will crash with error.
9 s4 L8 g. K8 R* t9 U0 n. [+ |! F926503 CAPTURE GENERAL Memory leak Capture/Pspice
% t+ I8 E' A# H- |1 B926553 CONCEPT_HDL CONSTRAINT_MGR CMGR ERROR There is no net in the Cset that has pins matching those in net 1 in the Xnet6 P: F$ A: l2 ` X
926691 ALLEGRO_EDITOR OTHER Crash while Importing Technology File in CM, with Overwrite Constraints.
/ L# s \% c% {, R2 P8 U/ H- X926887 CONSTRAINT_MGR CONCEPT_HDL Pin pairs lost after Export Physical1 s) S; T! u1 l' q$ S9 c
927159 CONCEPT_HDL CONSTRAINT_MGR Export Physical fails due to errors in ConCM.log when SIGNAL_MODEL injected property is ''8 `6 D) u( f1 _6 s% @
& t# n2 \" J, Y# n
DATE: 08-19-2011 HOTFIX VERSION: 004
& f: Q) N( i; U/ }===================================================================================================================================% `& I5 K& U. [# n) \8 F+ U; q4 M
CCRID PRODUCT PRODUCTLEVEL2 TITLE8 x' t# h# w( K0 @) N3 T* x
===================================================================================================================================; r- [3 l3 X: m$ ?& e: M% V3 M: e r
785417 CONCEPT_HDL COPY_PROJECT copyprojectui crashes with a Windows runtime error& g. q6 d; _9 a2 t. Q
851044 CAPTURE GEN_BOM "Export BOM report to Excel" does not appear in the Standard Bill of Material Window.
6 x$ [5 X, {0 F/ I9 N# D868216 PSPICE MODELEDITOR Encryption of subckt names, internal nodes, comments
: j, o; q0 J( d k) J870247 PSPICE SIMULATOR Encrypt a model and simulate it, info about inside nodes being dumped in the probe file
" Q# z; Q* o- ]9 E7 S, r, X877091 CAPTURE SCHEMATICS Save JPEG, GIF, PNG and other image formats in the database in its compressed form
& ] R l' A0 g) e894059 CAPTURE OTHER Enhancement: Adding column in edit>browse>parts window
, j9 W; g1 g7 Q9 m: b- \895902 RF_PCB OTHER Alphanumerical allegro pin numbers are unusable in ADS 2009 Update 1( P# D! p3 l3 B% ]* u
895919 RF_PCB OTHER Round trip Allegro to ADS to Allegro requirement: y* D/ g. I9 W# ?/ j( K
903102 ALLEGRO_EDITOR OTHER Zcopy shape command for cline seems not to work correctly.
c+ @- `: O% X1 I& t, ^& v r, W I905562 SIG_INTEGRITY SIGWAVE Noise margin seems not to be measured correctly with Eye Measure function.
' e; B+ w/ o* q: c) p- l909469 SCM TABLE ASA crashes when opening project: k A8 U% ?; |1 ~/ }
909595 APD LOGIC Inconsistency between export die text out and show element after pin swap
9 |2 s A6 U) g7 k/ c911123 CONCEPT_HDL CORE 16.2 Design uprev to 16.5 fails with ERROR SPCOCD-152# }1 m* m/ u" j, g! @
911569 CAPTURE EE_INTERSHEET_RE Q: Why is capture assigning incorrect Irefs in attacehd design ?9 B3 A; \5 p3 l) C" N
915657 ALLEGRO_EDITOR OTHER Allegro PDF Publisher Mirror capability1 M5 \4 v; w1 ^7 w
915755 CONCEPT_HDL CONSTRAINT_MGR Cannot view net in SigXP# d- D" q O9 Z/ ^4 Z) A& z% c! e
916062 CAPTURE GENERAL Auto Wire Crashes Capture
: p( b* y6 H7 x& v% S5 `+ `916820 F2B OTHER RF create netlist with problem
# [' Q- b: I0 }+ k; a917967 ALLEGRO_EDITOR REFRESH Update symbol resets refdes location for bottom side components only.
5 H. H# _, u- t0 k* {919343 ALLEGRO_EDITOR PLACEMENT Place Manual is crashing the board file
' F: m$ K/ f& H7 \5 x919481 CONCEPT_HDL CHECKPLUS CheckPlus isGlobal function is not working
0 K% N7 i3 w/ k* ~! M( O: x! D# ?919510 CONCEPT_HDL PAGE_MGMT takes 10 min to insert page in DE HDL& e+ q' Z: n1 U
919976 APD DATABASE Update Padstack to design crashed APD.3 \* h% E. {) b5 Z1 y9 i
920418 SIP_LAYOUT OTHER SiP enhancement to Auto Assign Pin Use to add ability to change the pin use definition" {( z( O5 O' l: t! A( `. H
920420 SIP_LAYOUT LOGIC SiP enhancement to Logic Auto Assign Net to display a dialouge Auto Pin Use assignment should be run; p" p% i7 z) a g/ W7 d5 i/ F. X+ p
920712 ALLEGRO_EDITOR ARTWORK Program has encountered a problem ... error when creating artwork L. }7 i8 Z$ o0 l+ }2 A# ]
920763 ALLEGRO_EDITOR ARTWORK Soldermask gerber missing thru-hole pins5 |+ d' w% z6 Y p( p! {
920976 ALLEGRO_EDITOR GRAPHICS Question regarding the difference in the behavior of 3D Viewer w.r.t. height_min. Z4 [% \2 A- T2 b: M
920993 ALLEGRO_EDITOR DRC_CONSTR Minimum Metal Spacing Error is detected on Same Net
$ @$ K/ P8 J- l( Z921727 ALLEGRO_EDITOR DRC_CONSTR Pad Boundary causing P/P drc to adjacent symbol.$ g+ E' G4 E8 O9 q9 F. \/ a" z
922579 CONCEPT_HDL CORE Xcon file gets corrupted upon Save of Hierarchical design with Global nets tied to interface nets
" }* Q' \9 f: P5 j922592 CONCEPT_HDL CORE DE-HDL does not report illegal connection when Global Net tied to interface net using an Port symbol and named
3 i* A% i3 _+ @: ?& g, q922758 ALLEGRO_EDITOR DATABASE Allegro crashes while placing second mechanical symbol with route keepin; i8 L" V$ x; |) e, c
922839 ALLEGRO_EDITOR DFA The DFA drc display is unstable.
1 u* |, R6 b/ T923293 ALLEGRO_EDITOR INTERFACES File> Export> IDX is failing for this design while creating an empty error log.# o, y; X0 x$ }5 N; q$ y$ f
924772 ADW PCBCACHE Import Sheet is not bringing in Parts used in the source pages into target cache ptf
3 J6 a( D8 O) K6 G! n7 ], a& N7 @ ^3 T. E' ^% w. L" \+ c
DATE: 08-4-2011 HOTFIX VERSION: 003
% C8 d) s# |$ y/ J8 I5 u7 A4 `===================================================================================================================================
; u; b6 d1 t+ [4 |! [CCRID PRODUCT PRODUCTLEVEL2 TITLE4 }- F9 K) O' U* Q+ a. y; z
===================================================================================================================================
+ q' L; t' u% I! T4 A$ k* N, V9 |787414 CAPTURE PROPERTY_EDITOR Part value can抰 be moved on schematic if a part has been copied to a new design and not saved yet.
4 m5 u# A3 \3 `# H3 j903898 PCB_LIBRARIAN GRAPHICAL_EDITOR PDV move symbol graphics and Undo causes corruption in graphics
7 K# ?# L# t, i0 H; X) M904287 ALLEGRO_EDITOR ARTWORK some cline with arc is missed, when creating artwork.5 ~! E% `" ` E9 n8 T- f
904418 CHANNEL_ANALYS SIMULATION channel analysis sim does not give valid result
8 Y: g0 F* M$ r1 d) y; g905777 SIG_INTEGRITY SIMULATION User gets popup message that halts an analysis until it is acknowledged
5 ?0 c8 Z" }3 w6 t! _. v! T906139 SIG_INTEGRITY OTHER Bus sim result were cleared at the next run even if no preference changed.! s* U. Z+ X: ~+ X
908680 SIG_INTEGRITY OTHER Extra prop delay due to resistance% `6 h' R: L7 |, R7 S) l9 |
909583 ALLEGRO_EDITOR SKILL axlPolyOperation AND operation is not working correctly.
. f( g0 m" t$ e; }: D# Y" X910315 ADW LRM Import Design with ADW causes partmgr and pxl errors7 ^* K+ ~+ M* X3 g
910689 CONCEPT_HDL CONSTRAINT_MGR NO_SWAP_COMP warning after uprev to 16.5( Y6 A5 e L+ p# N1 t& ?
911684 CONCEPT_HDL CONSTRAINT_MGR Attribute Definitions are incompatible for attribute 'HEADER'. when attempting to place in 16.5# @% N l5 A4 i4 x8 B/ M
912343 APD OTHER APD crash on trying to modify the padstack1 ~. w; ~% n# J8 I: [, ]
912384 PCB_LIBRARIAN CORE PDV Symbol Editor often freezes when moving groups objects by arrow keys5 c7 `; |5 Z8 r5 f
912853 APD OTHER Fillets lost when open in 16.3.
9 J2 E# R$ K0 U) d2 X6 q7 Y5 ?913586 ALLEGRO_EDITOR ARTWORK Cannot create the drill figures in this design.! e, V& |* f$ u3 m& c
914009 ALLEGRO_EDITOR DRC_CONSTR Diff impedance worksheet showing almost zero impedance for differential pair in attached testcase.. p4 ?2 q- P% _: f* w( D: y
914110 CONCEPT_HDL OTHER DEHDL 16.5 Uprev overides property values on hierachical blocks
* y* N: w) p7 n; v5 Y$ \914264 F2B OTHER Cross Probing from DEHDL for global nets present inside block doesn抰 highlight in PCB Editor.& m( a2 I i& L9 p. e* H
914309 CONCEPT_HDL CORE 16.5 DEHDL crash on saving the user design
! U7 c0 h3 N/ _# W# V1 u914558 ALLEGRO_EDITOR ARTWORK Gerber6x00 output creates unpainted niche in a shape3 N. |0 o$ D' t6 V7 ^1 N" \1 j
914633 ALLEGRO_EDITOR ARTWORK Artwork failing in v16.5 while the same design when downrev'd to 16.3 is working fine.8 R. W: B) m) N2 Z
914634 ALLEGRO_EDITOR SKILL IsThrough flag for a padstack is reset
: S$ H5 g$ W/ w: [" [) {7 f7 l914746 ALLEGRO_EDITOR DRC_CONSTR DRC Update repeats takes longer on each successive pass.- D$ {8 b5 A) ]; U
914962 ALLEGRO_EDITOR SHAPE Corruption with Shape filling
) j1 s. z6 E( W) G915583 CONCEPT_HDL CORE performance issues in 16.5 compared to 16.3
& ?+ G4 N4 W x915630 PCB_LIBRARIAN OTHER Error when running SI Model Interface Comparison using IBIS models
+ y& { z$ ]. M! N; D915742 CONCEPT_HDL HDLDIRECT I get a newgenasym error and crash when trying to save the symbol$ o2 f/ o P' j' p0 T
916154 SCM NETLISTER scm crashes when exporting physical database to allegro7 s# o1 F" ~4 |' B1 I8 @
916448 CAPTURE NETLIST_LAYOUT Capture 16.5 Layout netlist contains errors
3 \7 ?5 t Q$ R: M0 V1 e8 B916462 ALLEGRO_EDITOR DATABASE Edit>Split_plane>create hangs Allgro PCB Editor7 j- p6 |. c: d) P. @
916469 ALLEGRO_EDITOR REPORTS One Unrouted pin does not show in Unconnected Pins Report
; r# Z3 x% l5 n1 o916495 ALLEGRO_EDITOR INTERACTIV Pick selects components from invisible (Off ) layer
9 i- j/ x" J6 t+ N) X' ?& z3 ^916889 CAPTURE NETGROUPS How to change unnamed net group name?! c" l& V4 b& [- n
917002 ALLEGRO_EDITOR OTHER Allegro PDF Publisher creates extra circles not available on film# z3 M! U! i+ ?! H. r
917434 APD OTHER Stream out GDSII has more pads in output data.
$ v& j* `, Y1 e, O5 r917739 CONCEPT_HDL INFRA Global Net tied to port is getting split into 2 nets in 16.5, in 16.3 it is treated as a single net1 o! A( i/ y/ i% b- p" X
918187 CONSTRAINT_MGR OTHER Missing acGetTotalEtchLength predicate.
' t& R- S/ f, ^' |8 m918576 CAPTURE DRC Incorrect DRC is reported for visible power pins which are connected to power symbol& z5 n7 M# }9 |1 C
- x4 j+ [, k8 C) @: {$ X
DATE: 07-24-2011 HOTFIX VERSION: 002
: ^' V) U9 _! D& L8 Y===================================================================================================================================
' n, v% D2 T1 ^5 ?) Y) A& PCCRID PRODUCT PRODUCTLEVEL2 TITLE
( Z$ K6 a1 e7 H# d===================================================================================================================================
# i! ^, j8 |$ J: h7 I9 @527444 ALLEGRO_EDITOR EDIT_ETCH Slide command needs to be enhanced for same net spacings
. m8 n1 g9 }3 t t# m; N583257 ALLEGRO_EDITOR EDIT_ETCH Add Connect and slide command needs to be enhanced for same net spacings.& {: a* ^3 D4 Q
592956 ALLEGRO_EDITOR EDIT_ETCH Same net traces will not push and/or shove each other.$ H' i7 b& d9 D7 A, v( ~
745285 ALLEGRO_EDITOR EDIT_ETCH Requesting a true "shove" in Route > Slide for Same net routing. [- E1 ~( }4 }- k
773503 CAPTURE OTHER Doing "Mirror Horizontally" creates extra un-connects or extra junction dots in Capture V16.3.8 }6 `! i9 Y5 S
774270 F2B PACKAGERXL Require to ignore space in Pattern setting to prevent duplicated Refdes.
) M4 W9 U. C; h, T, ^799984 ALLEGRO_EDITOR INTERACTIV Enhance the Fix command to select just cline segs: f8 l3 B8 W$ e1 ?" V2 Z
809008 CAPTURE SCHEMATIC_EDITOR New nodes get appeared within the design when we select the design and do "Mirror Horizontally".$ V' u8 S, G4 U3 Y- k% h
810058 CAPTURE SCHEMATIC_EDITOR New nodes get appeared within the design when we select the design and do "Mirror Horizontally".
* v. R6 A2 i4 {" {' [/ G$ }! P2 Z821133 ALLEGRO_EDITOR MANUFACT Output artwork for pad data that are suppressed unconnected pads with Gerber 6x00 format
' N5 `4 K. [) N+ b3 H831710 CAPTURE SCHEMATIC_EDITOR Capture adds extra junctions to design by itself
c P- O2 X& E2 `3 v# E842410 ALLEGRO_EDITOR EDIT_ETCH Ability to slide with "Shove" for "Same Net" segments/vias.& `- b/ m" F8 O+ I
854971 ALLEGRO_EDITOR INTERACTIV Capability to add cline segment in a temp group
: c3 ^8 y6 H7 }4 v' A1 \$ V$ c& v/ s860772 ADW PCBCACHE Save Shopping Cart (pcbcache) is crashing component browser
. ^" p" e, A1 @2 D' V' ]867842 CAPTURE PROJECT_MANAGER Capture crash with 'Open File Location"
4 N! A9 n" I2 h: n5 a% k, j868306 CAPTURE CONNECTIVITY mirror vertically removes junction creates extra nets
3 q* Y3 W0 v" ?, @! [8 y e' {' @882677 EMI RULE_CHECK bypass_plane_split fail if BYPASS_XXXX_EFFECT_DISTANCE1 |# G1 u$ y; {
891439 ALLEGRO_EDITOR INTERACTIV moving cline segments* z3 o2 p) W; K0 o! w# |9 x% c
893544 ALLEGRO_EDITOR INTERFACES IPC-D-356A netlist issue with BB vias.
" O" ]9 u1 S+ N; K1 u. g893765 ALLEGRO_EDITOR PARTITION Mail command not sending out email on Linux platforms.
, i" o R. p+ t6 m7 ~3 P( S; _$ h% M894390 SIP_LAYOUT EXPORT_DATA Generate all balls in the xml file for export to EDI's readPackage command
6 U$ k. T3 K; B, x( B895933 APD DATABASE Update Symbol shifts the center of the Dynamic Fillet and creating DRCs
+ P: w, M8 k* O' q8 \( U896598 ALLEGRO_EDITOR PLACEMENT error message is misleading6 {* s* X# S2 J6 r' N1 }3 D8 m$ W
897196 CIS LINK_DATABASE_PA Schematic Contents are not shown in CIS window while link Dbase part for parts placed from library
" ^% E" S, k+ B1 v" g- t9 f# a898598 ALLEGRO_EDITOR MENTOR Negative planes from Mentor Board Station not being translated.: r% `9 N3 @3 n3 C; p' f
899556 ALLEGRO_EDITOR ARTWORK Import artwork seems not to work correctly.
# z# A7 V8 e+ J* b) \- Z/ K900501 ALLEGRO_EDITOR PLACEMENT "lace Replicate Apply" is showing lot of DRC's during placement of replicated circuit in 16.5
. ]6 x0 @6 e; _901141 CIS EXPLORER Japanese character appear garbled in CIS explorer window.5 s o& S- S9 ]" i
901666 CAPTURE OTHER Home page of Flowcad-Switzerland and Flowcal-Poland is not preserved on captre restart on start page
+ N K3 W# Z0 L( H- q902066 ALLEGRO_EDITOR DRC_CONSTR Shape in Region not follow the constrains4 K7 |! ^/ h; l( E
902349 CAPTURE LIBRARY Capture crashes while closing library# k! w: N, r: B
902508 F2B PACKAGERXL SPB16.5 Packager-XL consumes much more memory than 16.3- }' V1 Z( h) C1 ]+ W" O
902841 CAPTURE GENERAL Capture Start page does not show
& k: I0 @7 @4 V0 f. Y5 E* _7 T902876 F2B PACKAGERXL Packager fails on the design upreved in 16.5" q G) f. ^, f' Z/ x; g2 n$ b
902959 CONCEPT_HDL HDLDIRECT HDLDirect Error while saving design
% C$ G& a3 w7 _5 w9 q4 \$ B903171 PSPICE NETLISTER Why Capture is treating hierarchical power ports as floting nets in complex heirarchy designs?; J% X( T- X( ^- _% {* C
903713 ALLEGRO_EDITOR PARTITION Placement Replication do not work fine in the Design Partition+ C& X2 M9 l) |6 W$ m% d, z
903799 SIP_LAYOUT DIE_EDITOR Disappear die pins after exiting co-design die editor
8 F% w7 A/ ?3 {, f) L3 y904021 ALLEGRO_EDITOR OTHER Export PDF from SPB 16.5 produces a file not text searchable
3 |/ H8 b v7 O: @904339 CONCEPT_HDL CORE new design crashes using the attached CDS_SITE
/ |6 n0 {1 ?; Y904522 F2B PACKAGERXL Part will not package in 16.5 but packages in 16.3& b4 w2 v4 ~6 s) c' q& ]* y7 j. _8 M$ d
904764 APD OTHER Enhance Scale Factor of Stream Out to support 4 decimal places; \8 a: X. p- ?! a* G! m
904771 ALLEGRO_EDITOR MANUFACT Pin Number display issue., b+ }2 W" X# c
904853 ALLEGRO_EDITOR GRAPHICS Enhancement for showing Static shape as it was seen in 16.3
6 E: x2 P! M, p+ F# w' p905144 CONSTRAINT_MGR ECS_APPLY Min Line Spacing is larger than Primary or Neck Gap less(-) Tolerance but No Warning in CM
& J. e! j( q( x( u, s+ o! K905314 F2B PACKAGERXL Import physical causes csb corruption1 b) U0 {2 {' j) R& y. x4 x# R
905337 CONCEPT_HDL CORE ConceptHDL crashes after Import Design process.
4 s. I4 i; g' x( K905533 ALLEGRO_EDITOR INTERACTIV Pin numbers for components on BOTTOM Side are moved in Preselect mode,when the BOTTOM layer is invisible$ N5 q0 \4 V2 L
905796 CONCEPT_HDL CONSTRAINT_MGR Fujitsu CM issue inaccurate concept2cm diff pair issues
! F: \- p& q; d4 \/ t9 L905811 CAPTURE EE_INTERSHEET_RE interesheet references in the form of grid grid page number instead of page number grid0 m; I0 D8 i9 e7 o4 c( _* w! H$ L
906118 CONCEPT_HDL CONSTRAINT_MGR Cannot open CM if SIGNAL_MODEL value was not assigned in ptf.
+ D8 V$ G' U6 D) n! p: e0 M906153 ALLEGRO_EDITOR SCRIPTS Unable to run allegro script in batch mode on the attached board.9 w- m4 }0 p; L, x
906182 APD EXPORT_DATA Modify Board Level Component Output format7 `% A) [( x# t8 v3 B7 U( }2 u
906200 ALLEGRO_EDITOR DFA Enh- DFA drc invoked in Batch mode returns false constraint value in Show Element3 w4 x# N6 x" s9 a( O3 J* o
906517 PSPICE PROBE PSpice new cursor window shows incorrect result.: R: X; `- k# M; i/ ]
906627 ADW COMPONENT_BROWSE ppt options are not read if ucb is launched from FM. works fine if launched from dehdl.
) s8 O1 \: D5 {+ k! }906647 SIG_INTEGRITY LIBRARY lib_dist creates a signoise.log in current directory (with backup files like ,1 ,2 etc.) on each run. t; R2 g1 J! c+ Y7 k( i
906673 F2B PACKAGERXL Ignore the signal model validity check during packaging$ L7 R: g: X5 }$ I; r, S1 N
906688 ADW LRM A copy of source design gets created in worklib of target design after 'Import Design'
. _- w# c6 y3 U/ l/ S906750 ALLEGRO_EDITOR PARTITION Importing design partition removes the testpoint reference designation9 I0 ?/ V! c& ~) ^& w1 p U
906874 PSPICE NETLISTER Error less than 2 connections for unconnected hierarchical pin8 F/ n' D. }* C, u( S3 |
907095 F2B OTHER Part Manager does not show Error as Undefined when directive ptf_mismatch_exclude_inj_prop is used
7 [& i* M6 m8 u907424 ALLEGRO_EDITOR GRAPHICS Allegro add option for pre 16.5 shape display! N; W( h7 c. w0 U; b- d
907490 CAPTURE NETLIST_LAYOUT 16.5 Layout netlist is not correct. It differs form 16.3 layout netlist.' x0 o- L& b0 b0 i4 b, c
907884 SIP_LAYOUT MANUFACTURING Need to add an "NC" pin text option for "Manufacturing Documentation Display Pin Text"4 R, ^+ d% u5 @7 O
907885 SIG_INTEGRITY OTHER Matchgroup targets lost when importing netlist to Allegro layout in HF31- ?- {. b) Y1 R0 ]
907929 CAPTURE TCL_SAMPLE TCL command to delete a property from parts in a library is not working correctly7 F6 b Z* ]+ S+ Z F+ l
907933 SIG_INTEGRITY OTHER Single line impedence not working in OrCad PCB Professional
+ ^( X, `/ Y( O( m% w907963 CONCEPT_HDL CORE Design uprev issue when moving from 16.2 to 16.5
+ r, ]' S- _& f: y908000 SIG_INTEGRITY OTHER Inconsistence z-axis delay reported on Tpoint when define at via location.
0 d5 l5 Z0 J+ \908057 CONCEPT_HDL CORE DE HDL crash with the cut and paste of a signal name
/ h+ Y0 S' G& h7 x4 B0 b" E4 {908060 CONCEPT_HDL CORE CTRL+LMB Option not working correctly in 16.3+ p5 r' n" F! y+ s* f
908210 CAPTURE CONNECTIVITY Connection is being lost while dragging a component2 }6 d0 _, }, n0 ?! u3 A* q- R
908241 CAPTURE DRC DRC error column is blank in DRC markers window in 16.5
, w3 B2 x' M, O2 D908339 RF_PCB BE_IFF_IMPORT mechanical holes VIAFC are not at the right place
0 K; F# m( U! W) Y" B908534 SIP_LAYOUT SYMB_EDIT_APPMOD issues with symbol editor and copying pin arrays
$ A& R* _# L" z908535 F2B DESIGNVARI When I try to view my variant file the variant editor crashes
* L1 L9 R0 H+ }: O* B0 @908595 APD 3D_VIEWER cadence Design 3D viewer" screen pops up and is all black because the colors have all converted to b8 y2 C' C8 z- S, V
908849 CAPTURE ANNOTATE Getting crash while annotating the attached design) T9 V8 e# a+ v! U
908874 CONCEPT_HDL CORE Part Manager - No Part Found error when using CCR# 775788 feature
1 U# r2 x* @# e909077 CONCEPT_HDL CORE After packaging pin numbers remains invisible even when $PN
- ~1 }9 x+ x4 y: r7 _1 p909104 ALLEGRO_EDITOR SYMBOL Warning message needs to be modified. It does not save the symbol and also not tell the actual problem.5 V1 }5 I7 F2 x# Q1 `+ f- v
909417 ALLEGRO_EDITOR REPORTS "report -v upc" returns 'Segmentation fault' on Linux6 I7 e' I# ?7 @5 x$ ~+ L
909635 SIP_LAYOUT DIE_STACK_EDITOR Add Interposer crashes in SiP Layout
, T6 \8 D; n4 @ [ R: U909749 ALLEGRO_EDITOR MANUFACT Allegro Crash during dimensioning
5 |/ }+ B2 l5 i; U7 o* H9 q909760 SIP_LAYOUT MANUFACTURING Create bond finger solder mask doesn't follow the mask opening as defined in the padstack
4 h+ }1 U9 n- M. ?' x909861 F2B PACKAGERXL NetAssembler broken within the latest 16.30.031
2 L' o* r3 @% a* J" a910006 CONCEPT_HDL INFRA Motorola design fails to uprev from 16.3 to 16.5, xcon file is getting corrupted.
4 I5 n7 ^0 z9 T1 W- ?1 X1 f910141 CAPTURE NETGROUPS Modify NetGroup definition does not update Offpage Connector
8 }" `4 Z( U3 M8 G# s910340 ADW LRM Import design in schematic, only 1 page import, the entire block is getting imported.
. i6 H! h! n, a( g( O+ P910678 SIG_INTEGRITY OTHER The Analyze> Model Assignment> Auto setup is not creating/assigning models to discrete components in 16.5. O8 s% B1 ~# u3 i$ I2 j- A0 p
910713 F2B DESIGNVARI Variant Editor crashes when you click web link under Physical Part Filter window.
, q( I* P1 g2 n+ R0 T7 n910936 F2B PACKAGERXL ConceptHDL subdesign net name is inconsistent7 t9 I9 |+ y" ^1 v7 U8 n
911530 ALLEGRO_EDITOR SYMBOL Package Symbol Wizard does not create symbol with the name given
, z6 h, I! v+ i% u5 t911631 CONCEPT_HDL CORE DEHDL crashes when opening a design8 [+ [) E8 J- |( Q
912001 ALLEGRO_EDITOR OTHER option_licenses entries are made in allegro.ini even when not set as default( \% C4 c' N" R! ]% q7 ]
912459 F2B BOM BOMHDL crashes before getting to a menu' n x( N. z* o* F# S! l
913359 APD MANUFACTURING Package Report shows incorrect data7 ~: v1 \8 Y Q: _
, j# Z0 P6 ` U8 hDATE: 06-24-2011 HOTFIX VERSION: 001
% I6 V# J2 G9 O===================================================================================================================================
. e! v+ C) F8 Z/ o' n3 n% B. H0 vCCRID PRODUCT PRODUCTLEVEL2 TITLE' x& L% D# y2 z/ `# D6 q% g+ b
===================================================================================================================================
) R2 \% }$ A) I" A6 k* ]293005 ALLEGRO_EDITOR DATABASE Allegro crash when attempting to move mech. symbol0 Y+ j5 z' K' E9 E* k
298289 CIS EXPLORER CIS querry gives wrong results
. j) f, ?+ r6 Q6 |! F* C4 c366939 ALLEGRO_EDITOR OTHER Cannot attach refdes on silk subclass with add text
9 Y( q; C V: W, Y9 }/ o432200 ALLEGRO_EDITOR MANUFACT Fillets with an arc are required for Flexi designs
- ?7 \9 l6 z+ O$ H- @2 l443447 APD SHAPE Shapes not following the acute angle trim control setting. i2 j& d' X# S" s. e
473308 PSPICE AA_SENS Passing variables to lower level blocks using subparam
3 ~& f h r9 z" @8 l517556 PSPICE AA_SENS Advanced Analysis does not support variables being passed down the hierarchy
6 d. W! M0 K( R: S& ]2 A7 \548143 ALLEGRO_EDITOR SHAPE Dynamic shpe on Etch TOP will not void properly.0 A, d, Z: ?$ _- {/ q$ b
606959 ADW COMPONENT_BROWSE Key properties with blank values are not getting read in shooping cart! b7 s; g5 S- p; X
616466 ALLEGRO_EDITOR SHAPE Solid shapes are not getting filled j& h+ o& S6 ~- L5 c
641358 SIP_LAYOUT DIE_STACK_EDITOR Request for Via and Multi Layer Pin support for DIE stack Area (blue region)
; C+ }' l- f' @644122 SIP_LAYOUT OTHER SiP Layout - xsection - ERROR Adjacent conductive layers are not allowed, but these are diestack layers not conductor
4 i# y+ G# d0 c; F0 p) B1 }645816 ALLEGRO_EDITOR SHAPE Slide a cline all removes gnd shapes on board: s4 \2 q8 A$ A6 ~: O- _! q$ \ U! K
725355 ALLEGRO_EDITOR SHAPE User can not voided Logo correctly.4 @! f0 x2 i# g' N9 d) S! y8 j
763569 CONCEPT_HDL CORE Display status of Hide/Show unconnected pins icon in DE HDL UI
# w& T: v4 N. q0 P8 d770021 CAPTURE BACKANNOTATE Changing pin group property after pin swap resets pin numbers
/ f4 p: ?. f8 d5 `% F9 [792126 CAPTURE PROPERTY_EDITOR Attempt to change display for occ prop resets
( @$ D: r9 u. t& E" a799014 CONCEPT_HDL CONSTRAINT_MGR concept2cm errors not shown in export physical after hier_write) G+ _% P% r8 ~( B* K7 B& l+ V7 T3 e
803147 CIS LINK_DATABASE_PA Link DB part should not change RefDes of multi package part
" v; N/ Z0 R0 d7 m804240 PSPICE DEHDL Problem in simulation result for a multi-section split part.
) |) s( U4 ]5 |809118 CAPTURE NETLISTS ENH to compare two schematic Capture designs
: O4 O. C$ ^8 w+ [816568 ALLEGRO_EDITOR SHAPE shape disappears when update to smooth.. State no etch6 g' ]5 |! v9 R
830053 CAPTURE STABILITY DXF export fails if schematic folder name as /* k; v a/ b/ F0 F
832108 ALLEGRO_EDITOR SHAPE Shape void incorrectly.
4 n1 V( Z9 C4 R. r: h833542 CONCEPT_HDL CORE PDF publisher font is NOT WYSIWIG with respect to what seen in DE HDL
# p3 R. Z, T8 n! c0 j- t1 E' m8 C835777 CIS DERIVE_NEW_DB_PA For XLS, donot display table as worksheetName$worksheetName to avoid 8012 error$ K% I8 i: y2 F8 Z) M W
837640 CIS GEN_BOM date format of CIS BOM has broken macros of 16.2 in 16.3 version0 C2 a# E' z( R" T+ E7 |
844074 APD SPECCTRA_IF Export Router fails with memory errors.! S. Z. ~+ C* K) B% ?: |2 T
851595 CONCEPT_HDL CORE Pin numbers overlap on the pin and increase in size
; b+ H3 l. H# C4 u4 O( x852832 CAPTURE BACKANNOTATE Why is Capture crashing with Mentor back annotation?" T2 e3 o: S0 [. j
855015 ALLEGRO_EDITOR OTHER The rats are NOT connecting to the ends of the clines like they should be.
1 s2 U$ T8 I) ^/ K+ W859883 CAPTURE NETLISTS ENH to compare two schematic Capture designs) x8 p! q" ?+ Z' d6 q
866009 SIG_INTEGRITY OTHER Net with Pull-up/down should not be used for Diff-pair.
8 k7 [7 P4 M$ y v& U0 r866830 SCM REPORTS Multiple lines added as separator between title block and report header instead of single line8 B3 G# p. t: w2 F; j; U s" {
866833 SCM REPORTS Extra indentation is left in the left side of the report when the Line Numbers are set to OFF
5 I( K9 H7 u; }868618 SCM IMPORTS Block re-import does not update the docsch and sch view, d* M5 R L1 A5 r! c3 S( T
873402 SIP_LAYOUT LOGIC pin swap for co-design die in SiP- r9 c3 k; q7 K
874010 SIG_INTEGRITY OTHER PCB SI crashes when the Xnet is extracted with VARIANT_TO_IGNORE property./ U( q8 ^9 } |' {' W: I6 w
874400 ALLEGRO_EDITOR INTERACTIV Flip mode issue with move command
4 Z+ ?& j2 G- p! Z8 s# G3 i874966 ALLEGRO_EDITOR INTERFACES Placed mechanical component do not get Ref Des or part number in IDF file
: m+ t$ _9 J- j875709 ALLEGRO_EDITOR REPORTS Film area report generated incorrect data at l17 @- ^" ?1 l6 a
876275 CONCEPT_HDL CONSTRAINT_MGR Constraint Manager not retaining target net: H# b5 E1 [" H4 m: a' K
879361 SCM UI SCM crashes when opening project$ ?/ l+ ]( N. x+ k# v+ y: ~
879496 CONCEPT_HDL OTHER Customer wants to have the tabulation� key as separator in HDL BOM.
\" g, G8 `$ q8 K; w879514 PSPICE AA_MC Monte Carlo to handle equation as comp VALUE.6 d( L; m9 [/ ] v, F; @
881845 ALLEGRO_EDITOR SHAPE Delete island deletes complete shape/ \* y4 W9 F* Z8 t$ k' y4 B! [ k, O
882413 PDN_ANALYSIS PCB_PI PDN Analysis should support routed power nets/ A9 A: e8 H% e% x; a/ @* {0 w6 `
882427 PDN_ANALYSIS PCB_PI PDN Analysis target impedance should have a variable multiplier1 M2 Q5 E8 J9 S( C. i/ b4 `
882567 SIG_INTEGRITY OTHER PCB SI crash if boolean type prop was specified to VARIANT env.- _, q5 ]; R& }: U. K' {/ y8 p
882644 ALLEGRO_EDITOR PLACEMENT PCB Place Replicate Function automatically match Enhancement
5 }" V) o6 g3 E& f6 _: X6 V \883164 ALLEGRO_EDITOR INTERACTIV Vias marked fanout moves away from position when moving component
( y, d& q }" m' I6 b883224 SIG_INTEGRITY SIMULATION crash while reflection simulation from Constraint Manager3 H' i5 n& W4 f1 d R
883760 PCB_LIBRARIAN METADATA Incorrectly formatted revision.dat file in the metadata folder. q( e8 }& _+ D% E4 i0 v* }4 c
885391 SIG_INTEGRITY SIMULATION RLGC data sampling algorithm and w-element interpolation.$ L( B' i; g4 t, m5 e, r7 p
885849 ALLEGRO_EDITOR MANUFACT Silkscreen Audit cannot find Solder mask for the text string
5 f3 v# Q$ y7 C885996 SIG_INTEGRITY OTHER The effect of sn_maxwidthlimit user preference is not seen in cross section impedance calculations; g) E/ p! @3 L6 `8 w6 z4 H' l: S
886090 ALLEGRO_EDITOR INTERACTIV Add Arc w/Radius does not snap to grid' z& }4 n8 [, ?4 r) ?* y
887180 CAPTURE SCHEMATIC_EDITOR Signals Navigation window doesnt get updated for Buses
) I7 E; \5 D* Q887442 APD SHAPE Copper pour of Dynamic shapes on Top layer which contains many existing signal traces fails.
' E+ ]) h7 ?8 _# d6 `' ?4 P4 K" C887578 SCM AUTO_UI Component Replace pops-up the DSPANE-204 Message) l) R; N, ^1 Q8 J
887926 SIG_INTEGRITY GEOMETRY_EXTRACT Field solution failed if diff trace on bottom doesn't have reference plane./ f3 W( }! x Y$ ?; K
888414 SIG_EXPLORER OTHER View Trace Parameter display the thickness of dielectric incorrectly.
$ x, Z7 v- c5 {# _: j& p; z3 b# C888600 CONCEPT_HDL CREFER Cross References not added to Schegen schematic
* T& ?; K4 A7 z" x S: j* Z) u2 G888679 SIP_LAYOUT SHAPE Can't create the Dynamic shape on layer M1_sig without unwanted horizontal openings appearing.% W$ b, b( m* D' z* B
888804 ALLEGRO_EDITOR OTHER Fillet will become static shape after import from partition board.2 R& `7 C2 T9 x# R( V
888945 CONCEPT_HDL OTHER unplaced component after placing module
# ~. Y1 ^ ?, ~% a$ e; E889222 ALLEGRO_EDITOR SHAPE Allegro freezes/hangs when adding shape as Polygon with OpenGL ON.
+ N [5 f1 b! ~; U* F% W889365 SIG_INTEGRITY GEOMETRY_EXTRACT top/bottom trace impedances extracted to sigxp are wrong in 16.3
4 Q9 |* @" j: q) j( E( i8 O889404 ALLEGRO_EDITOR OTHER Incorrect pad size for Top conductor padstack written to column 59-62.- p% D# `! k( m, g
889426 CONCEPT_HDL CHECKPLUS CheckPlus does not find single node net. b' s6 p! E; S/ S: h
889636 ALLEGRO_EDITOR MANUFACT Incorrect spelling of "Visibility" in "Film Control" tab in the Artwork Control Form+ q2 s- u. B: L2 S v9 E
891235 F2B PACKAGERXL Packager crashes without creating a pxl.log file
1 R! t7 [; t1 x4 ?7 s) I891292 ALLEGRO_EDITOR SHAPE arc routing causes weird undesireable shape fill performance
' p9 s; S% w7 v9 P891856 ALLEGRO_EDITOR EDIT_ETCH crash when sliding diff pairs- N. V4 \! ]% g6 i4 J8 g" S& H
892375 ALLEGRO_EDITOR PLACEMENT Place Replicate Update disband other groups, irrespective Fixed property added or not.9 i# W3 W) S( L& H9 {
892455 ALLEGRO_EDITOR SYMBOL Why the overlapping pins are not reported with DRC?
# n, _, ^8 l0 t& R- F892541 SIG_EXPLORER OTHER Export/Import layerstack through the technology file is changing the layer thickness
0 b/ {/ ]/ b$ A% A% v1 ~( g892766 APD WIREBOND Excuting Finger moving cannot push aside finger to move with together by shove all mode- K; v& L. h' ~' T! i# M( C; Y
892907 ALLEGRO_EDITOR DRC_CONSTR DRC not reported for etch_turn_under_pin violations, [$ \6 a9 |& H6 s% Z* e2 Z
892963 ALLEGRO_EDITOR SKILL Bad shape boundary created after axlPolyOperation 'OR
, W$ P/ ^+ w! B6 m( f892964 SIP_LAYOUT LOGIC Request that Edit Parts List use Dashes "-".
8 w' U, o1 V! D2 d) B& R* b893295 APD WIREBOND Why move wirebond command does not shove wirebonds? This result in drcs.% r4 g- f% d- Y
893706 CONSTRAINT_MGR OTHER On line DRC hangs on partitioned board+ N4 r; p) j7 _ m1 i) I& W) D
893743 APD EDIT_ETCH Route behavior when spanning pads not as expected.0 U1 `; H) X' @' C% ^; P$ b. _) y
893783 SIP_LAYOUT OTHER Padstack Design Editing update File menu with a Update to Design and Close instead of 2 operation
+ L4 g6 Z1 C9 T6 C W894456 ALLEGRO_EDITOR REPORTS Request Net names be added to Propagation delay lines of the DRC report.
3 `, e8 T4 w( e% J8 g) R/ G& Q894499 SIG_INTEGRITY LIBRARY Tool crashes when moving a cline or selecting the Info icon with OpenGL on.
1 T% s R8 l8 B, n# Q6 B894582 APD SHAPE When making a dynamic xhatch Via shapes surrounding are abnormal.- A; \8 ]: }* s; x6 E' D
895542 SIP_LAYOUT WIREBOND SIP design crashing when moving bond finger using blur mode BLUR_BONDFINGER_PRESRV_CON
4 V; d1 o( N% D8 f895591 ALLEGRO_EDITOR PCAD_IN Importing PCAD file fails to get to the point where we can map layers3 ?/ E$ f @: C5 @
895757 APD ARTWORK Import Gerber command could not be imported Gerber data
7 J. f( O- e6 P$ e895964 CONCEPT_HDL CHECKPLUS The CheckPlus command getFileSubstrings is not working correctly
$ H( j8 R9 Z, _) F896428 SCM UI Changed Ref Des value not maintained in DEHDL block when part is replaced0 Z& A' `& h0 a. z4 B0 f
896655 CAPTURE EDIF Import/Export Design of Hierarcy design with OrCAD Capture
' U, |7 m7 [; s/ @% b896846 CAPTURE IMPORT/EXPORT Import edif2cap and capture is crashing; P8 m. [0 }( e4 Z& b) ?. p( d
897155 ALLEGRO_EDITOR REPORTS Copper coverage in L2 and L7 looks like the same but film area report had large gap.( R* g' }+ Y" N! g
897654 CAPTURE EE_INTERSHEET_RE Capture crashes on adding intersheet refernces in abbreviated format on attached design.
$ K1 P0 e- z! a& Z899344 RF_PCB BE_IFF_EXPORT dlibx2iff does not provide the component boundary drawing
* C5 D4 J* p X }* p899629 CONSTRAINT_MGR OTHER ECset for Total Etch Lenght is not present in OrCAD Prof. H0 T* V, u6 q! _1 \5 u/ f4 q
900175 CONCEPT_HDL CONSTRAINT_MGR Few Xnets are lost from Match Group after packaging and importing the netlist to board file.
, N7 l3 L7 k4 q/ c900481 CONCEPT_HDL CORE Genview creates a larger symbol without taking the no. of pin in consideration
V" _) G: @3 x/ n( y* l* `900813 ALLEGRO_EDITOR DRC_CONSTR With rotated pads, pad (pin - via) soldermask spacing DRC is unreasonable./ m" `/ c- C" Z8 P
900905 PSPICE STABILITY Simsrvr crash and RPC Server unavailable error while running simulation.
$ O" k5 u' K$ S901783 CONCEPT_HDL CORE CDS_PART_NAME is annotated on the schematic canvas after running back annotation in 16.5' y0 ]+ w! T1 i* W7 p$ _) B; J
901909 APD EXPORT_DATA The "package_pin_delay_length.rpt" with Z-axis delay turned on seems wrong% N" w+ `* y# b D& }
901987 CONCEPT_HDL OTHER SPB16.5 zoom fit does not center the page while ploting the schematic page
' ` @+ Q% Q! U2 U& K- ]9 }1 H902133 CIS OTHER The visible part property value are being shown very distant from part graphics on schematic+ u1 R: K3 z, U+ |4 z$ t* ]& I# e
902166 SPECCTRA ROUTE Specctra crashes when reading in "bestsave.w" file
{- E8 `& b3 W* ]! ^3 E e902170 ALLEGRO_EDITOR DATABASE Diffpair Issues with OrCad PCB Designer Professional( A! }0 L( x5 r) A' [
902177 CONSTRAINT_MGR CONCEPT_HDL Option to view the layer thickness in CM worksheet through worksheet customization
+ m1 X& ]3 e/ q+ \% ~( V8 Q z902463 ALLEGRO_EDITOR INTERACTIV APD crashes when we click ( show element ) on certain components
( b& O' o2 M) E3 _# U+ n4 [902621 CONCEPT_HDL OTHER Design Differences (vdd) Crashes0 ?4 L4 x! B, G/ G
902909 APD WIREBOND die to die wirebond crash
& X; y% A2 k6 }3 V2 v" m902933 ALLEGRO_EDITOR PADS_IN Pads_in fails while reading PADS ASCII file body: |6 C" M" e- Y8 ]0 V8 B/ F, y- k% L
903284 PDN_ANALYSIS PCB_STATICIRDROP IRDrop voltage gradients are plotted outside of the PCB outline4 s6 W5 \1 c" H" r$ f o$ m
903680 CONSTRAINT_MGR ECS_APPLY Constraint Manager not passing all hiearchical member objects to a custom measurement.9 K8 }7 h+ N" R/ `
904403 ALLEGRO_EDITOR DATABASE Allegro crashes when refreshing module |
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发表于 2012-2-21 14:58
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