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" v) I; B# U) S0 }2 D! V: {DATE: 02-17-2012 HOTFIX VERSION: 0161 a- N( n, m3 Q4 ]. @+ b
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6 h# c9 X G+ ^! Z' ]CCRID PRODUCT PRODUCTLEVEL2 TITLE' Z% w( C$ p2 S! P
===================================================================================================================================
- O# R' ?3 y' E, Z: }840105 PCB_LIBRARIAN USABILITY PTF subtype is getting changed when Save As option is used in PDV
4 f% }. E H' @) X$ J; ?: p873075 Pspice PROBE Decibel of FFT results are incorrect., j2 Y, m% v0 i% q
938744 ADW COMPONENT_BROWSE Need ability to customize shopping cart columns to include any Part property A% ]& Z9 O, O2 x
943003 SCM REPORTS The dsreportgen command fails with network located project
& L) m5 _" a$ B3 _8 f961530 allegro_EDITOR INTERACTIV The problem of Display measure command5 K' N8 p6 A" z8 j! O
962157 concept_HDL CORE Where is the setting for enabling the Enable PSpice Simulator menu?
; `0 Q5 m; n b5 h/ a# t962206 CONSTRAINT_MGR CONCEPT_HDL Import physical not passing all constraints from the board to frontend+ T, M8 Z/ j; u/ A0 S' r# S1 t( h
968205 PSPICE DEHDL_NETLISTER Change SPLIT_INST property to PSICE_SPLIT_INST for Quad Switch type of design.
e9 W8 f+ W6 J4 t968509 PCB_LIBRARIAN METADATA Incorrect pinlist.txt was generated if DIFF_PAIR_PINS_POS/NEG was set.
/ B& I/ v: s4 `) U0 [969450 LAYOUT TRANSLATORS orcad Layout to Allegro Translator crashes
( g& u, j" E, \969997 CONSTRAINT_MGR CONCEPT_HDL ERROR(SPCOPK-1053): Cannot find a ppt part that matches the instance pro~
% F1 I. Q6 g- G971193 CONSTRAINT_MGR UI_FORMS Copy and pasting a formula causes the application to crash on windows.
9 e8 |: I, Y2 }/ g& V2 ]971601 CONSTRAINT_MGR CONCEPT_HDL ERROR(SPCOPK-1053) and WARNING(SPCODD-66) because of directory structure
7 g+ Z* Y: G$ E# L2 C973398 CONCEPT_HDL OTHER It should be not packaged with error while working the packaging process if the design has a ERROR
" l) C4 A8 K9 R973859 PSPICE ENCRYPTION Pspice crashes with encrypted model
8 h/ `% ]9 v0 n; M973938 PCB_LIBRARIAN VERIFICATION pc.db is missing9 A6 Y& s* Q/ h% b
974540 CONCEPT_HDL CORE Graphics updates are real slow* ?3 G$ W' Z: `9 v# a: P
974791 F2B DESIGNVARI Variants are not back-annotating to schematic and turning to ?
7 E" ]! }) T Z974818 ALLEGRO_EDITOR NC Backdrilling produces 0 plunges yet no errors reported.
, p2 G2 o4 D5 E! v974945 ALLEGRO_EDITOR skill Why is axlPolyOperation is giving different result and not working
! J' N" W+ Z8 w2 L' L! z8 K( I974946 MODEL_INTEGRIT TRANSLATION ibis2signoise returns the error - Delay measurement fixture must contain V for ECL technology1 o3 p( a V/ z8 |
975396 CONCEPT_HDL CONSTRAINT_MGR Constraints are dropped after migrating from 16.3 to 16.5
" a3 l/ b3 [" j8 {975633 ALLEGRO_EDITOR GRAPHICS 'dynamic_layer_visibility' option in 3D Viewer when checked or unchecked should not change (until next change)
+ m( E/ @9 K0 _975720 ALLEGRO_EDITOR DRAFTING Datum dimension lines not adjusting to text move0 b, `) ]7 \% {! H6 E% d* z8 k
975745 ALLEGRO_EDITOR SKILL cdsServIpc different 16.2 vs 16.5 when Allegro exits5 V7 s( v# I- m$ ], a) R
976013 CONCEPT_HDL INFRA Power pin connection of FPGA symbol is missing in netlist.: w! Z! Q. e N
976058 CONCEPT_HDL COPY_PROJECT SCM Copy project does not create the con and dcf files in tbl_1 views
7 |) s' v j/ X976073 CONCEPT_HDL COPY_PROJECT All the constraint data is lost in the SCM copied design; p! _8 ]1 h: s. l6 A3 M& G
976160 CONCEPT_HDL CREFER Cref fails due to some Caeviews error in the design% v2 Z, |# R. o! D( {
976204 ALLEGRO_EDITOR DRC_CONSTR Application falsely reporting Mechanical Pin Antipad to Shape Spacing DRC- T% d# p+ S4 `" A: o
976448 F2B PACKAGERXL ERROR(SPCOPK-1069): Invalid POWER_GROUP property value7 B2 X5 H* P/ }( R) ?; L) X3 S# v
976521 ALLEGRO_EDITOR DRC_CONSTR multi-thread update DRC causes the application to crash6 @1 A% Q+ T7 n
976838 SIG_INTEGRITY OTHER Unable to create XNET for highlighted nets on attached database even after assigning proper Signal Models.1 ~( I4 y6 } P3 w8 n6 X1 f' t
977517 F2B PACKAGERXL Export physical fails after update to 16.5 from 16.35 u: D8 p6 v* p; X6 d% i0 P
977902 ALLEGRO_EDITOR DATABASE generate module is crashing allegro' _1 Q7 Y9 u5 M' F5 L3 m0 x
978652 ALLEGRO_EDITOR pads_IN PADS_IN fails with ERROR: Finished with errors.
% m% Y" ~" N4 G* F978744 APD DEGASSING Some shapes will not DeGas on this design4 m' Q( C0 p# m
979940 SIP_LAYOUT OTHER SiP Layout Leadframe autobonding with profile selection( k, g6 W' R# O) k
981699 CAPTURE HELP Start Page still shows Hotfix 14 after installing Hotfix 15
8 l( v7 ^2 p' w% z
8 u0 l* y. J. @" q% p. `DATE: 02-03-2012 HOTFIX VERSION: 015" u3 j1 q# B/ V* s9 G
===================================================================================================================================
1 d0 I1 {+ U4 ]0 ^8 B% TCCRID PRODUCT PRODUCTLEVEL2 TITLE
8 C& V+ l, v) u$ u' h7 }4 O===================================================================================================================================
7 m( i; v+ j3 F1 t, f: v8 q! Y871567 CONSTRAINT_MGR SCHEM_FTB Ability to filter out Single Node Nets from Constraint Manager: d* p) D/ S* k+ X! I+ D. v# R
921436 ALLEGRO_EDITOR MANUFACT Change in 'decimal place' for new dimension changes the already placed dimension
3 |; g: `1 a* M! v$ M941433 CONCEPT_HDL COPY_PROJECT 16.5 Copy Project should warn if trying to copy a 16.3 design8 n+ ]1 j% A# q. {% H
954375 ALLEGRO_EDITOR MANUFACT Change dimension accuracy for few instaces of associative dimensioning5 g0 i( j: A1 N0 A
961646 PDN_ANALYSIS EMVIEWER EMViewer Help > About shows wrong version: e4 h+ G+ T) O( u3 x# O1 ?
964912 CONCEPT_HDL COPY_PROJECT ASA project crash after using copy project
& r& a7 t0 u6 @9 y3 [& o967223 ALLEGRO_EDITOR MANUFACT Bug:Oval slots orientation in one direction only
/ s+ H$ s/ U# i/ S' ], A968865 SIP_LAYOUT DIE_ABSTRACT_IF load of die abstract fails due to differences between component and symbol) v) X7 T9 j, b7 B
969485 ALLEGRO_EDITOR SHAPE Shape does not update correctly in 16.5
7 E; M0 X* g- a, K9 B% N970331 CONSTRAINT_MGR ANALYSIS Impedance worksheet shows a zero value for impedance S) G, g4 a5 a& h
970600 SIP_LAYOUT SYMB_EDIT_APPMOD Option in Die Editor to be able to "physically swap" pins
& Z" @* s" |) R3 V970910 F2B PACKAGERXL Our customer has problem with pin color after pxl 16.5.
, |; S: F# u: P& q9 H% A970970 SPECCTRA FANOUT Fanout Vias is placed far away from decaps and does not change the Fanout length even when max_length is reduced.6 O! b9 `# G7 |; K1 x$ W6 l! ^
970985 SIP_LAYOUT OTHER Importing a .spd2 database file using NA2 will cause the APD/SiP tool crash
( H0 |7 i. n7 W- W% q971757 CONCEPT_HDL INFRA Crash while Saving/Packaging the Design) c+ J! u) D7 i, w' u! l; |- S: u
971923 ALLEGRO_EDITOR MANUFACT Allow to change decimal accuracy for dimension instances; M# R+ m1 [, }
972568 CONSTRAINT_MGR UI_FORMS Tools >Excel missing from CM0 V! J+ I% O6 r D, }6 U2 O
972821 CONSTRAINT_MGR CONCEPT_HDL connectivity server warning: Unable to add property WEIGHT
! S2 U) X3 S! g' z7 n973185 SCM CONSTRAINT_MGR ASA2 block not seeing all instances in a package. d& Q! R9 M) t2 _& u5 A
973211 ALLEGRO_EDITOR INTERFACES IDX Object Type Change not recognized
; Z- h0 n$ n. d973214 ALLEGRO_EDITOR INTERFACES IDX import package keepout height value change assigns incorrect value
3 N! J6 \6 N* x0 y3 S8 V" l973384 CONCEPT_HDL CHECKPLUS The multiple SIG_NAME has to be occurred an ERROR at the SPB16.5.
" k, Z* [3 G% i) z) @973514 SIG_INTEGRITY OTHER Mapping error when Ecset is updated to constraint manager from extracted net* L; \( H" C: w3 D% t/ u
973950 ALLEGRO_EDITOR SHAPE Update to smooth crashes application2 A2 |0 V* m( y- g0 \, X
974533 SIP_LAYOUT OTHER Crashes in Edit > Die Properties and obviously has a setup problem.; ]8 O# ~ g' l! u% y3 U0 l+ n
974809 ALLEGRO_EDITOR SKILL argument available for hiding a property with function axlDBCreatePropDictEntry is not working* z0 ^* Z- E. b5 `
976179 INSTALLATION ISR Installation of ISR S014 to 16.5 on windows is breaking the documentation index
: E' o9 p5 S. M
4 C) A+ U8 d6 i- tDATE: 01-20-2012 HOTFIX VERSION: 014+ T6 |" U3 {4 H, O' T2 G9 t
===================================================================================================================================
2 {" t3 n% a9 P' @, lCCRID PRODUCT PRODUCTLEVEL2 TITLE
8 H7 X7 H! M/ `$ D! \" Z% h' M===================================================================================================================================
a; i) O1 J. y' Q$ ]4 x733285 PSPICE SIMULATOR Enhancement:In server-client installation use existing index file from server$ M' T9 W% |8 K6 \! W+ D, P2 F) [
941020 SIP_LAYOUT OTHER Soldermask enhancement
3 G+ f; S' I8 U( X) x946407 CONSTRAINT_MGR TDD When is it safe to open a 16.5 design in 16.3?7 _+ o" ?( j# \" H7 X
953067 CONCEPT_HDL OTHER Variant Editor "Error/Warning messages" form is unusable
1 V5 Q6 f2 _8 C, H; U954818 CONCEPT_HDL COMP_BROWSER Replace button turns to Add in component browser when a component replace is done on the schematic( z$ q1 N. Z4 ^. M
956450 ALLEGRO_EDITOR DRC_CONSTR Analysis always shows analysis failed in uncoupled length in some diffpairs8 k2 @+ T: a3 Q0 B' i2 ?) c
958259 F2B DESIGNSYNC ds.exe crashes on a big design when accessing the design from network drive- o3 W: ?+ g2 I- Z N2 R
958395 ALLEGRO_EDITOR SHAPE shape voids won't merge
8 B# l8 F K" p( w8 G2 n, s959212 MODEL_INTEGRIT PARSE Attempting to use "Mark qualified" option on DML File results in dmlcheck and Modelsim wanrings.# Z7 H2 w3 U b @- P
959940 APD AUTOVOID Void all command gets result as no voids being generated.. r( b3 y: M: |2 t6 d
960252 PCB_LIBRARIAN CORE Splash screen in PDV prevents showing error message& z" v5 Q6 P! D _
961634 PDN_ANALYSIS EMVIEWER Cannot launch PDN EMViewer from withing PCB SI/ ^) T: _7 f+ q9 d6 B/ B1 p" m+ E
961645 PDN_ANALYSIS EMVIEWER Standalone EMViewer will crash when opening any result file in the form of *.emv file. D* ^3 T( `( z) t7 ~* ~% M9 w. `
961700 ALLEGRO_EDITOR SHAPE dbdoctor reports ERROR(SPMHUT-144): Illegal arc specification& p$ }: y1 w& q0 I8 y$ v2 W
961733 ALLEGRO_EDITOR SKILL Allegro crashes. Appears to have a memory leak.8 y; _: u2 z9 {+ |+ {8 f
961758 ALLEGRO_EDITOR DRC_CONSTR DFA check produces no DRC when the dfa bounds are not a rectangle.& v0 _" U. j2 `3 F. Q {. ?* P' k
961887 CONCEPT_HDL CONSTRAINT_MGR Match Group created from ECSet cannot be deleted in the same session of CM3 p* j7 f7 ~7 x$ i! ]
962552 APD EDIT_ETCH BUG:APD crashing when we try to slideget information but move works fine2 a+ K: d* U- x+ p% f$ s
962869 CAPTURE STABILITY Capture crashes after RMB click on rotated parallel wires! A3 C) k9 z+ Y9 @4 C
963232 CAPTURE MACRO Macros not being played in Windows76 Q) D, g& _+ ^: t7 ^' ?. z/ z+ B
963300 ALLEGRO_EDITOR DATABASE Create > Module crashes in 16.5 but not in 16.3
, C7 A- n3 K" q: _' M+ I1 \- o3 j963651 CONSTRAINT_MGR CONCEPT_HDL ECsets are renamed after packaging on linux
4 a4 w% }5 N5 t, z1 v6 |' `' C& _963663 CONSTRAINT_MGR ANALYSIS Q- Why the customized worsheet for Diff pair Impedance not analysing at all for this SIP design
- x6 E0 p: ?: a, ]" \$ l( L963715 SIG_INTEGRITY OTHER Application only adds the bottom conductor thickness for the via z-axis length: ?9 B2 x; j' r7 H3 y! K
964068 ALLEGRO_EDITOR INTERACTIV Allegro crash when using move alt sym mirror alt sym...
, l6 `. C- Q9 W% H5 P5 S964267 CIS PART_MANAGER Capture become non-responsive, working on Part Manager and creating CIS BOM, for large designs
+ }- N- B, C7 m% r964597 ADW LRM Issue of LRM license checkout after renewal license by 16.5 (ADW15.5_S23+SPB16.3)1 J& F) X/ G1 `5 O; w# L: P
966148 APD INTERFACES Character Limit for DIE Files (*.die) Import. C# g& v& J! |$ ?
966416 F2B PACKAGERXL Cannot package this design! O! Y) Y8 E: Q Q( p
966421 CONCEPT_HDL CORE DEHDL Crash when applying property on components in duplicated blocks
# ]& C; {2 e4 |. M! R% `966693 CONCEPT_HDL CORE DEHDL crashes when doing model assignment if CM is open
: X" v7 s, u+ m+ N966795 ADW ROLLBACK rollback utility does not honor -product option from command line. j7 t r4 F ]: T8 U, a
967089 SIG_INTEGRITY OTHER Matchgroups created by ECSet not deleted when ECset is removed from object.
) x$ G$ O) Z) P$ L967222 ALLEGRO_EDITOR OTHER PDF export is leaving data off the drawing, N5 L% i2 o5 \0 y% t4 I& ?# |7 j
967240 SIP_LAYOUT WIREBOND Change default bond fingers selected on multi-site leads during "bond to leads" program# `6 m; Q$ `6 Z& L( f
967297 ALLEGRO_EDITOR OTHER Dynamic Fillet&Eliminate unused stacked vias cannot be used as the Miniaturization option.4 k; e& v$ D3 P
967576 CONCEPT_HDL CREFER Occurrence location property values do not appear in flattened schematic generated by CreferHDL
. o$ Q/ C- `: h968096 ALLEGRO_EDITOR DRC_CONSTR Mechanical Pin to conductor spacing is not followed. H( U) ~. t' ^
968222 SIP_LAYOUT DIE_EDITOR die pin loses IC net for a co-design die with multiple ports within IO-cell6 b/ `( d: a) J Y# F- H. D
968358 CIS PART_MANAGER Capture crash on removing a part from subgroup in part manager, f( Q# D0 {8 c, }) B% Y' `, ~- T
969594 CONCEPT_HDL CORE The dcf file is not updated with schematic changes+ y$ r7 w @$ G8 m2 i
* I7 w( l$ s) qDATE: 12-16-2011 HOTFIX VERSION: 013( r* k: x* J" |8 |
===================================================================================================================================
6 L5 G; \0 z' M, r( J/ RCCRID PRODUCT PRODUCTLEVEL2 TITLE
' o7 ] ]: O, @6 D$ S9 \===================================================================================================================================, g s- w5 }% K: k) d: a% [1 S
875695 SIG_EXPLORER INTERACTIV Enforce Causality check box doesn't work.0 x' @) ^1 r4 k. \+ f
927148 CAPTURE PROJECT_MANAGER Capture crashes on creating scehmatic folder with name which already exists in design' Y6 ~# _3 h, g( z# V) M% q9 S- N! e2 }
938013 CAPTURE NETLIST_OTHER The netlist in RINF Format contained two identical lines for PCB FOOTPRINT
6 S! r: K, T1 I0 `' k4 E( G941409 PSPICE PROBE BUG : Search accuracy wrong in new cursor window
: N, E: v$ i4 o1 S0 }/ F945242 SIG_INTEGRITY SIMULATION Unable to select "shapes" in find filter for 'show parasitic ' command
) {0 X8 w3 e1 C% x" q- r946293 CONCEPT_HDL ARCHIVER Archiver hangs if there is a whitespace at the end of the path of cref.dat
, _) Q a7 g1 h+ m( A8 j946770 CONCEPT_HDL CORE 揤iew Design� function is missing in Windows Mode after reseting the menus.* ^; u& v/ b3 i/ u
950994 CAPTURE NETGROUPS Problem in expanding the netgroup in Auto Connect to Bus function
9 m& q) c8 u2 Q9 t8 _5 A953530 SIG_INTEGRITY GEOMETRY_EXTRACT Display Parasitics is displaying wrong results for EMS2D Field Solver compared to topology extraction using Probe.. N* S( H: Q# E, }* s( s7 [
953713 CONCEPT_HDL PAGE_MGMT Random page replacement/duplication in block
3 k1 B7 S3 f+ o5 ], a0 f9 x8 w9 C953917 CONCEPT_HDL ARCHIVER archcore should handle errors correctly8 {5 b" U7 d) t7 I; L) h! A! z0 E
953971 ALLEGRO_EDITOR MANUFACT NC Drill files not generated correctly when using the option "搒eparate files for plated/nonplatedholes�' |8 Y6 x* ]2 [3 {! \' x# g! ~
954400 CAPTURE NETGROUPS BUS members of NetGroup are getting converted to Scalars in Export-Import NetGroup.
# O1 E' [8 i& G954498 SCM B2F SCM crashes when importing physical6 y0 s; G% Q; \$ E. s
954623 ALLEGRO_EDITOR EDIT_ETCH Unable to complete connection with Add Connect - related to soldermask to cline check?( _* m8 [. Y+ S+ Z7 i0 }
954894 ALLEGRO_EDITOR MANUFACT Dimensions disappear when opening database in v16.5 from v16.36 p# T4 V- t) ?2 g& g
955029 CONCEPT_HDL CORE custom text font size not recognized in symbol view) S& n9 a% c1 ^4 @
955133 SIG_INTEGRITY FIELD_SOLVERS The Field solver creates the differential trace model which is reversed T(D1) and T(D2) of bottom side.
( Q$ T" E& X( s; v955290 CAPTURE DRC Description for UPD0014 missing in the Browse DRC markers window$ S5 z3 F3 p) ~$ o# m
955299 ALLEGRO_EDITOR DRC_CONSTR drc text to smd pin does not work any more on this database in 16.3 S039
, t# }0 d/ K. W" w" h+ E955338 CONCEPT_HDL CHECKPLUS Need to change PART_NAME
, ?2 R# z" j3 |- x8 i4 E/ W955447 SIG_EXPLORER OTHER Model path set in DE HDL Model Assignment not used by SigXP from CM in DE HDL: y+ L, d7 I/ y g' H# r) P$ O/ S
955740 SIG_INTEGRITY GEOMETRY_EXTRACT Crosstalk with Timing Windows does not work correctly3 F' j& h2 b) {) N
955749 ALLEGRO_EDITOR MANUFACT show element Info shows symbol dimensions on incorrect subclass- W3 j: b" m9 Y9 d1 Q# u9 A
955912 ALLEGRO_EDITOR OTHER Shapes with voids that are exported to PDF have gray filled area over the void# w: l1 ^4 F' D, ^3 h( {
956129 CONCEPT_HDL INFRA DEHDL uprev hierachical design from 16.2 to 16.5 packaging failure.
4 K5 U3 ~' a: Z" ?2 W I& ~956373 ALLEGRO_EDITOR NC drawing name doesn't display in the log file
6 d8 Y" f! ?" b3 m956393 CAPTURE PROJECT_MANAGER "GENERAL" and "TYPE" tabs are missing from " roperties" dialogue box.# W4 K0 A' s+ C+ {
956448 PSPICE MODELEDITOR Can not generate a DEHDL symbol from Model Editor, because no Capture license found
) }& J+ y b0 f5 y9 I' \& Z956456 CAPTURE NETLIST_OTHER OrTelesis netlist not transferring user properties defined under combined
" j" `# q8 \ N2 U* x+ d956489 ALLEGRO_EDITOR MANUFACT dimensions lost when symbol with diemnsions attached to symbol origin placed on board
# w. B+ `2 c- J$ N: Y7 C$ U% X0 \956603 CONCEPT_HDL OTHER Part Manager "has stopped working" after changing a component, a. E- I, ^3 [
956751 ALLEGRO_EDITOR ARTWORK Import Gerber command does not work correctly
" l2 h) z$ z1 F: @6 W/ |( [956847 PCB_LIBRARIAN METADATA PDV - Partdeveloper symbol to function linkage broken/changed in 16.5; E9 | v3 s& D; K
956987 CAPTURE OTHER Find from "Search toolbar" doesn't gives complete results o2 {/ X3 r3 \. X4 X$ p# z
956996 CONCEPT_HDL INFRA Correction to ERROR(SPCODD-7): Following Primitive instance causes CM to empty$ K+ o5 D, J. H5 l! N& q
957009 CAPTURE NETLIST_OTHER Problem getting database property in mentor PADS PCB netlist& Z( n% G7 D1 Y
957137 APD DXF_IF DXF out command dose not work correctly.2 q2 X) ?( v' q2 X J- Z3 v6 y
957167 APD GRAPHICS Highlighting for Static shape with display_nohilitefont environment variable.+ }% x; B+ m" \! o7 [
957232 SIG_INTEGRITY OTHER Allegro crash during Model Assignment.
- `. p# x3 A) Q: e1 K' T, Z: _( q$ T957267 CONCEPT_HDL INFRA Packager Error after Import Design
0 R6 ]/ `5 ]+ @957866 SIP_LAYOUT DATABASE Cavity outline is not getting deleted from symbol file- q, v v/ O% E( F
958010 ALLEGRO_EDITOR REPORTS Wants the ability to extract "Batch" reports from Partition ".dpf" files.
" b9 o0 }7 | R3 E" l1 a: {958252 ALLEGRO_EDITOR TESTPREP Resequence testprep with the option - Delete probes too close crashes the design3 o0 i1 ^- ^- I- m
958253 ALLEGRO_EDITOR REPORTS Shape did not have thermal relief connected to pin but unrouted nets still shows zero.7 }2 ?8 b' k' Z) T% L
958433 ALLEGRO_EDITOR DRC_CONSTR False embedded component DRCs6 h6 s7 m+ \. a w& u/ @# R
958753 ALLEGRO_EDITOR SHAPE Dynamic shape is getting corrupted in 16.5, ^( D. r( U6 ~6 e
959011 ALLEGRO_EDITOR OTHER copy problem of via and cline$ S! S# S' e* B/ O
959101 ALLEGRO_EDITOR EXTRACT Using extracta with excluding Thermal reliefs
/ S. ]: i8 t& ]0 i- ?959253 CONCEPT_HDL INFRA Design will not open8 S; z6 _) x* z& t
959299 APD MODULES Getting ERROR(SPMHDB-279) when trying to update modules placed on the Top side$ B- s) M6 S( q* u T5 J L5 {
959884 CONCEPT_HDL INFRA Design Uprev/concept2cm crashes with Application Error/Out of Memory Error.1 L( Y$ P. F& v3 \8 \# Y% E
959909 ALLEGRO_EDITOR SCHEM_FTB Site level propflow.txt file is ignored property is transferred9 y* c; L" y1 [ V
960067 SIP_LAYOUT PLATING_BAR Creation of plating bar removes "NODRC_ETCH_OUTSIDE_KEEPIN" property from the clines.
/ j1 w- z6 K4 o* l1 R960126 SIG_EXPLORER EXTRACTTOP Allegro PCB SI license is used automatically at Topology Extraction of Allegro Physical Viewer." S: X+ L7 V+ ~6 b) k+ V/ b; p# j! |% \
960143 SIG_INTEGRITY GEOMETRY_EXTRACT Running simulation in Bus sim happened crash while enable Coulpled Via model to S parameter
+ ~7 N9 c; L$ j961349 CONCEPT_HDL HDLDIRECT Motorola designs have broken connectivity compared to 16.3
. t F" z) X) ^7 D7 r( I961816 ALLEGRO_EDITOR INTERFACES Normal Export > DXF fails and offsets the pins of the BGA symbol0 `! W7 @( V/ M+ B$ f
962519 SIP_LAYOUT WIREBOND Align option doesn't work for wb_tackpoint fingers1 E" Q( l5 r Y+ E0 P( y
7 ]/ J2 e* u- x: |DATE: 11-30-2011 HOTFIX VERSION: 012
' Z3 G$ C r% y: t' I; ]9 _===================================================================================================================================; t( r7 d$ g" Y. P
CCRID PRODUCT PRODUCTLEVEL2 TITLE
# y. `; z# C: `3 `9 U& U) _( U===================================================================================================================================
- P: j- _+ ], d9 Q9 x4 A/ V8 L959581 CAPTURE NETLIST_OTHER PCB Footprint is getting replaced by VALUE in OTHER netlist formats& ]) `5 n& S; ]+ S# I
8 Y, b# ]' J& Q0 c
DATE: 11-18-2011 HOTFIX VERSION: 011; Y1 H4 c' {. s) P$ m9 ^0 v: F
===================================================================================================================================
! \1 A/ _7 H# c) [CCRID PRODUCT PRODUCTLEVEL2 TITLE
4 S$ [4 f8 R- e$ {7 R% l& p4 W===================================================================================================================================
$ B# J) l1 w$ `' i' m735439 PCB_LIBRARIAN CORE PDV Moving line-dot pinshapes by arrow keys breaks the pinshape
, ^; t2 a8 {+ i6 [% j w# O894815 CONCEPT_HDL COMP_BROWSER Why does genlibmetadata command give 'Aborted $PROG' Message? b7 z4 ~7 L' O4 ?* {4 L
903073 ADW COMPONENT_BROWSE datasheetl_url directive should support a display string for URL
! W$ }8 a: ]/ O+ e6 i7 P/ F9 F909919 CONCEPT_HDL OTHER Why is the PublishPDF UNIX command line looking for "true" script?
" f b# M! ^. G0 b! A/ J911561 CAPTURE CORRUPT_DESIGN Capture crashes on trying to save the design.+ x9 @$ P7 c3 K* r* j9 V! C
919579 CAPTURE PRINT/PLOT/OUTPU Print mode be selected based on schematic mode8 r) @4 p+ g c3 r/ N, H: r* }
921247 CONCEPT_HDL COMP_BROWSER genlibmetadata.bat file does not have err defined
0 A. Z- ?0 ?0 L0 \5 R. ?925182 CAPTURE PROJECT_MANAGER ENH: Feature to run update cache on all the parts in design cache at once.
" r \/ q: y2 r, L0 _# g3 y" a926858 CONCEPT_HDL CORE Usability- Modify Component dialog forces user to do 'Reset Filters' to see other ppt rows& n7 e+ Z$ C; Q; l: B. i; c
927657 CAPTURE NETGROUPS Enhancement: Placement of netgroup definitions under design cache list1 c9 E( k: I: ^9 t: h& P
934684 ALLEGRO_EDITOR MANUFACT The relation between the linear dimension and the symbol breaks./ \% @3 b) F4 w/ a' I$ _
935836 SCM SCHGEN ASA crashes when generating Flat Document Schematic
4 T3 q+ Z1 R9 U937165 SCM SCHGEN Can't generate Schematic
; T8 }. P n/ f O5 Q; M' Y+ x937292 CAPTURE GENERAL Memory usage keeps on growing and finally gets exhausted while search
J" h; r6 a0 p) d* a937322 CONCEPT_HDL CORE Master.tag file alters the sequence of the files and Genview fails% w( O* L5 f2 F
939135 CONCEPT_HDL CORE Unable to uprev a 16.3 Design to 16.5 with DEHDL-L License% m( [: |% F( |4 s; k5 [' F
940373 CAPTURE TCL_INTERFACE Enhancement: TCL command to add nets to Netgroup
8 Q5 A+ Z9 ^8 I. ], c940547 TDA CORE ERROR(SPDWSD-69): highspeed cannot be checked in* g; O& M+ P0 l5 V
940607 SIG_EXPLORER OTHER Inconsistancy in License usage for opening sigxp -orcad
0 g# ]$ W9 B" M940790 F2B PACKAGERXL User doesn't want to display pin numbers after Export Physical 16.5.' E, u' a; u# \- ?1 E
940944 SIG_EXPLORER OTHER Inconsistant license usage while opening Orcad PCB SI using allegro -sq -orcad and allegro -sq; {: S" y7 a' e6 o, V$ u
941354 CAPTURE NETGROUPS Enhancement: Option to rename the unnamed NetGroups" e, q; ?$ q( _7 b) t4 u" y
941455 ALLEGRO_EDITOR MANUFACT The Dimensioned mechanical symbol when placed in the board does not show all the dimensions.* u0 a4 g1 r9 o, ]% E- M# Z2 C+ ]
941863 ALLEGRO_EDITOR EDIT_ETCH Different behavior of design in v16_3 & v16_5 when add connect is executed on a segment thru script
; W% a# g( K) q0 l8 A: O. E941881 CONCEPT_HDL COMP_BROWSER How can I suppress the dialog from universalbrowser -genlibindex?
. K* i# I- j1 Z: {942474 CAPTURE NETGROUPS NetGroup member type of last added member must be remembered by Capture4 }! d9 Y! i! v& @. c
942522 CAPTURE GEN_BOM Export in excel check mark doesn't invoked BOM in Excel" J y x% V- h- Z- j0 g0 k
942557 PCB_LIBRARIAN EXPORT_OTHER PDV Export to Capture crash& A6 |% ~( i1 q; G
942569 ALLEGRO_EDITOR MANUFACT Dimension move and change text deletes leaderless balloon$ B9 T k, \. I" |1 `
942573 ALLEGRO_EDITOR MANUFACT Balloon type parameter has no effect on leaderless balloon.
2 m4 X2 Z* e; W# [1 h' l942613 CONCEPT_HDL CORE Genview supports only SCHEMATIC/SYMBOL/VERILOG/VHDL views as input type. .xcon not recongnised# t4 E K( e7 ~8 I2 Y6 V' I0 D
943032 SCM OTHER ASA is not passing the correct reuse_module name to Allegro PCB layout.8 A1 d8 s+ Q) P: p9 e% S* b' x
943401 CAPTURE NETGROUPS Alphabetical ordering of NetGroups in Place NetGroup
2 W( c2 a( X1 ~* Z% q! b" f944006 ALLEGRO_EDITOR EDIT_ETCH Vias added to shapes behave differently
" {8 p0 V& X. n" m9 e% a/ w944367 CONCEPT_HDL OTHER Too late to do Model Assingment in conceptHDL 16.5
}9 B: O0 |7 z( |944788 ALLEGRO_EDITOR GRAPHICS Oblong Pad shows unexpected lines9 [% Y" e! o, N) l, Y
945221 CONSTRAINT_MGR RETAIN_CNS CM Conflict Resolution fails on more complex designs using ECSets and constraints
. h& |0 q X& x6 L# v946270 ALLEGRO_EDITOR PLACEMENT The Rotation Type was changed to "Absoute" if the "iangle 90" use at placementedit mode of spb16.5
# v' m% V/ d- a u+ F946350 F2B DESIGNVARI Variant Editor rename function removes all components
: G* M* a9 F8 b/ G/ r1 e& m0 v2 Z946380 F2B DESIGNVARI Some VARIANTX properties are hard some soft - why?# }8 v, i2 I7 u$ k$ Z8 H7 U/ q5 H
946419 SIG_INTEGRITY SIMULATION Cannot select component on BoardModel for controller in bus setup form0 o, q/ v( _$ B. S5 m6 h: s/ X' J
946458 SCM SCHGEN Schematic generator adding an unnecessary page
1 f$ F# O, c; U0 R# P947667 ALLEGRO_EDITOR PADS_IN Need support for PADS-POWERPCB-V9.3-BASIC
f. b7 E5 O& n2 o$ l; `0 c947789 ALLEGRO_EDITOR MENTOR mbs2brd crashes during translation on the attached design.3 \; ?3 z( s7 I( g w s
948110 CONCEPT_HDL CONSTRAINT_MGR Concept HDL craches when opening SigXP from CM
9 w M6 J' A! G* h D: Q950970 ALLEGRO_EDITOR MANUFACT Unable to generate artwork, dbdoctor fails to fix errors.2 C, b8 m5 e' z' c
951901 ALLEGRO_EDITOR EDIT_ETCH In 16.5 add connect to same net is shoved6 \) @% _7 W* J3 r9 o" c- g1 d! F
951919 ALLEGRO_EDITOR OTHER Exported package symbol soldermask and pastemask padstack locations not the same as original
! z' d B+ W2 Z/ d+ x951926 CONSTRAINT_MGR OTHER What is MaestroNotifyNotSetReport.txt file?6 u; P- Y, M5 K# H3 S5 Z! J
951939 F2B PACKAGERXL Uprev to 16.5 is changing refdes for some pages$ A' i6 a5 c8 o0 r& n7 m5 Q0 a" s. J
951983 CONCEPT_HDL INFRA Problems converting an Allegro design from 16.3 to 16.5
; I/ [& w) X$ R+ _952057 SCM PACKAGER Export Physical does not works correctly from SCM3 @+ K7 O% j5 B. K3 I
952217 ALLEGRO_EDITOR GRAPHICS crash when opening 3d viewer in PCB Editor
5 ^- u3 ]% n; Q4 L9 S! H5 K952634 CONCEPT_HDL CHECKPLUS Checkplus logical rule fails on a design which packages fine in 16.5
# u% u: Y- i( k) R O! |, S; j7 {953018 APD REPORTS Shape affects Package Report result.
0 I+ \; ^" _7 k* z953337 ALLEGRO_EDITOR OTHER Allow netname and padstack names to be visible for testpoint vias when viewed in Allegro PDF Publisher.
& m9 r6 { t4 B; |* E. o953827 ALLEGRO_EDITOR EDIT_ETCH Snake Breakout function crashed Allegro
5 H* X( |4 c B3 |2 m953918 GRE CORE GRE cannot route second and third row of pad in die symbol., Q& k6 u+ ^- \# ^% c9 @
954055 CONCEPT_HDL CREFER Crefer fails with UNC install path
1 q- I2 p+ K% C$ R9 A/ p954920 SIG_INTEGRITY CIRCUIT_BUILDER Each neighbor crosstalk simulation crashes or returns blank report: Z6 c2 S, u2 ]
3 E, P) I0 O3 w0 p" X
DATE: 11-7-2011 HOTFIX VERSION: 0101 N, \0 C/ b/ e/ w! J
===================================================================================================================================
+ I5 H9 W" H# @+ Z& b7 k4 pCCRID PRODUCT PRODUCTLEVEL2 TITLE
, q& b7 d: g# f" I; B- V. K3 v===================================================================================================================================) @4 P+ y/ V1 O' p- d3 f
658866 ALLEGRO_EDITOR EDIT_ETCH enhancement option - so that Sliding a via inside a pad does not create a cline7 T8 ?$ M6 L# l+ P& r! d# R7 q
928624 ALLEGRO_EDITOR GRAPHICS Layer visibility control for 3D Viewer
# y3 a( D- W/ z! X934991 SPECCTRA LICENSING Specctra_adv option is not working correctly for PA3100 plus PS3500 license in v16.5 tiering profile. v- o: y2 U" U# ?& U
938073 ALLEGRO_EDITOR PLOTTING Plot Page size A0 and A1 with problem
1 Q, U7 W, g$ p' K' p e938128 ALLEGRO_EDITOR DRC_CONSTR DRC changes when do update DRC.
. N) F, i* I6 L6 r: ]! Q: |! ^9 p+ t$ u938648 ALLEGRO_EDITOR GRAPHICS Enh - Requesting a way such that Package keepout appears transparent in 3D Viewer1 W, q# z/ T8 U
940518 SIP_LAYOUT SYMB_EDIT_APPMOD Swap pins command doesn't complete4 N; ?4 A" `* q) H9 g0 F
941426 CONCEPT_HDL COPY_PROJECT Copy Project fails - Updating opf view This can't happen!
0 B( K$ M! F+ `0 x# Y6 Y941499 ALLEGRO_EDITOR DRAFTING BUG imit Tolerance isnot working for Dimensioning0 S. P- R' q) S0 f2 q
941814 CONCEPT_HDL CREFER CreferHDL crashes during ScheGen! G! }& f8 @* }" {6 {
942914 SIG_INTEGRITY OTHER ZAxis delay calculation( T) U7 @9 A7 o5 N) N2 k7 L
943053 ALLEGRO_EDITOR SHAPE Modifying the Board Outline shape will cause the tool to crash& c& O. \& J$ K% h
945321 SIP_LAYOUT EXPORT_DATA generation of a xml file from cdnsip for shrunken die j7 M0 A, k, B% s+ P
945350 ALLEGRO_EDITOR SHAPE iPick does not work on shape boundary edit.; h6 h# e$ W" \/ F, m( A- |
945449 APD SKILL When they create a new menu entry with skill APD crashes with next menu selection.
& @& m; X! z7 I6 a946390 ALLEGRO_EDITOR DRAFTING refresh_symbol crash when trying to refresh mech sym that has dimensions) F. l) x# g# ~ Y! V
946401 APD EXPORT_DATA stream out gdsII results in shorting of PWR/GND nets due to elongated etch
' E1 [+ `/ V5 Q% G946819 SIP_LAYOUT DEGASSING Shape degass command/ E6 e% w v3 n9 x* D# b L
946869 ALLEGRO_EDITOR OTHER Allegro PDF arc representation needs cleaned up# i8 j2 E. F, i% v1 e5 r' r# K+ p8 ~3 r
947230 ALLEGRO_EDITOR SKILL Skill execution crash Allegro 16.5 but work correctly with Allegro 16.30 Q4 V9 X! V4 X, W$ _- s4 ~
947603 ALLEGRO_EDITOR OTHER Component Properties (Default or User Defined) not transferred to PDF file
# d2 f: M+ ]7 b. B6 K950995 SIG_INTEGRITY OTHER Netrev fatal error when importing logic: X- q6 d% r8 o# i$ i0 j% f
951123 ALLEGRO_EDITOR INTERFACES IPC fails to output drill hole info in columns 33-37' H' h( _0 P3 n& a) Q F
951557 CONCEPT_HDL CORE Cannot create the entity folder for old plumbing symbol
& I* @! |5 h) ~" z5 V6 A
; Z; F& j" k. V; m( BDATE: 10-26-2011 HOTFIX VERSION: 009
% Y$ h* m* L3 H8 u===================================================================================================================================4 e' ?8 v* P: i' W
CCRID PRODUCT PRODUCTLEVEL2 TITLE
! G. a& D. I: Q===================================================================================================================================
- n$ k0 C5 ?2 }945788 CONCEPT_HDL CORE Some component properties on the parts are incorrectly changed after Import Sheet$ w* s8 d3 K$ @5 g- [
945789 ADW LRM Some component instances are not updated by LRM even though cache ptf is updated from reference1 X; S& g. T4 n2 ~% I' x
" h4 q( R. g. n2 G% {
DATE: 10-21-2011 HOTFIX VERSION: 008/ B- p8 Y r: E
===================================================================================================================================
h2 \$ G8 k& ^CCRID PRODUCT PRODUCTLEVEL2 TITLE# D0 z% F2 z- w1 c/ {$ t! F
===================================================================================================================================
- F4 n" L- @; c3 L$ U2 B i906827 ALLEGRO_EDITOR DATABASE Logic > Parts logic does not work correctly.; [' @% C1 R+ p- o: f& v
923346 CONCEPT_HDL CORE Not able to move the reference designators inside hierarchal blocks after uprev to 16.5
; F& M% o6 ?3 I+ @% ^. g926347 ADW COMPONENT_BROWSE Usability- Libflow Part check in comment should end up in Comments attribute for UCB/Designer to see it+ w, f( M7 S# t3 [5 T
929348 F2B BOM Warning 007: Invalid output file path name5 X9 E: ~+ ?4 g# Q- W3 D
929777 CONCEPT_HDL OTHER Component Revision Manager gives internal error' N4 S# b% c* D, w8 [( J/ X" V4 G
930783 CONCEPT_HDL CORE Painting with groups with default colors
/ E7 K. S( K+ K$ a7 E936748 ALLEGRO_EDITOR INTERACTIV "Unplace Component" menu inconsistent between General Edit and Placement Edit Mode.9 D. ~4 T0 b& x0 V* U/ y/ W
938143 ALLEGRO_EDITOR CREATE_SYM Why is this Extra Property 'ECSET_MAPPING_ERROR
2 y' _9 I, i6 D1 q: C& `938281 SIP_RF OTHER export_chips creating bad data when symbol is split and contains V- V+ pins6 Z: `0 O7 S2 o2 t& g6 t0 F( X
938812 ALLEGRO_EDITOR SYMBOL Cannot create a BSM with this DRA, errors out but does not state a reason.& p6 t0 Y% S4 X5 Q% D B- } Y5 B4 ~
939075 CAPTURE TCL_INTERFACE Texts are getting garbled in command window
; @( K- _4 S) |3 A939193 F2B PACKAGERXL ERROR(SPCODD-439): Connectivity server is unable to load the design.
, s) k" J# ^; N7 y9 z939199 CONCEPT_HDL DOC "Retain electrical constraint on net" mismatch between schematic (YES) and design (NO)8 O+ d* G- g) x. [
939346 ALLEGRO_EDITOR SHAPE Shape disappears when updating with variable shape_rki_autoclip set.
& V" X% C# t c5 O# _( A" j939901 CONCEPT_HDL INFRA NET_SPACING_TYPE shows �?� on lower hierarchy level nets after Upreving to 16.5 version., v$ n8 z0 |, \* o( t! P A' a
939918 PSPICE PROBE Print > Preview for output file causes Pspice crash.
$ p! n% i1 K% U) }940217 CONCEPT_HDL COMP_BROWSER UCB reports 'No Symbol found for the part'5 D/ U; f T. T. X8 o; l
940835 CONCEPT_HDL INFRA Desing package different after uprev to 16.5 where comp instance propeties are lost lost
9 q0 Y! ?! d2 v5 r4 A' D/ o941125 ALLEGRO_EDITOR DATABASE Performance advisor doesn't skip non plated slot padstacks9 n6 K6 j, Z2 ~( a: R1 l" U0 s
941876 SIG_INTEGRITY OTHER Illegal model name cause pxl fail in 16.3
+ P$ d+ [, j5 I8 Y942210 SCM OTHER Is the Project File argument is being correctly passed?7 j* c" d) l, ?: a3 ~
942274 CAPTURE PROJECT_MANAGER Crash on renaming a Design Cache part in Project Manage after doing replace cache
# ^! o0 X; ^" i ?( s942839 ALLEGRO_EDITOR GRAPHICS Graphics Issue- Pads are not visible0 K) e0 t; i* S
943055 ALLEGRO_EDITOR SKILL axlDBCreatePropDictEntry causes application to crash
8 J3 A0 u+ B$ Q4 G; V8 c# e
) e7 ?) z, x, x9 ?& f) fDATE: 10-21-2011 HOTFIX VERSION: 007
, c: Y* O5 U' O# H===================================================================================================================================& R) y- k$ t, ~ O4 z
CCRID PRODUCT PRODUCTLEVEL2 TITLE
, Q/ D5 `8 W1 ~5 [===================================================================================================================================
) Z$ i9 ` L$ r r' K2 O841096 APD WIREBOND Function required which to check wire not in die pad center.
5 g$ T: T) s. _) k) l, i& w; B903263 CAPTURE SCHEMATIC_EDITOR ENH: Selecting parent netgroup must select the underlying netgroup bits.
/ L. v' u+ d/ c2 O- v+ s. g906692 ADW LRM LRM window is always in front when opening a project
3 C: E. R! ?3 h4 `: H912942 APD WIREBOND constraint driven wire bonding
- I4 s9 y: v2 L! X4 j* y912951 CONCEPT_HDL CONSTRAINT_MGR Need to manage temporary files on Linux systems" [: y% e$ q: ~ q/ D+ W
915178 SIP_LAYOUT DIE_STACK_EDITOR Die Pad names changing when updating Die in a design
+ S4 n% \9 p* c$ P# y917887 PCB_LIBRARIAN VERIFICATION Part should not be released if the alt_symbols has errors
" c7 N! ]! A1 R, t: ~6 T923315 SIG_INTEGRITY GEOMETRY_EXTRACT crosstalk simulation fails with TMP popup failure
e+ B9 \$ A4 h7 P$ z927382 CONCEPT_HDL CHECKPLUS 'Verify Symbol' forces the use of 'Concept_HDL_Studio' license8 U6 V7 k' X- }% B0 Y, i$ C
927664 CONCEPT_HDL CONSTRAINT_MGR Internal Error disposeipsp
- x" T2 j2 R2 c5 z930152 CAPTURE NETGROUPS Scalar net names when being connected to net group overlap when connections are made one by one' _1 B% [$ U/ e% ~3 W
930180 CIS LINK_DATABASE_PA Visible property position on schematic get reset on "link database part" operation' c# A, o8 U; F( z! ^( L
930188 CAPTURE DATABASE Capture 16.5 crashes in being re-invoked.
" x# J( h6 q& O930541 CAPTURE NETGROUPS NETGROUP element renaming doesn' renames the associated net ?; y9 y- Z" s) S1 V! s
930866 PDN_ANALYSIS SETUP OrCAD PCB SI Session crashes when we open PDN Analysis with "OrCAD PCB SI" license.
$ g4 e0 S9 r3 o& y# d+ m5 w930926 ALLEGRO_EDITOR GRAPHICS Via and Holes not visible eventhough set to Visible in Color form/ S4 D2 e1 q# B, t: t
931274 ALLEGRO_EDITOR DRC_CONSTR Negative Plane Islands waived DRCs reappear after performing update DRC.
/ B; `$ ?$ Q1 `% _932091 CONCEPT_HDL CORE Prop attached to SIG_NAME property K2 w% K8 z `9 h" Q7 w* i9 k7 K
932255 ALLEGRO_EDITOR GRAPHICS Change in Zoom level makes arc segment to disappear
& s2 p7 @' v$ B4 @* y932292 ADW LRM LRM crashes during Update operation on a customer design
) O0 _ d9 a% ?1 f% ]2 h932639 SIG_INTEGRITY OTHER Add Connect command hangs for about 14 seconds and then returns., A& f/ \9 C+ @5 P3 g1 F% }
932704 APD DEGASSING Shape > Degass never finishes on large GND plane- L) |$ W1 A# j. o! k" ?
932871 APD GRAPHICS could not see cursor as infinite
8 C, ?* ~" J0 s/ Q* A932882 CAPTURE SCHEMATIC_EDITOR Capture crash with FIND command - ISR05& N5 R6 X- M9 G$ u% _
932969 CONCEPT_HDL CORE ConceptHDL crashes when you save the design in 165 > hotfix #05
7 F: v% F2 ^/ x( u, l933024 CAPTURE NETGROUPS Naming restrictions for NetGroup members
# {# Q( P5 _) K933145 F2B PACKAGERXL Add Subdesign list is truncated in Force SubDesign Design Name pulldown
/ k G' G8 O$ @% @/ C% W933214 APD ARTWORK Film area report is larger when fillets are removed
* {2 `7 k. x( O7 A, i: Y: e" D933356 CONCEPT_HDL CORE Net prop display size become 0 if it was attached to SIG_NAME prop.
1 @% S+ t0 S9 n8 g933532 ALLEGRO_EDITOR COLOR Bad color assign and initialisation during creation of new subclass
7 @: _8 ^2 @1 }" V) }2 X6 g. u$ j2 ~933549 ALLEGRO_EDITOR OTHER Chart text missing in export PDF file./ |7 D* ]1 R/ M. O
934008 ALLEGRO_EDITOR REFRESH refresh symbol updates symbol text to some unexpected values, o/ Q- Z: L: D* ]2 k7 Y, \
934031 ALLEGRO_EDITOR DRC_CONSTR Bug : Update DRC removes Waived status for some DRCs8 l2 N; Y# a8 Z0 r5 N: \
934087 CONCEPT_HDL CORE Opening DEHDL and Model Assignment before design loads causes crash3 S- f6 N3 [6 P/ L
934396 CAPTURE SCHEMATIC_EDITOR Find operation is not searching power symbols with + or - signs.
3 K! _: |+ J [: J+ L+ n3 L2 V934533 F2B DESIGNVARI The Variant Editor errors are not written to the variants.lst file
! H, I6 B( R7 C3 n- J934811 SIP_LAYOUT UI_FORMS CDNSIP should not hang if contraction value in z-copy command is out-of-bound
- ~5 m1 r3 v! { _/ B$ J% f934909 SCM UI Require support for running script on loading a design in SCM
; Q! s/ `8 U- g( G935632 CAPTURE SCHEMATIC_EDITOR SHIFT+Mouse wheel scroll(horizontal) of page is not working in Auto Wire Mode. o) E$ S4 x# K' u4 z2 s1 H2 G
935794 ALLEGRO_EDITOR SHAPE BUG:Shape not filled in 16.5 but it does in 16.36 u8 d, i' }: U2 x9 a
935988 ALLEGRO_EDITOR INTERFACES When attempting to downrev this 16.5 design to 16.3 the tool will crash
- b0 t: w1 H" m" R) D& a- d936056 ALLEGRO_EDITOR DRC_CONSTR place_manual crash while moving mirrrored symbol
% w3 q0 W% i# f+ l936098 ALLEGRO_EDITOR SKILL axlDBCreateCloseShape does not work correctly.
. m: @ Q( f6 Z% e1 b6 ?936212 ALLEGRO_EDITOR INTERFACES DXF not created if Blocks created for Symbol and padstack
h3 x+ v7 _5 }$ }( X936797 CONCEPT_HDL COPY_PROJECT Copy Project crash
. [0 M7 M9 H" D936808 ALLEGRO_EDITOR DATABASE Allegro crash replace mechanical symbol; m5 W' y" ]: \2 S6 e8 x
936853 CONCEPT_HDL CONSTRAINT_MGR DEHDL crashes when trying to extract net from CM9 K$ j" m1 Q0 S/ v) n3 C
937087 CIS DESIGN_VARIANT Upreved design becomes very slow in Variant view mode. DELEET THE DESIGN AFTER RESOLVING THE ISSUE3 u6 Z4 \2 p8 ^: A
937173 CAPTURE OTHER Wrong license information "UNLICENSED" in Capture >> Help >> About
2 C( z! S5 O8 f% @937290 APD PLATING_BAR Plating Bar checks does not recognize connection made through etchback through shape.
5 W$ d$ d" x( r- a" F. {937411 ALLEGRO_EDITOR DATABASE downrev_library reading from one directory and writing to another hangs the command.2 y0 ?! V5 I& c6 k3 c% a5 e# N6 ?
938235 SIP_LAYOUT STREAM_IF Die Orientation is not correct after importing a stream file.: O+ B1 s# H: ]0 F
938273 ALLEGRO_EDITOR OTHER PDF export is is not opening viewer with ads_sdlog variable set7 i& N H& e$ r* Q$ F; T
4 Z* T) s! a7 x2 i" ?
DATE: 09-16-2011 HOTFIX VERSION: 006
7 s% A: u- E4 X5 t9 q w6 G- |===================================================================================================================================
, e' r$ O. S! ?6 I! J% Q8 F0 [6 z3 aCCRID PRODUCT PRODUCTLEVEL2 TITLE% [/ Z9 C2 t Y( V& K7 T7 W
===================================================================================================================================
; r! y- q' y- b6 B; r- S) L) T$ T# L' U820131 CONCEPT_HDL OTHER Moving symbols to other page will make Allegro components unplaced because logical_path changed.
7 g6 W( R) @# F9 P/ ?; V863860 CONSTRAINT_MGR SCHEM_FTB CM should display or Local Interface and Global nets to help defining low level constraints* H; j+ O' J/ q, f# s* l# J! {
919822 TDA CORE Cannot configure LDAP to only list the login name7 v* K: ^( W: d) A1 v$ E6 n
922907 ADW TDA 搇ast_callout_file� directive in the BOM section is empty causes tda for show Access Denied error
3 q3 }& V4 f& O! T. |( N924322 ADW COMPONENT_BROWSE Random - No instance properties are added on Add To Design (RMB or double click) from Search Results u0 L w% A% h! ]7 H7 E l$ i
924448 F2B DESIGNVARI Design does not complete variant annotation
/ I, b4 I. F5 Q( [925584 CONSTRAINT_MGR SCHEM_FTB 16.3 upreved Design passes the SLOT/Function Properties to PCB
" F7 f- w. }1 t: t" A* G8 d7 Z927102 ALLEGRO_EDITOR OTHER Question of Conductor Detailed Length Report% A6 g* @3 q4 v' Y
927104 F2B DESIGNVARI Tools > Annotate variants crashes when there are ASCII characters in the property values! ^! S7 {* u$ H, _
927142 F2B DESIGNVARI Incorrect pop up asking while executing variant editor from the command line
2 \" u9 ]* a* Y' R: r" T927166 CAPTURE NETLIST_ALLEGRO ENH: Feature like NET_SHORT in Capture Allegro flow which allows user to short 2 or more power nets
. W' J! s" ?! t4 I927410 ALLEGRO_EDITOR DATABASE ERROR(SPMHUT-144): Illegal arc specification error when Run DBDoctor
% f: x0 v, Q' X. U# O% b. s927475 CONCEPT_HDL CORE About forcereset command of nconcepthdl
6 f0 ^8 A; q2 z& l927498 CONCEPT_HDL CORE Pin_Name starting with minus causes incorrect behavior for $PN display
# @/ v$ p$ v" A+ o6 a( X5 A+ c927608 ALLEGRO_EDITOR PADS_IN Import PADs fails with error message: Failed to close the Allegro database/ X" l: N- s# @7 ]/ o
927637 SCM CONSTRAINT_MGR ASA crashes on change root and also performance is too slow.( z& k# [; b9 N, ^/ M3 m( g% C
928429 SIG_INTEGRITY OTHER Request - Package Wizard to work in PCB SI.+ z( L* |$ {' x- m
928483 ALLEGRO_EDITOR DRC_CONSTR Running Update DRC removes Via List DRC Error when via is actually not in the list5 s" f0 B+ i T9 u
928738 PSPICE PROBE Y-axis grid settings for multiple plots" m3 e+ L% z+ r! m: D( `0 T
928748 PSPICE PROBE Cursor width settings not saved7 ]! Q4 q9 L% v! _. a+ `( c! [
928779 CONCEPT_HDL CORE Error (1053) occurs on a copied part in SPB165 release! L8 K, j6 X& c( r1 Z/ p
928838 CONCEPT_HDL CONSTRAINT_MGR ECSets not migrated in 16.5
& V+ O/ l2 D3 G% ^6 q7 F) {( B928885 SIG_EXPLORER EXTRACTTOP PCB SI crashes when extracting a net from Probe; S; b% p7 z0 \( N9 u, v. ^
929284 CONCEPT_HDL ARCHIVER archive does not create a zip file( S# a; o9 Y$ j$ v0 Q. j
929542 SIP_LAYOUT DIE_ABSTRACT_IF net issue of multiple ports of co-design die in SiP) k) u+ }0 F9 g3 p
929656 ALLEGRO_EDITOR PADS_IN PADS translation fails with Microsoft Visual C++ Runtime Library error/ T( }! C/ q! N$ n- M. K0 U" H
930063 ALLEGRO_EDITOR TESTPREP Test prep crash Allego when it can not create pin escape3 j5 A+ p+ Y& V7 D0 o
930217 CAPTURE NETGROUPS Net aliases doen't gets assigend to bus bits if bus name is checked in NETGROUP.
T/ \& w( p. r930355 SIP_LAYOUT WIREBOND about "wirebond add nonstandard" command
+ a" {; k8 t; Q# i$ ~930607 APD OTHER Layer mapping information is reomved from Layer conversion file upon exporting DXF from board file.3 ?+ E1 k) z, f8 m5 ?
930646 ALLEGRO_EDITOR DRAFTING Bug - Adding Linear Dimenstion for ISO standard add the Angle information as well- Z( C4 M, M# f5 s5 I/ Y
930894 CAPTURE TCL_INTERFACE PDF export doesn't creates property file if some symbols are used in page name/folder name
8 P; W( M) u/ w7 n) p930944 ALLEGRO_EDITOR OTHER Setting variable 'appmode' equal to 'none' is not changing the Application Mode when reinvoked7 N# f* P5 j& H! |3 p- h
930978 ALLEGRO_EDITOR SCHEM_FTB 3rd party netin error - Pin is connected to net <netname> not reconnected no longer happens
* U( e/ M1 k- Y; R" [( b* R931248 ALLEGRO_EDITOR DRC_CONSTR Match Group was removed if member nets became xnets.
6 N. ?/ `5 u# Q931278 CONCEPT_HDL INFRA $PN gets copied when upreving design from 16.2 to 16.5 version: [9 z I$ c: w0 a
931349 CONCEPT_HDL COMP_BROWSER DEHDL craches and corrupts connectivity file when using Modify command extensivly.' E6 B, v. i( E5 L4 [! J
0 \5 q$ V0 _6 I9 M. }1 g
DATE: 08-31-2011 HOTFIX VERSION: 005
$ ?" [% @) f; Y7 h! \6 g===================================================================================================================================7 H: \! _" Q9 [! ^" |; v) F
CCRID PRODUCT PRODUCTLEVEL2 TITLE
: G1 l$ i8 h0 b, |* m8 `9 e. ]& R===================================================================================================================================
3 b8 r- E) k: V% R, u& x825848 ALLEGRO_EDITOR SHAPE Shape not filled when edges from 2 RKO shapes touch around mouting hole% g$ h) R) W. C4 B0 y7 B+ S% H% E
837723 CAPTURE PROPERTY_EDITOR Occurrences of external design not related to current root should not show
* g( M3 c' O* k7 L8 G891079 CONCEPT_HDL CORE DEHDL crashes with large number of commands in Winodws mode
: X: M5 l0 R4 d/ q. P910908 SIG_EXPLORER OTHER Cannot open top if Tx AMI dll name contain more than 2 dot.
4 ^0 T5 e( W* @8 S5 ?914036 CAPTURE LIBRARY ENH: Option to delete a corrupted part from a library and leaving other parts intact in the library.
7 u7 m8 w9 \# b! d( Y: J: a" Z0 Q914679 ALLEGRO_EDITOR INTERACTIV Custom toolbars are not retained when switching between brd to dra and back to brd file using the File > Recent Designs8 O: @4 e6 }3 \: j
914870 MODEL_INTEGRIT OTHER mergedml fails to merger 2 DML files from the model integrity
, r+ |9 B6 P S0 k915645 ALLEGRO_EDITOR MANUFACT Allow the user to place the cross-section chart at a desired location" i: i6 h& B7 C
915653 ALLEGRO_EDITOR INTERACTIV unable to delete non-etch shape
$ b, f7 e u2 _8 C, O915711 ALLEGRO_EDITOR MANUFACT dimensioning tolerancing by limit not working
# T4 ]" d% u; ?' g6 K916321 CAPTURE GEN_BOM letter limitation in include file9 s( v1 ^* |9 ^, ~- J8 E2 B& N
916907 CAPTURE SCHEMATICS 揂uto Connect to Bus� should place the wire through non-connectivity objects
7 F% e& n5 M) _920327 CONSTRAINT_MGR ANALYSIS The TotalEtchLength predicate in Constraint Manager does not work for a netclass with a bus.$ M# i7 O- E; y% f# r
920753 ALLEGRO_EDITOR GRAPHICS If I confirm to padshape with zoom-in after install the s002 It was changed to wrong shape.% I0 P3 R! _$ b) ?3 D$ [8 v
921097 ALLEGRO_EDITOR GRAPHICS Padstack seen partail filled when Zoomed in even "static_shapes_fill_solid" is set
4 l9 G. U, k8 W* W921226 ALLEGRO_EDITOR DRAFTING Unable to select Package Geometry class when dimensioning in the symbol editor.2 C; X& y" \1 s2 g! {
921623 ALLEGRO_EDITOR GRAPHICS Bug : Symbol not visible when zoomed in 16.5 S002
; m! S0 C! |, H: {/ b6 A" P7 a921891 ALLEGRO_EDITOR DRAFTING dimensions are lost after downrev(ing) a SPB 16.5 design with associative dimensions4 Y7 A0 {/ m% Q. P3 g6 j# x
921937 ALLEGRO_EDITOR COLOR Padstacks with shape symbol are not showing correctly
! T. S" y- e1 T- S2 u922066 CONSTRAINT_MGR ANALYSIS Custom measurement Actual not being cleared when layout changes.
0 c0 C0 \3 ~4 M( x/ E922117 PSPICE PROBE Label colors are not correct in Probe0 ~9 p& c" \5 Q2 G' b$ Q5 }
922519 ALLEGRO_EDITOR SKILL add_bviaarray command fails for some clines but not all
1 B: M" P9 c9 w% w923224 ALLEGRO_EDITOR GRAPHICS Thermal flash Display problem in Allegro v16.5 Hotfix S002/ F/ E; _1 t0 w% x
923286 CAPTURE DRC DRC markers not reported for undefined RefDes
: q4 N5 o6 v0 Z923362 ALLEGRO_EDITOR PLOTTING Print to Postscript file not correct in 16.5* E( s# Q5 y1 r- g3 f8 X: E
923416 ALLEGRO_EDITOR PAD_EDITOR Pad Designer crash on clicking on the Arrow before Soldermask_top0 r8 b# y; o* |- D6 ?7 W) V
923507 CONCEPT_HDL CONCEPT-PCBDW The function of Import Design in the SPB16.5 Design Entry HDL (for data of ADW15.5_S23 + SPB16.3)) @' h, @* k9 k: q4 |& S+ T% Q
923910 CIS PART_MANAGER Copy & Paste operation from Part Manager copies properties only to first section of the part.% F x) k* T! ?* G% [1 W ~, y
923913 CAPTURE PROJECT_MANAGER Capture runs slow on attached design
. T& c5 k. `) j9 q0 g923937 CONCEPT_HDL CORE Back annotation time significantly increased with the metadata generation on. f+ J( o5 q7 u; |
923949 ALLEGRO_EDITOR INTERFACES Incremental DXF_IN gives 'Invalid subclass' error
, D6 @/ r( I" W924458 SCM OTHER Project > Export > Schematics crashes
% F( b: L, N. t+ F* X% {- d! a924621 ALLEGRO_EDITOR SHAPE Dynamic shapes are disappearing upon updating them to smooth.
2 _, P' W+ b: f5 a7 S8 w1 P; c925193 SIG_INTEGRITY FIELD_SOLVERS Diffential Impedance (DiffZ0) values computed in the layer stack-up is incorrect
4 E! |. i$ B# Y9 Z% C" G925195 ALLEGRO_EDITOR DRC_CONSTR Incorrect pin to shape DRC error
2 k0 z" l6 K# ^925338 CONCEPT_HDL CORE This application has requested the Runtime to terminate it in an unusual way
) y) ]2 E/ ], b925435 CAPTURE TCL_INTERFACE Capture crashes if 揝ave design as UPPERCASE� option is disabled.4 O9 l" W# c9 Y
925530 SIG_INTEGRITY OTHER Why the single line impedance value for Top and Bottom layers are different for this design?
7 U+ R$ ?( ~3 O' Y$ i& l: `/ P925864 ALLEGRO_EDITOR DRAFTING Ability to add dimensioning to different CLASS/SUBCLASS2 P# Y7 b6 n+ r) ? h9 N% r2 R* B
925976 ALLEGRO_EDITOR MENTOR mbs2brd fails to import data
' U$ J3 q6 f8 q0 T$ d; v926409 SIP_LAYOUT DRAFTING Exporting a 16.5 design to 16.3 will cause the leader/dimesion lines to be removed.# z9 a# e: w3 }6 I, M* {
926443 CONCEPT_HDL CONSTRAINT_MGR In new 16.3 "035" ISR Concept2cm will crash with error. w# Q( y# T) D
926503 CAPTURE GENERAL Memory leak Capture/Pspice: B4 ~$ h$ `5 c
926553 CONCEPT_HDL CONSTRAINT_MGR CMGR ERROR There is no net in the Cset that has pins matching those in net 1 in the Xnet
1 y9 Y4 S# ?0 ^. M7 R% m" ]926691 ALLEGRO_EDITOR OTHER Crash while Importing Technology File in CM, with Overwrite Constraints.
! w4 e; G/ g0 s- q h8 ^3 H926887 CONSTRAINT_MGR CONCEPT_HDL Pin pairs lost after Export Physical- E8 T y& O s1 P& h
927159 CONCEPT_HDL CONSTRAINT_MGR Export Physical fails due to errors in ConCM.log when SIGNAL_MODEL injected property is ''# J$ M0 M' b) x
* d/ O# t: Q# e6 R3 s |6 W( X) k
DATE: 08-19-2011 HOTFIX VERSION: 004' l' E9 c& l! h! s3 }2 F
===================================================================================================================================
5 W7 D% C% I: b4 MCCRID PRODUCT PRODUCTLEVEL2 TITLE/ ^3 n' L, m7 R5 u
===================================================================================================================================- i) s" b6 @) T0 O
785417 CONCEPT_HDL COPY_PROJECT copyprojectui crashes with a Windows runtime error
( k* I! K7 L' P3 V2 X4 p851044 CAPTURE GEN_BOM "Export BOM report to Excel" does not appear in the Standard Bill of Material Window.. @! k) C* U4 O! \+ Z7 _4 R
868216 PSPICE MODELEDITOR Encryption of subckt names, internal nodes, comments
$ y' G' H+ t& s870247 PSPICE SIMULATOR Encrypt a model and simulate it, info about inside nodes being dumped in the probe file- T" u7 N3 B- k% ?5 f
877091 CAPTURE SCHEMATICS Save JPEG, GIF, PNG and other image formats in the database in its compressed form- c2 r4 | ^% _8 p1 a: V1 Q! T6 Q
894059 CAPTURE OTHER Enhancement: Adding column in edit>browse>parts window
. y7 Z4 k6 L, ^: Q8 T+ q! m895902 RF_PCB OTHER Alphanumerical allegro pin numbers are unusable in ADS 2009 Update 1
3 l3 r: t4 ~7 b" b R1 Y895919 RF_PCB OTHER Round trip Allegro to ADS to Allegro requirement
/ f* q3 r0 a3 b2 Z! E% g6 Y6 ~903102 ALLEGRO_EDITOR OTHER Zcopy shape command for cline seems not to work correctly.3 G9 u3 K a( H" ~3 d& K
905562 SIG_INTEGRITY SIGWAVE Noise margin seems not to be measured correctly with Eye Measure function.
& c3 m/ j" y; Z9 ]7 o$ r" ]909469 SCM TABLE ASA crashes when opening project' t$ i& e0 B2 B. _2 J9 I3 f, I2 O
909595 APD LOGIC Inconsistency between export die text out and show element after pin swap
4 `4 u, \0 X. U! a4 N8 B911123 CONCEPT_HDL CORE 16.2 Design uprev to 16.5 fails with ERROR SPCOCD-152+ r8 e" t, s4 c1 U' w9 C0 e, \
911569 CAPTURE EE_INTERSHEET_RE Q: Why is capture assigning incorrect Irefs in attacehd design ?
% R$ m" j2 m) g. H$ \7 E915657 ALLEGRO_EDITOR OTHER Allegro PDF Publisher Mirror capability7 |$ Q ^5 C! K
915755 CONCEPT_HDL CONSTRAINT_MGR Cannot view net in SigXP
( w8 Q, }6 O' U916062 CAPTURE GENERAL Auto Wire Crashes Capture3 t+ E/ w0 w/ H. C" n: b' `( l
916820 F2B OTHER RF create netlist with problem d1 Y) }, d* u/ x+ ]2 Y6 m8 [
917967 ALLEGRO_EDITOR REFRESH Update symbol resets refdes location for bottom side components only.
' x1 z7 s; h, [919343 ALLEGRO_EDITOR PLACEMENT Place Manual is crashing the board file
$ B @$ |! S8 t( A919481 CONCEPT_HDL CHECKPLUS CheckPlus isGlobal function is not working5 q( d' H3 g+ d& R7 c5 m3 y
919510 CONCEPT_HDL PAGE_MGMT takes 10 min to insert page in DE HDL$ t' x2 c- U1 D# n/ L
919976 APD DATABASE Update Padstack to design crashed APD.5 k3 i9 q- Z' r: }3 J ]
920418 SIP_LAYOUT OTHER SiP enhancement to Auto Assign Pin Use to add ability to change the pin use definition
* b* S" x5 s' x! a920420 SIP_LAYOUT LOGIC SiP enhancement to Logic Auto Assign Net to display a dialouge Auto Pin Use assignment should be run0 I! o: N. _ `; o; V
920712 ALLEGRO_EDITOR ARTWORK Program has encountered a problem ... error when creating artwork
3 B# G5 |- p7 {, k' d( E; z920763 ALLEGRO_EDITOR ARTWORK Soldermask gerber missing thru-hole pins
* m" l. ]3 b' y3 z, h( `; w8 d0 g1 m920976 ALLEGRO_EDITOR GRAPHICS Question regarding the difference in the behavior of 3D Viewer w.r.t. height_min
$ S6 x6 i, C" o4 Q+ r6 J( `5 F920993 ALLEGRO_EDITOR DRC_CONSTR Minimum Metal Spacing Error is detected on Same Net. e6 k* D- H# O! c" o$ [
921727 ALLEGRO_EDITOR DRC_CONSTR Pad Boundary causing P/P drc to adjacent symbol.
6 l8 m5 }4 p* @4 t922579 CONCEPT_HDL CORE Xcon file gets corrupted upon Save of Hierarchical design with Global nets tied to interface nets
- e* k7 i! C8 m, A$ H922592 CONCEPT_HDL CORE DE-HDL does not report illegal connection when Global Net tied to interface net using an Port symbol and named
6 K/ N- `3 S! [3 l6 b2 e1 @6 T922758 ALLEGRO_EDITOR DATABASE Allegro crashes while placing second mechanical symbol with route keepin7 D+ R- p% a: i8 i& b$ V1 P
922839 ALLEGRO_EDITOR DFA The DFA drc display is unstable.
0 Y" z1 [4 r0 f# R6 o923293 ALLEGRO_EDITOR INTERFACES File> Export> IDX is failing for this design while creating an empty error log." w3 G# M. T" Z6 p
924772 ADW PCBCACHE Import Sheet is not bringing in Parts used in the source pages into target cache ptf, P6 x1 m- T$ L) F6 c2 ^" ]
a8 R/ S! x: }1 }/ d8 W3 tDATE: 08-4-2011 HOTFIX VERSION: 003
8 f% I0 D0 }! l: h" i===================================================================================================================================
% u( e, [& M$ c! gCCRID PRODUCT PRODUCTLEVEL2 TITLE
' W% U3 M, x1 h( \) \8 q+ ~4 A===================================================================================================================================
2 g2 v* g% T- b' ~787414 CAPTURE PROPERTY_EDITOR Part value can抰 be moved on schematic if a part has been copied to a new design and not saved yet.) R0 I8 v, w. e
903898 PCB_LIBRARIAN GRAPHICAL_EDITOR PDV move symbol graphics and Undo causes corruption in graphics
- p5 c7 F+ T( S. Y4 v( J904287 ALLEGRO_EDITOR ARTWORK some cline with arc is missed, when creating artwork.! C6 r {4 e, [4 r
904418 CHANNEL_ANALYS SIMULATION channel analysis sim does not give valid result2 F2 ~7 m: |* I, U/ O$ K& R2 @
905777 SIG_INTEGRITY SIMULATION User gets popup message that halts an analysis until it is acknowledged
5 U) v5 I7 K2 W7 N906139 SIG_INTEGRITY OTHER Bus sim result were cleared at the next run even if no preference changed.
, z$ Q. d4 G- C9 j+ T908680 SIG_INTEGRITY OTHER Extra prop delay due to resistance) y6 A% Q3 m! o: u; X' P: W6 h
909583 ALLEGRO_EDITOR SKILL axlPolyOperation AND operation is not working correctly.- B. u7 _0 X* V% X7 K
910315 ADW LRM Import Design with ADW causes partmgr and pxl errors) `3 N. f5 Z! I4 ?5 l, V y: Q
910689 CONCEPT_HDL CONSTRAINT_MGR NO_SWAP_COMP warning after uprev to 16.5
# c& g. n2 _7 H2 A911684 CONCEPT_HDL CONSTRAINT_MGR Attribute Definitions are incompatible for attribute 'HEADER'. when attempting to place in 16.5
& _4 t3 t! ~2 E! U4 U912343 APD OTHER APD crash on trying to modify the padstack" V; P& [! e) _7 v, O9 n
912384 PCB_LIBRARIAN CORE PDV Symbol Editor often freezes when moving groups objects by arrow keys
% v) M% }( S' ~. v) q912853 APD OTHER Fillets lost when open in 16.3.4 |& I' U6 j) l# W7 T- w6 I
913586 ALLEGRO_EDITOR ARTWORK Cannot create the drill figures in this design.
' z( L( c" D; k7 V h1 a914009 ALLEGRO_EDITOR DRC_CONSTR Diff impedance worksheet showing almost zero impedance for differential pair in attached testcase.( K ]$ } ~$ i5 ?# ^3 m" |" G/ G
914110 CONCEPT_HDL OTHER DEHDL 16.5 Uprev overides property values on hierachical blocks
7 E; O0 q. d" `3 w) Y914264 F2B OTHER Cross Probing from DEHDL for global nets present inside block doesn抰 highlight in PCB Editor.% z( D6 e9 t" W6 w- B
914309 CONCEPT_HDL CORE 16.5 DEHDL crash on saving the user design/ Y. o# n1 z) j4 U k
914558 ALLEGRO_EDITOR ARTWORK Gerber6x00 output creates unpainted niche in a shape4 ?9 o# q6 A! z9 n% V9 Y+ ^; \! d
914633 ALLEGRO_EDITOR ARTWORK Artwork failing in v16.5 while the same design when downrev'd to 16.3 is working fine.* Y/ p0 |! f& F, n" H# h" w
914634 ALLEGRO_EDITOR SKILL IsThrough flag for a padstack is reset
- v3 d4 I. d/ x5 N. G, B: t914746 ALLEGRO_EDITOR DRC_CONSTR DRC Update repeats takes longer on each successive pass.: ]! U/ o1 d# }$ e, ?1 }3 y' X
914962 ALLEGRO_EDITOR SHAPE Corruption with Shape filling( n+ F( E0 M3 g" s
915583 CONCEPT_HDL CORE performance issues in 16.5 compared to 16.3& @; R" o, c9 u8 F! x) w2 [
915630 PCB_LIBRARIAN OTHER Error when running SI Model Interface Comparison using IBIS models
+ S: O3 `8 N9 r5 O% t* N! m915742 CONCEPT_HDL HDLDIRECT I get a newgenasym error and crash when trying to save the symbol
, P. }2 g" S& ^) L916154 SCM NETLISTER scm crashes when exporting physical database to allegro& l* t0 x; d5 `2 k5 ~
916448 CAPTURE NETLIST_LAYOUT Capture 16.5 Layout netlist contains errors
0 C* X3 H8 y$ R; s- L( n1 `) k916462 ALLEGRO_EDITOR DATABASE Edit>Split_plane>create hangs Allgro PCB Editor# A5 d5 K& E6 v7 z$ P- h! N
916469 ALLEGRO_EDITOR REPORTS One Unrouted pin does not show in Unconnected Pins Report) z) T; N6 @; E; x4 q! N/ i
916495 ALLEGRO_EDITOR INTERACTIV Pick selects components from invisible (Off ) layer# M! @; J' J6 ]4 C0 \
916889 CAPTURE NETGROUPS How to change unnamed net group name?
1 M- R, h' D6 _9 r, M1 {917002 ALLEGRO_EDITOR OTHER Allegro PDF Publisher creates extra circles not available on film) Y' I1 y3 Q# P2 T. M( D
917434 APD OTHER Stream out GDSII has more pads in output data.
7 o: E8 d, g$ ~917739 CONCEPT_HDL INFRA Global Net tied to port is getting split into 2 nets in 16.5, in 16.3 it is treated as a single net
& x* ^4 y. e' ^+ n5 r: w/ s- P918187 CONSTRAINT_MGR OTHER Missing acGetTotalEtchLength predicate.. l2 V9 A' i) ~4 t
918576 CAPTURE DRC Incorrect DRC is reported for visible power pins which are connected to power symbol* R; }- j- B4 R! h E" u
8 R/ P& v) e! E/ _7 ODATE: 07-24-2011 HOTFIX VERSION: 0021 ~; c1 Y7 [( j& ?0 ]5 F4 g! p6 A/ a
===================================================================================================================================: c) ~$ m4 _# o5 H8 @
CCRID PRODUCT PRODUCTLEVEL2 TITLE
! ^8 F$ v( T8 c' ^2 K. f: t===================================================================================================================================
" W [+ _$ j+ T& z& M* Q527444 ALLEGRO_EDITOR EDIT_ETCH Slide command needs to be enhanced for same net spacings
: Z1 Z) k9 H6 ~7 m' K* c% E) D ^583257 ALLEGRO_EDITOR EDIT_ETCH Add Connect and slide command needs to be enhanced for same net spacings.# f3 |) X* f2 x9 {- P2 ~
592956 ALLEGRO_EDITOR EDIT_ETCH Same net traces will not push and/or shove each other.
; z5 [8 V+ p9 x! }" `745285 ALLEGRO_EDITOR EDIT_ETCH Requesting a true "shove" in Route > Slide for Same net routing.; b+ T( y) |* ^! B, ]2 z; {
773503 CAPTURE OTHER Doing "Mirror Horizontally" creates extra un-connects or extra junction dots in Capture V16.3.. {& N9 ^5 t4 B1 G6 G
774270 F2B PACKAGERXL Require to ignore space in Pattern setting to prevent duplicated Refdes., `1 w: i- E& w2 I" U
799984 ALLEGRO_EDITOR INTERACTIV Enhance the Fix command to select just cline segs4 W. B7 H6 m# L1 V0 I. a
809008 CAPTURE SCHEMATIC_EDITOR New nodes get appeared within the design when we select the design and do "Mirror Horizontally". K' z9 c8 |6 {1 z
810058 CAPTURE SCHEMATIC_EDITOR New nodes get appeared within the design when we select the design and do "Mirror Horizontally".
) m" T3 ] F% v: [4 i% q821133 ALLEGRO_EDITOR MANUFACT Output artwork for pad data that are suppressed unconnected pads with Gerber 6x00 format
; O6 Q- z+ H2 N% V' X, S+ ^831710 CAPTURE SCHEMATIC_EDITOR Capture adds extra junctions to design by itself7 C( I) @! H# H e4 _
842410 ALLEGRO_EDITOR EDIT_ETCH Ability to slide with "Shove" for "Same Net" segments/vias.) F2 j K. d9 o, ?/ T$ r8 S
854971 ALLEGRO_EDITOR INTERACTIV Capability to add cline segment in a temp group1 a& M- L3 C; B- H3 ~. U
860772 ADW PCBCACHE Save Shopping Cart (pcbcache) is crashing component browser! |* |- c5 h4 C" B G
867842 CAPTURE PROJECT_MANAGER Capture crash with 'Open File Location"9 V3 U4 p6 n3 v" @: d$ R! B
868306 CAPTURE CONNECTIVITY mirror vertically removes junction creates extra nets* t7 J' P2 o6 p$ d A, P
882677 EMI RULE_CHECK bypass_plane_split fail if BYPASS_XXXX_EFFECT_DISTANCE
2 b/ \1 L4 B1 I+ H891439 ALLEGRO_EDITOR INTERACTIV moving cline segments
! ~, E: W5 e8 A+ B893544 ALLEGRO_EDITOR INTERFACES IPC-D-356A netlist issue with BB vias.
0 q) H" c; ?) D8 q; T893765 ALLEGRO_EDITOR PARTITION Mail command not sending out email on Linux platforms.) O( [0 | `% |
894390 SIP_LAYOUT EXPORT_DATA Generate all balls in the xml file for export to EDI's readPackage command
5 d9 g- e1 G+ z Z895933 APD DATABASE Update Symbol shifts the center of the Dynamic Fillet and creating DRCs7 v. u. |1 q& E3 W! ]! T4 g; s
896598 ALLEGRO_EDITOR PLACEMENT error message is misleading' E( @1 q4 N( r9 O$ Q0 \ j
897196 CIS LINK_DATABASE_PA Schematic Contents are not shown in CIS window while link Dbase part for parts placed from library, Y: }* Y1 v+ Y& i( g2 a" m: Z
898598 ALLEGRO_EDITOR MENTOR Negative planes from Mentor Board Station not being translated.; O$ X* c' ^# a$ U; _# B
899556 ALLEGRO_EDITOR ARTWORK Import artwork seems not to work correctly." Q6 Y- U( s3 v% \
900501 ALLEGRO_EDITOR PLACEMENT "lace Replicate Apply" is showing lot of DRC's during placement of replicated circuit in 16.5
8 G6 o$ L* o: y9 y901141 CIS EXPLORER Japanese character appear garbled in CIS explorer window.
. Q7 `% p3 ^$ C: {, n8 v901666 CAPTURE OTHER Home page of Flowcad-Switzerland and Flowcal-Poland is not preserved on captre restart on start page
0 h: j2 @; T! o$ y8 O902066 ALLEGRO_EDITOR DRC_CONSTR Shape in Region not follow the constrains
% y( n9 X- K. h) x' p. l902349 CAPTURE LIBRARY Capture crashes while closing library/ `& f! f' c: |. d
902508 F2B PACKAGERXL SPB16.5 Packager-XL consumes much more memory than 16.3$ H$ [+ G+ U3 d" s8 `
902841 CAPTURE GENERAL Capture Start page does not show- i4 e/ j( T- ?) E2 S! U
902876 F2B PACKAGERXL Packager fails on the design upreved in 16.5' n9 Y F0 Q$ E
902959 CONCEPT_HDL HDLDIRECT HDLDirect Error while saving design
" V: x3 ?! M+ e903171 PSPICE NETLISTER Why Capture is treating hierarchical power ports as floting nets in complex heirarchy designs?
5 w: k6 Z: n# ^2 D903713 ALLEGRO_EDITOR PARTITION Placement Replication do not work fine in the Design Partition
1 V" G* L* ]9 P! F f! E903799 SIP_LAYOUT DIE_EDITOR Disappear die pins after exiting co-design die editor' q4 o; Y! [, g, K
904021 ALLEGRO_EDITOR OTHER Export PDF from SPB 16.5 produces a file not text searchable$ s9 ]1 V: h/ O$ Y* A$ p
904339 CONCEPT_HDL CORE new design crashes using the attached CDS_SITE0 @# \, i# h0 ]0 R
904522 F2B PACKAGERXL Part will not package in 16.5 but packages in 16.3
' u ]# X/ A6 F7 y7 I; @0 {) \904764 APD OTHER Enhance Scale Factor of Stream Out to support 4 decimal places6 J) O' W2 B) M7 z
904771 ALLEGRO_EDITOR MANUFACT Pin Number display issue.
7 _' C7 a7 i" N4 \$ P904853 ALLEGRO_EDITOR GRAPHICS Enhancement for showing Static shape as it was seen in 16.36 d, u" Q' e9 F3 i/ }5 I8 O& I
905144 CONSTRAINT_MGR ECS_APPLY Min Line Spacing is larger than Primary or Neck Gap less(-) Tolerance but No Warning in CM
% [* W) P* L4 z! ~, W7 P4 V" J' d# P905314 F2B PACKAGERXL Import physical causes csb corruption/ y1 D( h' b4 ]/ G: ~
905337 CONCEPT_HDL CORE ConceptHDL crashes after Import Design process.
1 n0 ?5 R4 ?$ P0 O* }905533 ALLEGRO_EDITOR INTERACTIV Pin numbers for components on BOTTOM Side are moved in Preselect mode,when the BOTTOM layer is invisible
7 n' [# m, x3 B% M3 P& n905796 CONCEPT_HDL CONSTRAINT_MGR Fujitsu CM issue inaccurate concept2cm diff pair issues9 n: r0 P& d) G7 W1 c& c
905811 CAPTURE EE_INTERSHEET_RE interesheet references in the form of grid grid page number instead of page number grid3 Q, e% w, z$ B5 ]. a, w* F
906118 CONCEPT_HDL CONSTRAINT_MGR Cannot open CM if SIGNAL_MODEL value was not assigned in ptf.
0 E7 Z* H f7 S8 ^4 c6 b% ^ N4 B906153 ALLEGRO_EDITOR SCRIPTS Unable to run allegro script in batch mode on the attached board., a* _/ G' h7 B, h
906182 APD EXPORT_DATA Modify Board Level Component Output format
/ X( B+ q+ ~. f; B# A' R' B& ~906200 ALLEGRO_EDITOR DFA Enh- DFA drc invoked in Batch mode returns false constraint value in Show Element0 w+ A3 ~ i3 a/ V+ n* ]( h
906517 PSPICE PROBE PSpice new cursor window shows incorrect result.
/ p: K5 T1 {' i' r906627 ADW COMPONENT_BROWSE ppt options are not read if ucb is launched from FM. works fine if launched from dehdl.
9 H# {2 T! j7 p906647 SIG_INTEGRITY LIBRARY lib_dist creates a signoise.log in current directory (with backup files like ,1 ,2 etc.) on each run
4 ~; F1 c6 K# n R& G; G: S906673 F2B PACKAGERXL Ignore the signal model validity check during packaging) R D) e5 j# }, D, d% a: X/ D
906688 ADW LRM A copy of source design gets created in worklib of target design after 'Import Design'
/ m! t# m" t5 i( r9 D9 f' c) z906750 ALLEGRO_EDITOR PARTITION Importing design partition removes the testpoint reference designation8 g0 H0 @9 A' r3 z
906874 PSPICE NETLISTER Error less than 2 connections for unconnected hierarchical pin
, ?- O' i& _/ R* t2 P: H907095 F2B OTHER Part Manager does not show Error as Undefined when directive ptf_mismatch_exclude_inj_prop is used7 L$ G; b2 k2 D- k m: E: b
907424 ALLEGRO_EDITOR GRAPHICS Allegro add option for pre 16.5 shape display# E% E. G) ?2 W, A# X& \
907490 CAPTURE NETLIST_LAYOUT 16.5 Layout netlist is not correct. It differs form 16.3 layout netlist.) t* L! i6 t- ?! x9 ^1 O: y
907884 SIP_LAYOUT MANUFACTURING Need to add an "NC" pin text option for "Manufacturing Documentation Display Pin Text"6 y# k6 b( a( g
907885 SIG_INTEGRITY OTHER Matchgroup targets lost when importing netlist to Allegro layout in HF31
# H8 j9 A& X- `4 w! F+ B9 G) H& Q907929 CAPTURE TCL_SAMPLE TCL command to delete a property from parts in a library is not working correctly
- L* p }, W: k8 f) b907933 SIG_INTEGRITY OTHER Single line impedence not working in OrCad PCB Professional
& N3 q4 {, }; u8 T9 T5 y907963 CONCEPT_HDL CORE Design uprev issue when moving from 16.2 to 16.59 c* S1 B( p" _; G
908000 SIG_INTEGRITY OTHER Inconsistence z-axis delay reported on Tpoint when define at via location.
7 m% @: u' a: P5 m3 u$ s908057 CONCEPT_HDL CORE DE HDL crash with the cut and paste of a signal name: \# X9 K" |9 j2 x0 h
908060 CONCEPT_HDL CORE CTRL+LMB Option not working correctly in 16.3( F' C6 f9 |+ n7 ]
908210 CAPTURE CONNECTIVITY Connection is being lost while dragging a component
9 r+ ]7 `6 x1 P- x+ u2 b( U908241 CAPTURE DRC DRC error column is blank in DRC markers window in 16.5
3 ~: x% v# Y0 c% v: Y& B( K7 n908339 RF_PCB BE_IFF_IMPORT mechanical holes VIAFC are not at the right place. K5 R+ Y& B) p+ F2 u; d Q; `* ~/ j, `
908534 SIP_LAYOUT SYMB_EDIT_APPMOD issues with symbol editor and copying pin arrays6 F: q. P' E" s5 X
908535 F2B DESIGNVARI When I try to view my variant file the variant editor crashes
$ t5 G( i* u( f: F; ?: J! t908595 APD 3D_VIEWER cadence Design 3D viewer" screen pops up and is all black because the colors have all converted to b: z; H; \9 U9 y4 B% g* V, E
908849 CAPTURE ANNOTATE Getting crash while annotating the attached design
# E# o5 `! Z y908874 CONCEPT_HDL CORE Part Manager - No Part Found error when using CCR# 775788 feature# ~; F: r: k! x' I. ?
909077 CONCEPT_HDL CORE After packaging pin numbers remains invisible even when $PN7 \+ W1 P4 \; f R
909104 ALLEGRO_EDITOR SYMBOL Warning message needs to be modified. It does not save the symbol and also not tell the actual problem.
. X# ^" `4 N/ y& G/ Z0 A) M909417 ALLEGRO_EDITOR REPORTS "report -v upc" returns 'Segmentation fault' on Linux
. c6 K! v7 P( s! E& n909635 SIP_LAYOUT DIE_STACK_EDITOR Add Interposer crashes in SiP Layout
' I# ^, M; g( H909749 ALLEGRO_EDITOR MANUFACT Allegro Crash during dimensioning( n- m8 F+ }, c2 U; ~
909760 SIP_LAYOUT MANUFACTURING Create bond finger solder mask doesn't follow the mask opening as defined in the padstack
o- k, E9 E7 r- [- U+ c0 N909861 F2B PACKAGERXL NetAssembler broken within the latest 16.30.031$ f4 d0 i$ F$ h# b0 b! Z# C
910006 CONCEPT_HDL INFRA Motorola design fails to uprev from 16.3 to 16.5, xcon file is getting corrupted.% }& a0 H, K4 s6 J
910141 CAPTURE NETGROUPS Modify NetGroup definition does not update Offpage Connector. l# X0 s9 V4 p& P1 n
910340 ADW LRM Import design in schematic, only 1 page import, the entire block is getting imported./ a3 s5 @/ {# T8 d1 @/ k) I
910678 SIG_INTEGRITY OTHER The Analyze> Model Assignment> Auto setup is not creating/assigning models to discrete components in 16.5
/ E2 r6 z* @7 M910713 F2B DESIGNVARI Variant Editor crashes when you click web link under Physical Part Filter window.' U/ ~* N) L4 N
910936 F2B PACKAGERXL ConceptHDL subdesign net name is inconsistent
( z3 ?0 B) g' Z2 u4 ]5 I8 N911530 ALLEGRO_EDITOR SYMBOL Package Symbol Wizard does not create symbol with the name given3 }- \2 S- [1 S
911631 CONCEPT_HDL CORE DEHDL crashes when opening a design
3 D7 q2 b9 j, l0 y" t912001 ALLEGRO_EDITOR OTHER option_licenses entries are made in allegro.ini even when not set as default
. ]3 n- X$ h$ A912459 F2B BOM BOMHDL crashes before getting to a menu9 i& V4 U2 Q* c2 g
913359 APD MANUFACTURING Package Report shows incorrect data
- h+ ?: t% x, C+ U. G% r. `
) F+ E3 b, ^% v. H) YDATE: 06-24-2011 HOTFIX VERSION: 001! w+ Q; I5 O. a8 z- _7 N' f6 ?' ?
===================================================================================================================================9 E' c) P% \# |/ a2 I
CCRID PRODUCT PRODUCTLEVEL2 TITLE
5 e! H1 |& |4 b. I7 o W4 [1 \! s===================================================================================================================================1 v6 V; Z. w, U1 N! @% x u# T
293005 ALLEGRO_EDITOR DATABASE Allegro crash when attempting to move mech. symbol! _/ C! X5 [: E
298289 CIS EXPLORER CIS querry gives wrong results
Q7 ~% {9 V+ \' d+ ?366939 ALLEGRO_EDITOR OTHER Cannot attach refdes on silk subclass with add text
) U3 e |! o) z( E* v' X9 o432200 ALLEGRO_EDITOR MANUFACT Fillets with an arc are required for Flexi designs6 n# L; [6 ^* x) Y: L; X
443447 APD SHAPE Shapes not following the acute angle trim control setting.
6 X9 T5 w H" j2 b' W& _473308 PSPICE AA_SENS Passing variables to lower level blocks using subparam' w- a3 o7 Y# H6 U" ]
517556 PSPICE AA_SENS Advanced Analysis does not support variables being passed down the hierarchy& i+ {( f' ^. t" s" ]9 e, M
548143 ALLEGRO_EDITOR SHAPE Dynamic shpe on Etch TOP will not void properly.
( J+ V3 k# I: |8 J+ w- S+ B606959 ADW COMPONENT_BROWSE Key properties with blank values are not getting read in shooping cart) }8 k( o. ^+ Q! V; P/ c
616466 ALLEGRO_EDITOR SHAPE Solid shapes are not getting filled
4 I* X. [4 v2 m" M1 _641358 SIP_LAYOUT DIE_STACK_EDITOR Request for Via and Multi Layer Pin support for DIE stack Area (blue region)
+ k9 J6 m, a' f1 p+ w% i' J0 `644122 SIP_LAYOUT OTHER SiP Layout - xsection - ERROR Adjacent conductive layers are not allowed, but these are diestack layers not conductor3 z5 Y" e7 z5 p
645816 ALLEGRO_EDITOR SHAPE Slide a cline all removes gnd shapes on board
7 T! _1 H( ^- x4 v$ s725355 ALLEGRO_EDITOR SHAPE User can not voided Logo correctly.
6 F% R/ _' u: Z: {" s0 W& }: g0 {763569 CONCEPT_HDL CORE Display status of Hide/Show unconnected pins icon in DE HDL UI
& W/ y' x7 \) _, i$ ~770021 CAPTURE BACKANNOTATE Changing pin group property after pin swap resets pin numbers; D1 ]1 X" J- }5 Z w9 }
792126 CAPTURE PROPERTY_EDITOR Attempt to change display for occ prop resets
( I$ g4 s7 e: y* {$ j/ G! O799014 CONCEPT_HDL CONSTRAINT_MGR concept2cm errors not shown in export physical after hier_write. I/ h2 M' W* a, N2 a
803147 CIS LINK_DATABASE_PA Link DB part should not change RefDes of multi package part
. y$ A" _& N: _/ _0 t804240 PSPICE DEHDL Problem in simulation result for a multi-section split part.6 g8 Z0 b/ ~4 Z0 d, e8 B
809118 CAPTURE NETLISTS ENH to compare two schematic Capture designs4 X2 ?( X: k, |4 Y
816568 ALLEGRO_EDITOR SHAPE shape disappears when update to smooth.. State no etch
, }* k1 `% ?6 w! [830053 CAPTURE STABILITY DXF export fails if schematic folder name as /
5 s2 F6 E+ `$ k832108 ALLEGRO_EDITOR SHAPE Shape void incorrectly. m# a% N/ C8 `; e6 T: e
833542 CONCEPT_HDL CORE PDF publisher font is NOT WYSIWIG with respect to what seen in DE HDL
3 h0 d+ ^, d4 d X* s835777 CIS DERIVE_NEW_DB_PA For XLS, donot display table as worksheetName$worksheetName to avoid 8012 error" M$ A& d+ J% i r0 q
837640 CIS GEN_BOM date format of CIS BOM has broken macros of 16.2 in 16.3 version
0 G" \; k& j& \844074 APD SPECCTRA_IF Export Router fails with memory errors.
4 _! |8 Q a9 Y9 _851595 CONCEPT_HDL CORE Pin numbers overlap on the pin and increase in size4 W9 x9 B8 G% k) Z: r4 F' [
852832 CAPTURE BACKANNOTATE Why is Capture crashing with Mentor back annotation?
) E6 s+ V9 }+ u8 |2 N# N6 y855015 ALLEGRO_EDITOR OTHER The rats are NOT connecting to the ends of the clines like they should be.: N y$ A& X- E: [
859883 CAPTURE NETLISTS ENH to compare two schematic Capture designs
. M6 ]* ]" I" ~% M8 n866009 SIG_INTEGRITY OTHER Net with Pull-up/down should not be used for Diff-pair.
L$ h8 q d$ P0 S+ W- |. D866830 SCM REPORTS Multiple lines added as separator between title block and report header instead of single line" g8 u5 k4 G r5 Q
866833 SCM REPORTS Extra indentation is left in the left side of the report when the Line Numbers are set to OFF+ t# K6 i/ `4 Q& s. h3 D- W6 b
868618 SCM IMPORTS Block re-import does not update the docsch and sch view
5 }& y6 D# [. x9 Z+ V% s873402 SIP_LAYOUT LOGIC pin swap for co-design die in SiP$ `- V0 u# @6 \4 O( X) J8 T
874010 SIG_INTEGRITY OTHER PCB SI crashes when the Xnet is extracted with VARIANT_TO_IGNORE property.
9 D5 z4 u1 C9 P2 V3 D! X874400 ALLEGRO_EDITOR INTERACTIV Flip mode issue with move command
$ j7 d; v y# j4 Y+ n/ w874966 ALLEGRO_EDITOR INTERFACES Placed mechanical component do not get Ref Des or part number in IDF file% ]) c9 P7 V/ f6 u" D& _7 W, `* o
875709 ALLEGRO_EDITOR REPORTS Film area report generated incorrect data at l1% V6 x8 R4 J6 u4 D* ?2 X7 a
876275 CONCEPT_HDL CONSTRAINT_MGR Constraint Manager not retaining target net
% K# }+ @6 W! x879361 SCM UI SCM crashes when opening project
! ]6 A0 F9 C1 D( O4 c! h3 s879496 CONCEPT_HDL OTHER Customer wants to have the tabulation� key as separator in HDL BOM.
X- o( {- e$ _' T& S' W# P879514 PSPICE AA_MC Monte Carlo to handle equation as comp VALUE.
3 H( {2 \4 Q" Q% H881845 ALLEGRO_EDITOR SHAPE Delete island deletes complete shape
3 a+ n) v$ q# b+ s: V+ ]& r) ]882413 PDN_ANALYSIS PCB_PI PDN Analysis should support routed power nets
; n5 ?- g0 \# A882427 PDN_ANALYSIS PCB_PI PDN Analysis target impedance should have a variable multiplier
! E3 x. m+ v' y882567 SIG_INTEGRITY OTHER PCB SI crash if boolean type prop was specified to VARIANT env.0 R0 \4 _7 q6 V/ u
882644 ALLEGRO_EDITOR PLACEMENT PCB Place Replicate Function automatically match Enhancement# @: d8 U# ?+ A
883164 ALLEGRO_EDITOR INTERACTIV Vias marked fanout moves away from position when moving component
n9 G; @- p9 r" l/ g883224 SIG_INTEGRITY SIMULATION crash while reflection simulation from Constraint Manager+ J9 F5 ^' y) W' E4 a+ d& m9 m. ^4 `
883760 PCB_LIBRARIAN METADATA Incorrectly formatted revision.dat file in the metadata folder: N: h$ Q. f2 k9 C
885391 SIG_INTEGRITY SIMULATION RLGC data sampling algorithm and w-element interpolation.
( r6 `0 I% Y7 n885849 ALLEGRO_EDITOR MANUFACT Silkscreen Audit cannot find Solder mask for the text string
- G# C1 d4 K' e5 {! x7 G9 N885996 SIG_INTEGRITY OTHER The effect of sn_maxwidthlimit user preference is not seen in cross section impedance calculations
4 O& I$ X: Q% d; s7 r886090 ALLEGRO_EDITOR INTERACTIV Add Arc w/Radius does not snap to grid
" I+ o: z6 d' u; k8 U% u7 N887180 CAPTURE SCHEMATIC_EDITOR Signals Navigation window doesnt get updated for Buses
' A0 V9 K- P9 G3 i( [887442 APD SHAPE Copper pour of Dynamic shapes on Top layer which contains many existing signal traces fails.
, A; q! _# J4 @* b887578 SCM AUTO_UI Component Replace pops-up the DSPANE-204 Message
, q0 r {5 E: N5 b# O4 o4 T7 u887926 SIG_INTEGRITY GEOMETRY_EXTRACT Field solution failed if diff trace on bottom doesn't have reference plane.! o* Y7 E% ]' e2 V* ^ k9 @
888414 SIG_EXPLORER OTHER View Trace Parameter display the thickness of dielectric incorrectly.' I4 |# w, B/ t* X/ C
888600 CONCEPT_HDL CREFER Cross References not added to Schegen schematic! v1 y4 |$ |) t
888679 SIP_LAYOUT SHAPE Can't create the Dynamic shape on layer M1_sig without unwanted horizontal openings appearing.. r6 h6 \9 @" \ F$ a9 g6 ~; b
888804 ALLEGRO_EDITOR OTHER Fillet will become static shape after import from partition board.0 p$ D( D& s2 w9 }, e# F
888945 CONCEPT_HDL OTHER unplaced component after placing module
3 s+ @& |5 c% M1 c! ^! z( C889222 ALLEGRO_EDITOR SHAPE Allegro freezes/hangs when adding shape as Polygon with OpenGL ON.
: b, G8 O9 B L" u) E: G889365 SIG_INTEGRITY GEOMETRY_EXTRACT top/bottom trace impedances extracted to sigxp are wrong in 16.3" h' [5 w3 D7 Q
889404 ALLEGRO_EDITOR OTHER Incorrect pad size for Top conductor padstack written to column 59-62.
2 n4 ~8 x2 Z8 n; V/ J% @! U889426 CONCEPT_HDL CHECKPLUS CheckPlus does not find single node net& B& T6 ^6 N& u3 Y! f! x2 [
889636 ALLEGRO_EDITOR MANUFACT Incorrect spelling of "Visibility" in "Film Control" tab in the Artwork Control Form; G9 Z8 L# a4 x. c, {7 F& i0 x
891235 F2B PACKAGERXL Packager crashes without creating a pxl.log file
5 w/ N$ y# Y( x. D9 `& p891292 ALLEGRO_EDITOR SHAPE arc routing causes weird undesireable shape fill performance
( O6 y& g& X* ]891856 ALLEGRO_EDITOR EDIT_ETCH crash when sliding diff pairs2 g4 D+ z* v% G; A$ C
892375 ALLEGRO_EDITOR PLACEMENT Place Replicate Update disband other groups, irrespective Fixed property added or not.
, Z" _9 |9 B* W* x( i8 d% ^892455 ALLEGRO_EDITOR SYMBOL Why the overlapping pins are not reported with DRC?2 ?! D% V, d9 v+ i7 S4 [
892541 SIG_EXPLORER OTHER Export/Import layerstack through the technology file is changing the layer thickness; x0 N _3 O1 b2 n' b2 y
892766 APD WIREBOND Excuting Finger moving cannot push aside finger to move with together by shove all mode
3 e! ^6 ]- \* W8 J7 V, m892907 ALLEGRO_EDITOR DRC_CONSTR DRC not reported for etch_turn_under_pin violations
& M y6 Y4 o1 Q7 _3 b892963 ALLEGRO_EDITOR SKILL Bad shape boundary created after axlPolyOperation 'OR+ `: i- k( S2 Z Y; n& r/ Z' C
892964 SIP_LAYOUT LOGIC Request that Edit Parts List use Dashes "-".
" {; E3 G6 O5 O. t- r893295 APD WIREBOND Why move wirebond command does not shove wirebonds? This result in drcs.
! R& B- X" Q' m1 Y7 c; O9 I0 Z: k% z893706 CONSTRAINT_MGR OTHER On line DRC hangs on partitioned board
! C9 W3 D9 ~6 l3 P, H3 C' y893743 APD EDIT_ETCH Route behavior when spanning pads not as expected.
. E: u3 ~, ^' O: T4 ~3 w- d1 T893783 SIP_LAYOUT OTHER Padstack Design Editing update File menu with a Update to Design and Close instead of 2 operation
# h5 p1 L4 ~/ e! [5 D+ h894456 ALLEGRO_EDITOR REPORTS Request Net names be added to Propagation delay lines of the DRC report.
. q9 D- g+ ]5 j, ^$ M894499 SIG_INTEGRITY LIBRARY Tool crashes when moving a cline or selecting the Info icon with OpenGL on.
. l% J! V6 S. B7 q894582 APD SHAPE When making a dynamic xhatch Via shapes surrounding are abnormal.
9 S$ j, r) X1 d) R; c895542 SIP_LAYOUT WIREBOND SIP design crashing when moving bond finger using blur mode BLUR_BONDFINGER_PRESRV_CON* M8 s7 ?$ x9 Q5 A
895591 ALLEGRO_EDITOR PCAD_IN Importing PCAD file fails to get to the point where we can map layers% ^2 P" |* R4 ~4 e, I6 V
895757 APD ARTWORK Import Gerber command could not be imported Gerber data+ p. A% J' S$ [3 K) \
895964 CONCEPT_HDL CHECKPLUS The CheckPlus command getFileSubstrings is not working correctly
3 x' c% Y7 _- c; a# a896428 SCM UI Changed Ref Des value not maintained in DEHDL block when part is replaced) f, A+ G6 Q3 k$ u
896655 CAPTURE EDIF Import/Export Design of Hierarcy design with OrCAD Capture; A2 ^% l9 R7 @3 f. C. ?/ b" ~$ j
896846 CAPTURE IMPORT/EXPORT Import edif2cap and capture is crashing
' U. b' K4 ?3 c' c+ }897155 ALLEGRO_EDITOR REPORTS Copper coverage in L2 and L7 looks like the same but film area report had large gap.
0 w1 Z. [0 I' R9 t897654 CAPTURE EE_INTERSHEET_RE Capture crashes on adding intersheet refernces in abbreviated format on attached design.
7 \% J4 _0 E$ S$ `" G0 ^6 x) @. b6 W899344 RF_PCB BE_IFF_EXPORT dlibx2iff does not provide the component boundary drawing
/ F, e' K5 c* c- y899629 CONSTRAINT_MGR OTHER ECset for Total Etch Lenght is not present in OrCAD Prof
' V6 |0 g& W8 l+ j900175 CONCEPT_HDL CONSTRAINT_MGR Few Xnets are lost from Match Group after packaging and importing the netlist to board file.
# s8 I+ i4 o, t- ^2 J* L900481 CONCEPT_HDL CORE Genview creates a larger symbol without taking the no. of pin in consideration x1 i' U& @7 k; Y
900813 ALLEGRO_EDITOR DRC_CONSTR With rotated pads, pad (pin - via) soldermask spacing DRC is unreasonable.0 U! F+ j$ l+ d/ x0 B" X. z
900905 PSPICE STABILITY Simsrvr crash and RPC Server unavailable error while running simulation. N3 s5 X; `0 E. ]7 d
901783 CONCEPT_HDL CORE CDS_PART_NAME is annotated on the schematic canvas after running back annotation in 16.5 X) H1 h |% |
901909 APD EXPORT_DATA The "package_pin_delay_length.rpt" with Z-axis delay turned on seems wrong
% G9 f6 P3 _) I5 f5 P) c901987 CONCEPT_HDL OTHER SPB16.5 zoom fit does not center the page while ploting the schematic page$ L e# n8 P) [ f
902133 CIS OTHER The visible part property value are being shown very distant from part graphics on schematic
7 D6 i" B' F" y9 i9 P902166 SPECCTRA ROUTE Specctra crashes when reading in "bestsave.w" file f# R9 Q1 }- {& A
902170 ALLEGRO_EDITOR DATABASE Diffpair Issues with OrCad PCB Designer Professional, c' |! f6 b9 T+ `( O+ Y
902177 CONSTRAINT_MGR CONCEPT_HDL Option to view the layer thickness in CM worksheet through worksheet customization! L; i5 H$ C4 ~9 }
902463 ALLEGRO_EDITOR INTERACTIV APD crashes when we click ( show element ) on certain components6 l, I" e8 ~6 T6 K7 ?& N& b2 v7 O
902621 CONCEPT_HDL OTHER Design Differences (vdd) Crashes
j5 G# c4 \* \( L902909 APD WIREBOND die to die wirebond crash
2 @; J! d( O% m- k; O, y. t1 ^902933 ALLEGRO_EDITOR PADS_IN Pads_in fails while reading PADS ASCII file body4 K4 C& ^( K- D/ @* q
903284 PDN_ANALYSIS PCB_STATICIRDROP IRDrop voltage gradients are plotted outside of the PCB outline' D& q/ w8 K( i: X* W* q' x
903680 CONSTRAINT_MGR ECS_APPLY Constraint Manager not passing all hiearchical member objects to a custom measurement.4 o0 `/ W/ _1 u
904403 ALLEGRO_EDITOR DATABASE Allegro crashes when refreshing module |
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发表于 2012-2-21 14:58
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