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. s2 \$ ?3 R9 {% iDATE: 02-17-2012 HOTFIX VERSION: 016( n# u& E' v; n8 {% X8 ^
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CCRID PRODUCT PRODUCTLEVEL2 TITLE
- a0 G) o0 ?: V===================================================================================================================================: m; P w5 G3 ]- o/ f8 f; a
840105 PCB_LIBRARIAN USABILITY PTF subtype is getting changed when Save As option is used in PDV
. u/ s' {0 |! s) H- @% q873075 Pspice PROBE Decibel of FFT results are incorrect. C9 c t: [- R& P& @+ d
938744 ADW COMPONENT_BROWSE Need ability to customize shopping cart columns to include any Part property* j% B3 B3 {2 @
943003 SCM REPORTS The dsreportgen command fails with network located project4 H0 J8 x: h- w- I( v) _% t
961530 allegro_EDITOR INTERACTIV The problem of Display measure command) |1 Q1 _) \# W; ^% b) T
962157 concept_HDL CORE Where is the setting for enabling the Enable PSpice Simulator menu?3 p& u' w1 W) h/ k: a
962206 CONSTRAINT_MGR CONCEPT_HDL Import physical not passing all constraints from the board to frontend
+ [8 u# L/ u& E' A6 |& _" E968205 PSPICE DEHDL_NETLISTER Change SPLIT_INST property to PSICE_SPLIT_INST for Quad Switch type of design.0 H, m6 y- b& i3 o
968509 PCB_LIBRARIAN METADATA Incorrect pinlist.txt was generated if DIFF_PAIR_PINS_POS/NEG was set.
( T3 ], d* c: z9 _& b969450 LAYOUT TRANSLATORS orcad Layout to Allegro Translator crashes9 w: C( P+ v1 J
969997 CONSTRAINT_MGR CONCEPT_HDL ERROR(SPCOPK-1053): Cannot find a ppt part that matches the instance pro~0 K& O& J+ W. H7 ^- S2 X* R: v
971193 CONSTRAINT_MGR UI_FORMS Copy and pasting a formula causes the application to crash on windows.1 W) q5 d. S" ]" j
971601 CONSTRAINT_MGR CONCEPT_HDL ERROR(SPCOPK-1053) and WARNING(SPCODD-66) because of directory structure. @1 {9 w% k$ ^3 ?1 \
973398 CONCEPT_HDL OTHER It should be not packaged with error while working the packaging process if the design has a ERROR
7 z; F+ n2 W. L5 U973859 PSPICE ENCRYPTION Pspice crashes with encrypted model6 @( G0 {* \; O2 d7 G, \
973938 PCB_LIBRARIAN VERIFICATION pc.db is missing4 r/ }2 X, H: _+ i n
974540 CONCEPT_HDL CORE Graphics updates are real slow
! v4 j. K1 Y3 M8 s2 n, J974791 F2B DESIGNVARI Variants are not back-annotating to schematic and turning to ?8 U0 S+ ~5 M( O/ M( s- I/ T
974818 ALLEGRO_EDITOR NC Backdrilling produces 0 plunges yet no errors reported.
: C+ V! ]1 g* C6 g3 x1 t974945 ALLEGRO_EDITOR skill Why is axlPolyOperation is giving different result and not working
3 R5 I' v4 w- B/ x, t1 M. A974946 MODEL_INTEGRIT TRANSLATION ibis2signoise returns the error - Delay measurement fixture must contain V for ECL technology5 J, i- y$ F/ q! ?7 |, _0 P
975396 CONCEPT_HDL CONSTRAINT_MGR Constraints are dropped after migrating from 16.3 to 16.5, T3 i& n6 N& ]4 C6 |+ I, P9 R
975633 ALLEGRO_EDITOR GRAPHICS 'dynamic_layer_visibility' option in 3D Viewer when checked or unchecked should not change (until next change)4 x1 t+ p* x6 N
975720 ALLEGRO_EDITOR DRAFTING Datum dimension lines not adjusting to text move
2 m* z; c" l) {6 u2 F5 x( T975745 ALLEGRO_EDITOR SKILL cdsServIpc different 16.2 vs 16.5 when Allegro exits
) ^+ n; i% o1 c0 K2 S7 b c& R: r976013 CONCEPT_HDL INFRA Power pin connection of FPGA symbol is missing in netlist.2 m$ C3 e8 w6 O8 y# C' i3 r4 P) c
976058 CONCEPT_HDL COPY_PROJECT SCM Copy project does not create the con and dcf files in tbl_1 views5 @3 L& h& G/ C- K8 p# W/ W) t. M1 G
976073 CONCEPT_HDL COPY_PROJECT All the constraint data is lost in the SCM copied design0 V1 w! q7 N% v5 w/ \5 a4 T' T3 N: G
976160 CONCEPT_HDL CREFER Cref fails due to some Caeviews error in the design
. h* R H1 Y* y$ o+ F: H6 a, P' L976204 ALLEGRO_EDITOR DRC_CONSTR Application falsely reporting Mechanical Pin Antipad to Shape Spacing DRC& b3 z, \ J4 I: p
976448 F2B PACKAGERXL ERROR(SPCOPK-1069): Invalid POWER_GROUP property value) |0 W7 C5 d% w0 p& M: f* c( ?8 P
976521 ALLEGRO_EDITOR DRC_CONSTR multi-thread update DRC causes the application to crash
+ V# K1 L; k! r, C$ N2 x976838 SIG_INTEGRITY OTHER Unable to create XNET for highlighted nets on attached database even after assigning proper Signal Models.
- W: ~7 o, X9 i977517 F2B PACKAGERXL Export physical fails after update to 16.5 from 16.3
9 b* \* g- i/ a5 f2 D8 A977902 ALLEGRO_EDITOR DATABASE generate module is crashing allegro
& h% B: J" K5 f0 `# l978652 ALLEGRO_EDITOR pads_IN PADS_IN fails with ERROR: Finished with errors.
8 _/ ?! k. G, j) B, ^2 W7 \978744 APD DEGASSING Some shapes will not DeGas on this design
! Z( | n: E# @4 H) `; R979940 SIP_LAYOUT OTHER SiP Layout Leadframe autobonding with profile selection
1 S& @: T- O1 V7 d" z8 ?" K& e981699 CAPTURE HELP Start Page still shows Hotfix 14 after installing Hotfix 15, x: Y8 ]! @) |# G
s+ y @" M) K/ \! I) t
DATE: 02-03-2012 HOTFIX VERSION: 015 c7 P1 t( W. a# f/ P: A, E
===================================================================================================================================
/ f9 X A8 U8 \, i6 [CCRID PRODUCT PRODUCTLEVEL2 TITLE
( P1 Q) Z2 X$ o6 R& M===================================================================================================================================
; H4 Q. s* s: V% Y* F& H# r871567 CONSTRAINT_MGR SCHEM_FTB Ability to filter out Single Node Nets from Constraint Manager& H. l$ R* x X, K. M
921436 ALLEGRO_EDITOR MANUFACT Change in 'decimal place' for new dimension changes the already placed dimension
6 @! n' d+ C$ Z( |941433 CONCEPT_HDL COPY_PROJECT 16.5 Copy Project should warn if trying to copy a 16.3 design! J% l p5 L0 S" T) H
954375 ALLEGRO_EDITOR MANUFACT Change dimension accuracy for few instaces of associative dimensioning
/ p' @1 _" R6 Z% i3 D. Z961646 PDN_ANALYSIS EMVIEWER EMViewer Help > About shows wrong version
8 ] h. s9 y2 |964912 CONCEPT_HDL COPY_PROJECT ASA project crash after using copy project1 s" D) C. C/ S- G% O
967223 ALLEGRO_EDITOR MANUFACT Bug:Oval slots orientation in one direction only6 c1 X: n4 y) T5 O' A$ v
968865 SIP_LAYOUT DIE_ABSTRACT_IF load of die abstract fails due to differences between component and symbol
7 z2 H' x: F% T# u. K3 ]969485 ALLEGRO_EDITOR SHAPE Shape does not update correctly in 16.5
$ D* X: @8 E Q U970331 CONSTRAINT_MGR ANALYSIS Impedance worksheet shows a zero value for impedance
* g0 ~, n8 U6 b1 D970600 SIP_LAYOUT SYMB_EDIT_APPMOD Option in Die Editor to be able to "physically swap" pins* A5 c; f- H' R" H Y/ G u1 v
970910 F2B PACKAGERXL Our customer has problem with pin color after pxl 16.5.
0 h8 q! E0 w" Z/ E: A N970970 SPECCTRA FANOUT Fanout Vias is placed far away from decaps and does not change the Fanout length even when max_length is reduced./ u M+ |* }7 j' c; p+ \- `' t
970985 SIP_LAYOUT OTHER Importing a .spd2 database file using NA2 will cause the APD/SiP tool crash
: |+ B! ^2 m4 P. W# c971757 CONCEPT_HDL INFRA Crash while Saving/Packaging the Design$ Z1 {% ]! U0 }3 m$ [/ ?
971923 ALLEGRO_EDITOR MANUFACT Allow to change decimal accuracy for dimension instances
2 f/ y" @" q' K6 q/ R8 p6 d972568 CONSTRAINT_MGR UI_FORMS Tools >Excel missing from CM. z- T) R; Y: l. J' {2 n
972821 CONSTRAINT_MGR CONCEPT_HDL connectivity server warning: Unable to add property WEIGHT
, G! {: S7 k" V973185 SCM CONSTRAINT_MGR ASA2 block not seeing all instances in a package.
& |! H5 P6 K9 I* s4 y8 x1 ~4 D* x973211 ALLEGRO_EDITOR INTERFACES IDX Object Type Change not recognized2 H' h0 s1 T9 |! e6 w
973214 ALLEGRO_EDITOR INTERFACES IDX import package keepout height value change assigns incorrect value* |, O7 W) s( V: T i1 w' A
973384 CONCEPT_HDL CHECKPLUS The multiple SIG_NAME has to be occurred an ERROR at the SPB16.5./ E, {* k4 z) z7 V& H8 u. ? m
973514 SIG_INTEGRITY OTHER Mapping error when Ecset is updated to constraint manager from extracted net) @6 c: e) p& J8 R
973950 ALLEGRO_EDITOR SHAPE Update to smooth crashes application
! P6 O) z' i! V% M( h# P. M974533 SIP_LAYOUT OTHER Crashes in Edit > Die Properties and obviously has a setup problem.& B+ @& v5 U4 |, k9 }+ H, H, F( }
974809 ALLEGRO_EDITOR SKILL argument available for hiding a property with function axlDBCreatePropDictEntry is not working
5 j% @7 ]5 R$ Z; j( {$ m976179 INSTALLATION ISR Installation of ISR S014 to 16.5 on windows is breaking the documentation index5 f! i2 R) _# f/ }* ~4 \
7 |% X1 O7 {) o0 N( e$ E
DATE: 01-20-2012 HOTFIX VERSION: 014
! G. i) i/ s5 l& ?5 f===================================================================================================================================
7 A3 X U' ?" @# ]8 v* w1 u/ G7 n3 oCCRID PRODUCT PRODUCTLEVEL2 TITLE
4 K( ^9 n- P. [5 L! q# _7 i7 j===================================================================================================================================
& h( y) k7 d6 W6 E733285 PSPICE SIMULATOR Enhancement:In server-client installation use existing index file from server6 x9 t- b. `& K; p5 n
941020 SIP_LAYOUT OTHER Soldermask enhancement C4 x1 A e4 b4 O. L7 j/ j
946407 CONSTRAINT_MGR TDD When is it safe to open a 16.5 design in 16.3?
8 j" S% M+ Y. s _953067 CONCEPT_HDL OTHER Variant Editor "Error/Warning messages" form is unusable
8 @6 d7 o/ H4 ]9 ] }# L# L954818 CONCEPT_HDL COMP_BROWSER Replace button turns to Add in component browser when a component replace is done on the schematic9 m$ i' W' }' n: a2 b& F
956450 ALLEGRO_EDITOR DRC_CONSTR Analysis always shows analysis failed in uncoupled length in some diffpairs* q5 ~/ {9 n3 Z. v
958259 F2B DESIGNSYNC ds.exe crashes on a big design when accessing the design from network drive
+ ], ?& k& }# R8 q" y0 _* m" _958395 ALLEGRO_EDITOR SHAPE shape voids won't merge) S: z5 p( E. I1 z4 _+ w
959212 MODEL_INTEGRIT PARSE Attempting to use "Mark qualified" option on DML File results in dmlcheck and Modelsim wanrings." [0 i1 S2 l0 o1 u
959940 APD AUTOVOID Void all command gets result as no voids being generated.: B, p. O* ?* R
960252 PCB_LIBRARIAN CORE Splash screen in PDV prevents showing error message
' e( o" _4 @: p) w$ E4 |961634 PDN_ANALYSIS EMVIEWER Cannot launch PDN EMViewer from withing PCB SI
, j- Y" E; e% d5 w0 v @# ~961645 PDN_ANALYSIS EMVIEWER Standalone EMViewer will crash when opening any result file in the form of *.emv file.
3 l+ R. W3 k' E2 ^2 T961700 ALLEGRO_EDITOR SHAPE dbdoctor reports ERROR(SPMHUT-144): Illegal arc specification
6 w z; h# y n' }961733 ALLEGRO_EDITOR SKILL Allegro crashes. Appears to have a memory leak./ G2 E5 k, n) l: W; ]
961758 ALLEGRO_EDITOR DRC_CONSTR DFA check produces no DRC when the dfa bounds are not a rectangle.8 ^1 h4 @9 T( _! n3 B0 P/ b' r
961887 CONCEPT_HDL CONSTRAINT_MGR Match Group created from ECSet cannot be deleted in the same session of CM5 D$ S& m: J" j S. Y ^- t' q
962552 APD EDIT_ETCH BUG:APD crashing when we try to slideget information but move works fine) ]* Y2 S: ?7 k. g- X
962869 CAPTURE STABILITY Capture crashes after RMB click on rotated parallel wires
# h, f4 Z* B) ]* u# B963232 CAPTURE MACRO Macros not being played in Windows7
( ?) Y4 b Y6 C963300 ALLEGRO_EDITOR DATABASE Create > Module crashes in 16.5 but not in 16.3
% E/ w" G' V8 D5 N' x3 [963651 CONSTRAINT_MGR CONCEPT_HDL ECsets are renamed after packaging on linux4 t* x) ~$ B! d, b m9 [# M2 J4 Y% A
963663 CONSTRAINT_MGR ANALYSIS Q- Why the customized worsheet for Diff pair Impedance not analysing at all for this SIP design" L4 ~. m- E* R$ L8 W& I
963715 SIG_INTEGRITY OTHER Application only adds the bottom conductor thickness for the via z-axis length$ O1 b1 V! b, `& N
964068 ALLEGRO_EDITOR INTERACTIV Allegro crash when using move alt sym mirror alt sym...
2 g% R3 I$ u$ |& g5 l3 s964267 CIS PART_MANAGER Capture become non-responsive, working on Part Manager and creating CIS BOM, for large designs
( \5 f4 u" [1 B" y N964597 ADW LRM Issue of LRM license checkout after renewal license by 16.5 (ADW15.5_S23+SPB16.3)
?$ Q, o4 X$ G0 h* {5 s966148 APD INTERFACES Character Limit for DIE Files (*.die) Import
9 B0 t- Z; z- Z# A8 V966416 F2B PACKAGERXL Cannot package this design
2 K3 V7 |$ C& H9 l! g( Q! I/ T966421 CONCEPT_HDL CORE DEHDL Crash when applying property on components in duplicated blocks
7 U0 i/ A! [1 a5 x. U+ V5 q: }966693 CONCEPT_HDL CORE DEHDL crashes when doing model assignment if CM is open; ~& K; q' x$ m. m0 \& F
966795 ADW ROLLBACK rollback utility does not honor -product option from command line( M5 c; y/ R0 [
967089 SIG_INTEGRITY OTHER Matchgroups created by ECSet not deleted when ECset is removed from object.% p5 P- h2 t* c. T, X+ v
967222 ALLEGRO_EDITOR OTHER PDF export is leaving data off the drawing
/ x/ s. G0 y! ?8 g) l' L9 p. s967240 SIP_LAYOUT WIREBOND Change default bond fingers selected on multi-site leads during "bond to leads" program7 u* y9 b. ]7 ?" S
967297 ALLEGRO_EDITOR OTHER Dynamic Fillet&Eliminate unused stacked vias cannot be used as the Miniaturization option.2 V% c$ w' s3 D
967576 CONCEPT_HDL CREFER Occurrence location property values do not appear in flattened schematic generated by CreferHDL: J+ g; F1 ?# A6 i0 B* ?+ B
968096 ALLEGRO_EDITOR DRC_CONSTR Mechanical Pin to conductor spacing is not followed.$ [* ~2 d Y4 _. T) F
968222 SIP_LAYOUT DIE_EDITOR die pin loses IC net for a co-design die with multiple ports within IO-cell; A/ e) ?3 q6 F5 g
968358 CIS PART_MANAGER Capture crash on removing a part from subgroup in part manager
/ H1 Y5 U8 z; l e969594 CONCEPT_HDL CORE The dcf file is not updated with schematic changes
P: L+ A( l) D# ^ W3 i6 I. y, V1 ]( j
DATE: 12-16-2011 HOTFIX VERSION: 013' R% p6 M' T: n; W" G( N1 i1 c
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CCRID PRODUCT PRODUCTLEVEL2 TITLE" \/ H* b& Y, U& g% w- m
===================================================================================================================================
: ~ d. ]" e- ]1 \( {875695 SIG_EXPLORER INTERACTIV Enforce Causality check box doesn't work.. r6 D4 o! h j* _- v; S" ?* V. k
927148 CAPTURE PROJECT_MANAGER Capture crashes on creating scehmatic folder with name which already exists in design, L+ w+ W" d/ z, i4 o
938013 CAPTURE NETLIST_OTHER The netlist in RINF Format contained two identical lines for PCB FOOTPRINT$ P8 S3 ^+ m8 `0 _: V, k* u/ N% \
941409 PSPICE PROBE BUG : Search accuracy wrong in new cursor window
6 K& ^3 t `- A/ h' l945242 SIG_INTEGRITY SIMULATION Unable to select "shapes" in find filter for 'show parasitic ' command" S1 D$ {. a( P# v6 \$ I
946293 CONCEPT_HDL ARCHIVER Archiver hangs if there is a whitespace at the end of the path of cref.dat8 m6 e$ J q' B% }3 {8 O
946770 CONCEPT_HDL CORE 揤iew Design� function is missing in Windows Mode after reseting the menus.# j4 j, y; D9 r' K6 T3 u) H: N
950994 CAPTURE NETGROUPS Problem in expanding the netgroup in Auto Connect to Bus function
1 I6 d' p: y! g- R* l1 Z953530 SIG_INTEGRITY GEOMETRY_EXTRACT Display Parasitics is displaying wrong results for EMS2D Field Solver compared to topology extraction using Probe.
( T, Z/ t3 s5 U3 C8 }6 I( M953713 CONCEPT_HDL PAGE_MGMT Random page replacement/duplication in block
/ n: e- d* ^2 P953917 CONCEPT_HDL ARCHIVER archcore should handle errors correctly B. d) t, @4 U3 G& I, T
953971 ALLEGRO_EDITOR MANUFACT NC Drill files not generated correctly when using the option "搒eparate files for plated/nonplatedholes�
& J7 N: L+ d% O$ ?954400 CAPTURE NETGROUPS BUS members of NetGroup are getting converted to Scalars in Export-Import NetGroup.
7 q+ Z/ P7 ]: N0 ?9 f954498 SCM B2F SCM crashes when importing physical5 C4 ^5 ^5 e9 C# z- L. ~; p
954623 ALLEGRO_EDITOR EDIT_ETCH Unable to complete connection with Add Connect - related to soldermask to cline check?
! Y# ^! p3 K ~0 f954894 ALLEGRO_EDITOR MANUFACT Dimensions disappear when opening database in v16.5 from v16.3
4 D1 \, A" k) d z# D955029 CONCEPT_HDL CORE custom text font size not recognized in symbol view
/ U1 e! S7 W2 G955133 SIG_INTEGRITY FIELD_SOLVERS The Field solver creates the differential trace model which is reversed T(D1) and T(D2) of bottom side.
# {. {7 t! q) v/ l& _9 N# O955290 CAPTURE DRC Description for UPD0014 missing in the Browse DRC markers window
' @7 P o ~8 R8 j( o4 ~955299 ALLEGRO_EDITOR DRC_CONSTR drc text to smd pin does not work any more on this database in 16.3 S039
f( |# m0 v4 s' C0 Z955338 CONCEPT_HDL CHECKPLUS Need to change PART_NAME5 g' j* Y& v8 Q) p* b% z5 ~
955447 SIG_EXPLORER OTHER Model path set in DE HDL Model Assignment not used by SigXP from CM in DE HDL1 j1 m: `2 |3 ]) e5 C1 X$ B
955740 SIG_INTEGRITY GEOMETRY_EXTRACT Crosstalk with Timing Windows does not work correctly
* s8 B+ a( q) C$ l955749 ALLEGRO_EDITOR MANUFACT show element Info shows symbol dimensions on incorrect subclass
( }, S) j# K' Z0 {) s- H7 z955912 ALLEGRO_EDITOR OTHER Shapes with voids that are exported to PDF have gray filled area over the void! ] v) r8 b* B: o, Q$ }% ^. r
956129 CONCEPT_HDL INFRA DEHDL uprev hierachical design from 16.2 to 16.5 packaging failure.' H W+ h9 E/ ]
956373 ALLEGRO_EDITOR NC drawing name doesn't display in the log file
. Z( d+ `7 A$ u. j0 d; j956393 CAPTURE PROJECT_MANAGER "GENERAL" and "TYPE" tabs are missing from " roperties" dialogue box.
1 e1 c1 I# p. m# E/ T/ U# X. F5 ~) @956448 PSPICE MODELEDITOR Can not generate a DEHDL symbol from Model Editor, because no Capture license found O, c, d7 h( }8 J( H* a
956456 CAPTURE NETLIST_OTHER OrTelesis netlist not transferring user properties defined under combined7 S6 G* [; b/ n/ K) U. h! o
956489 ALLEGRO_EDITOR MANUFACT dimensions lost when symbol with diemnsions attached to symbol origin placed on board
, f3 p( i. M% ]2 d$ |: u956603 CONCEPT_HDL OTHER Part Manager "has stopped working" after changing a component
4 {8 S- t- S; }5 B956751 ALLEGRO_EDITOR ARTWORK Import Gerber command does not work correctly0 x6 r: I. i( f
956847 PCB_LIBRARIAN METADATA PDV - Partdeveloper symbol to function linkage broken/changed in 16.5) y; x6 @3 L( j9 c- X2 ^9 j9 V0 X
956987 CAPTURE OTHER Find from "Search toolbar" doesn't gives complete results
. C: d: [+ m4 O5 l& `: [4 ?: y956996 CONCEPT_HDL INFRA Correction to ERROR(SPCODD-7): Following Primitive instance causes CM to empty
) C: K+ F2 s5 o, ^% {1 n/ `& [. f957009 CAPTURE NETLIST_OTHER Problem getting database property in mentor PADS PCB netlist
' n5 _, t0 u! w) u% T957137 APD DXF_IF DXF out command dose not work correctly." [; p' f& @9 h, z' z& s" ?
957167 APD GRAPHICS Highlighting for Static shape with display_nohilitefont environment variable.
5 u9 `/ |- G4 o957232 SIG_INTEGRITY OTHER Allegro crash during Model Assignment.8 a; u( V: D, G- X& L
957267 CONCEPT_HDL INFRA Packager Error after Import Design
W+ w! d$ H2 q* V {# O957866 SIP_LAYOUT DATABASE Cavity outline is not getting deleted from symbol file& J( Y! H$ ]5 D& J/ g* ~
958010 ALLEGRO_EDITOR REPORTS Wants the ability to extract "Batch" reports from Partition ".dpf" files.3 J" B" K t. [9 T0 I
958252 ALLEGRO_EDITOR TESTPREP Resequence testprep with the option - Delete probes too close crashes the design' s- ?1 W) W+ n6 u9 E$ S
958253 ALLEGRO_EDITOR REPORTS Shape did not have thermal relief connected to pin but unrouted nets still shows zero.
# h) g. q% U1 W958433 ALLEGRO_EDITOR DRC_CONSTR False embedded component DRCs' ` O- K7 Y) V: B9 g' H
958753 ALLEGRO_EDITOR SHAPE Dynamic shape is getting corrupted in 16.5
0 ^, S1 J: O& @959011 ALLEGRO_EDITOR OTHER copy problem of via and cline
f: E' ?: g- @0 E5 S959101 ALLEGRO_EDITOR EXTRACT Using extracta with excluding Thermal reliefs
0 U, d1 O; I$ [ D1 i C4 s959253 CONCEPT_HDL INFRA Design will not open
/ }2 H4 ~, d' T1 g959299 APD MODULES Getting ERROR(SPMHDB-279) when trying to update modules placed on the Top side/ i! p6 H* M, m0 h' g7 B$ k/ x
959884 CONCEPT_HDL INFRA Design Uprev/concept2cm crashes with Application Error/Out of Memory Error.( t0 I- G2 ~; z; p! I# f
959909 ALLEGRO_EDITOR SCHEM_FTB Site level propflow.txt file is ignored property is transferred
3 e' {* J( d. |960067 SIP_LAYOUT PLATING_BAR Creation of plating bar removes "NODRC_ETCH_OUTSIDE_KEEPIN" property from the clines.
1 R$ i! j0 n1 t- g960126 SIG_EXPLORER EXTRACTTOP Allegro PCB SI license is used automatically at Topology Extraction of Allegro Physical Viewer.
/ n- o2 \; j. b# g960143 SIG_INTEGRITY GEOMETRY_EXTRACT Running simulation in Bus sim happened crash while enable Coulpled Via model to S parameter V2 V4 q4 k' J; b- Z; A( \4 X
961349 CONCEPT_HDL HDLDIRECT Motorola designs have broken connectivity compared to 16.3
0 C' V" W0 n; ]+ R N0 e4 U961816 ALLEGRO_EDITOR INTERFACES Normal Export > DXF fails and offsets the pins of the BGA symbol/ n' B: @5 M: i
962519 SIP_LAYOUT WIREBOND Align option doesn't work for wb_tackpoint fingers- C( c0 N% }+ |# x
) S5 u `4 u; L& h5 ^: Q" W6 Z' f' m# x7 QDATE: 11-30-2011 HOTFIX VERSION: 012 H/ W1 y e! F+ O) ^3 Z+ a
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CCRID PRODUCT PRODUCTLEVEL2 TITLE
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959581 CAPTURE NETLIST_OTHER PCB Footprint is getting replaced by VALUE in OTHER netlist formats4 c; M- R3 b+ O, j# \" \6 r
8 ^) |3 _, X5 A% j' V# oDATE: 11-18-2011 HOTFIX VERSION: 011
3 P0 v1 b e3 p, R! J$ ^===================================================================================================================================
9 e6 X" P) r' ]! vCCRID PRODUCT PRODUCTLEVEL2 TITLE" w. j1 b- ]3 N7 @( b
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735439 PCB_LIBRARIAN CORE PDV Moving line-dot pinshapes by arrow keys breaks the pinshape8 H# l& t/ X! o, G$ N; h
894815 CONCEPT_HDL COMP_BROWSER Why does genlibmetadata command give 'Aborted $PROG' Message?
: w I& b3 m8 p903073 ADW COMPONENT_BROWSE datasheetl_url directive should support a display string for URL* ?! X4 i0 t. |1 h' n! {% O
909919 CONCEPT_HDL OTHER Why is the PublishPDF UNIX command line looking for "true" script?8 J& }. V0 ~ E
911561 CAPTURE CORRUPT_DESIGN Capture crashes on trying to save the design.
0 x7 v) b5 X& N. B G- }9 R' Q919579 CAPTURE PRINT/PLOT/OUTPU Print mode be selected based on schematic mode; P) X4 i4 a$ Y3 E
921247 CONCEPT_HDL COMP_BROWSER genlibmetadata.bat file does not have err defined
" ]: M( [' p1 ?% v6 g$ N3 ~925182 CAPTURE PROJECT_MANAGER ENH: Feature to run update cache on all the parts in design cache at once.
* Z. [, I1 c& w0 E& D2 |3 a6 n926858 CONCEPT_HDL CORE Usability- Modify Component dialog forces user to do 'Reset Filters' to see other ppt rows
, G [( H- y2 \6 p9 J9 r927657 CAPTURE NETGROUPS Enhancement: Placement of netgroup definitions under design cache list
8 c8 w$ t# u* A4 }3 P) f934684 ALLEGRO_EDITOR MANUFACT The relation between the linear dimension and the symbol breaks.
: J k" L: k, k' B s935836 SCM SCHGEN ASA crashes when generating Flat Document Schematic2 W( R; R. H/ l* S
937165 SCM SCHGEN Can't generate Schematic* u7 m# C/ G+ ~5 \8 a6 N# J) x
937292 CAPTURE GENERAL Memory usage keeps on growing and finally gets exhausted while search
8 ^# r& n) P+ b( A) m L937322 CONCEPT_HDL CORE Master.tag file alters the sequence of the files and Genview fails# Q2 |+ ]! W# C) ]+ V S
939135 CONCEPT_HDL CORE Unable to uprev a 16.3 Design to 16.5 with DEHDL-L License. b2 K8 y" U3 V3 x* B: O
940373 CAPTURE TCL_INTERFACE Enhancement: TCL command to add nets to Netgroup
- ^' w& t7 {' y5 ~+ [: O: H& V940547 TDA CORE ERROR(SPDWSD-69): highspeed cannot be checked in; g4 S1 {' ?/ K1 j# c
940607 SIG_EXPLORER OTHER Inconsistancy in License usage for opening sigxp -orcad
9 v2 V6 {; @, e940790 F2B PACKAGERXL User doesn't want to display pin numbers after Export Physical 16.5.
& v( ~" x, s/ A/ D2 Q! w940944 SIG_EXPLORER OTHER Inconsistant license usage while opening Orcad PCB SI using allegro -sq -orcad and allegro -sq2 B3 N" J1 d2 A; m- D" ?; |3 K
941354 CAPTURE NETGROUPS Enhancement: Option to rename the unnamed NetGroups
' f; M9 l& w* a- r941455 ALLEGRO_EDITOR MANUFACT The Dimensioned mechanical symbol when placed in the board does not show all the dimensions.
6 ~$ o& t2 U/ g1 c$ d$ n- m941863 ALLEGRO_EDITOR EDIT_ETCH Different behavior of design in v16_3 & v16_5 when add connect is executed on a segment thru script
6 H: y h+ E0 E; P1 Z8 E941881 CONCEPT_HDL COMP_BROWSER How can I suppress the dialog from universalbrowser -genlibindex?
6 B% i3 F6 o& x9 A942474 CAPTURE NETGROUPS NetGroup member type of last added member must be remembered by Capture1 q% K* s5 }* U' K/ M+ J: I$ S j% f
942522 CAPTURE GEN_BOM Export in excel check mark doesn't invoked BOM in Excel
9 g; P. s* P+ [8 a% j9 |942557 PCB_LIBRARIAN EXPORT_OTHER PDV Export to Capture crash H/ ?5 M1 q, p8 T4 N7 C6 d) [
942569 ALLEGRO_EDITOR MANUFACT Dimension move and change text deletes leaderless balloon
. A. j5 s2 ~9 a9 I7 o1 Q942573 ALLEGRO_EDITOR MANUFACT Balloon type parameter has no effect on leaderless balloon.
7 O' v% _) P, S1 S+ i! ?942613 CONCEPT_HDL CORE Genview supports only SCHEMATIC/SYMBOL/VERILOG/VHDL views as input type. .xcon not recongnised0 q$ O# ^0 {2 j
943032 SCM OTHER ASA is not passing the correct reuse_module name to Allegro PCB layout.+ s( ~% q0 A: [0 j# Q2 C: J: D; P
943401 CAPTURE NETGROUPS Alphabetical ordering of NetGroups in Place NetGroup
4 u, P/ g% m0 M944006 ALLEGRO_EDITOR EDIT_ETCH Vias added to shapes behave differently& O/ T; ^0 n; p" H0 U/ j7 k3 ^
944367 CONCEPT_HDL OTHER Too late to do Model Assingment in conceptHDL 16.5( E/ d/ x% V" p# q0 n
944788 ALLEGRO_EDITOR GRAPHICS Oblong Pad shows unexpected lines
# G- ]9 ~: @1 c- D4 J8 g# }945221 CONSTRAINT_MGR RETAIN_CNS CM Conflict Resolution fails on more complex designs using ECSets and constraints
- H% q( v+ o! C. e" P, {1 j$ ~946270 ALLEGRO_EDITOR PLACEMENT The Rotation Type was changed to "Absoute" if the "iangle 90" use at placementedit mode of spb16.57 V1 U* w6 E2 m1 `
946350 F2B DESIGNVARI Variant Editor rename function removes all components
) n: Z! _: [8 u# w7 ~* C1 {6 i946380 F2B DESIGNVARI Some VARIANTX properties are hard some soft - why?. ~1 K2 e" } Y5 J
946419 SIG_INTEGRITY SIMULATION Cannot select component on BoardModel for controller in bus setup form
& k/ S& J/ C0 {946458 SCM SCHGEN Schematic generator adding an unnecessary page
; g, ~' N# ~/ L7 r6 \2 z947667 ALLEGRO_EDITOR PADS_IN Need support for PADS-POWERPCB-V9.3-BASIC
9 B2 A9 i8 D# h" V. Q, j947789 ALLEGRO_EDITOR MENTOR mbs2brd crashes during translation on the attached design.
; s- W$ O% O% V9 c/ O) y- u948110 CONCEPT_HDL CONSTRAINT_MGR Concept HDL craches when opening SigXP from CM# B) D$ X0 T# r2 ~; n$ n) |
950970 ALLEGRO_EDITOR MANUFACT Unable to generate artwork, dbdoctor fails to fix errors.7 P; d$ v$ h/ o/ z1 A* w
951901 ALLEGRO_EDITOR EDIT_ETCH In 16.5 add connect to same net is shoved
: S3 `( D6 X3 ]2 D1 r; ?" ]1 h951919 ALLEGRO_EDITOR OTHER Exported package symbol soldermask and pastemask padstack locations not the same as original) J Y5 s$ Y5 j* v4 M2 {
951926 CONSTRAINT_MGR OTHER What is MaestroNotifyNotSetReport.txt file?
% C/ u$ s' h' X& \( K9 G+ l; K951939 F2B PACKAGERXL Uprev to 16.5 is changing refdes for some pages' ~, `3 z3 r8 P3 _4 o) H
951983 CONCEPT_HDL INFRA Problems converting an Allegro design from 16.3 to 16.5
7 g6 U8 a" u4 b952057 SCM PACKAGER Export Physical does not works correctly from SCM
8 |4 s- f' b7 Z8 f952217 ALLEGRO_EDITOR GRAPHICS crash when opening 3d viewer in PCB Editor
" L' G0 h4 z; r F1 j8 Z( m- C1 s5 a952634 CONCEPT_HDL CHECKPLUS Checkplus logical rule fails on a design which packages fine in 16.5: w% _" `4 K9 ^ B- Q
953018 APD REPORTS Shape affects Package Report result.
9 ~+ ^/ y3 _/ W; K; v: f953337 ALLEGRO_EDITOR OTHER Allow netname and padstack names to be visible for testpoint vias when viewed in Allegro PDF Publisher.
) r o2 r, F* N W# \1 v6 Y953827 ALLEGRO_EDITOR EDIT_ETCH Snake Breakout function crashed Allegro
7 t$ Y5 `' ]& M953918 GRE CORE GRE cannot route second and third row of pad in die symbol.
; P% Z4 `3 N3 @* y: {- v7 x954055 CONCEPT_HDL CREFER Crefer fails with UNC install path: [+ q$ w$ L3 k: A. t7 K" e
954920 SIG_INTEGRITY CIRCUIT_BUILDER Each neighbor crosstalk simulation crashes or returns blank report
5 h( F8 {% E8 S
9 I2 |$ |7 u3 I: _ N( @DATE: 11-7-2011 HOTFIX VERSION: 010# U. @; l* ~! Q% r
===================================================================================================================================
0 ~( b8 c) F% ]$ nCCRID PRODUCT PRODUCTLEVEL2 TITLE
- N$ ^5 H& \2 H N3 ?===================================================================================================================================
3 k b8 i3 k9 d- z& X, T; ^ `8 j' G658866 ALLEGRO_EDITOR EDIT_ETCH enhancement option - so that Sliding a via inside a pad does not create a cline' [6 X/ V% [ Z+ V3 l- I% N* d
928624 ALLEGRO_EDITOR GRAPHICS Layer visibility control for 3D Viewer
) w0 I$ e+ ~' m& _5 N% C934991 SPECCTRA LICENSING Specctra_adv option is not working correctly for PA3100 plus PS3500 license in v16.5 tiering profile
: K5 p" K' j" r4 Q7 N938073 ALLEGRO_EDITOR PLOTTING Plot Page size A0 and A1 with problem& U" U5 y& p' U
938128 ALLEGRO_EDITOR DRC_CONSTR DRC changes when do update DRC.
8 R7 S) ?5 J9 U* T) I938648 ALLEGRO_EDITOR GRAPHICS Enh - Requesting a way such that Package keepout appears transparent in 3D Viewer' m9 w# |6 s" N: x" y) D
940518 SIP_LAYOUT SYMB_EDIT_APPMOD Swap pins command doesn't complete4 O( s8 `* C; W
941426 CONCEPT_HDL COPY_PROJECT Copy Project fails - Updating opf view This can't happen!3 T+ [: ?% S5 M' r5 D
941499 ALLEGRO_EDITOR DRAFTING BUG imit Tolerance isnot working for Dimensioning
5 P7 k2 b: F/ k1 s% s941814 CONCEPT_HDL CREFER CreferHDL crashes during ScheGen+ ^3 A+ s2 @, Z P8 P. A* S$ B
942914 SIG_INTEGRITY OTHER ZAxis delay calculation5 T+ O! E( x+ H9 G3 m# H
943053 ALLEGRO_EDITOR SHAPE Modifying the Board Outline shape will cause the tool to crash
* N* U' F& }; a% X2 ^2 @( P8 I945321 SIP_LAYOUT EXPORT_DATA generation of a xml file from cdnsip for shrunken die, u" v/ q1 B1 m/ K: u' g+ I: w
945350 ALLEGRO_EDITOR SHAPE iPick does not work on shape boundary edit.' e3 ?! Z% r" j8 m, ]; y! @
945449 APD SKILL When they create a new menu entry with skill APD crashes with next menu selection." l( {. A q0 }. E6 b7 T" X
946390 ALLEGRO_EDITOR DRAFTING refresh_symbol crash when trying to refresh mech sym that has dimensions0 A0 s9 C4 c6 s! B t C
946401 APD EXPORT_DATA stream out gdsII results in shorting of PWR/GND nets due to elongated etch' ~7 l3 {, |4 s2 Z& e6 i
946819 SIP_LAYOUT DEGASSING Shape degass command) f9 e7 B4 {' {, Y7 F$ B8 f' ?$ O- K
946869 ALLEGRO_EDITOR OTHER Allegro PDF arc representation needs cleaned up- X5 _% @, P( F+ D7 }
947230 ALLEGRO_EDITOR SKILL Skill execution crash Allegro 16.5 but work correctly with Allegro 16.3
) K7 a7 v0 ?% ~8 \1 I947603 ALLEGRO_EDITOR OTHER Component Properties (Default or User Defined) not transferred to PDF file
( r" ~: z* s2 `2 j950995 SIG_INTEGRITY OTHER Netrev fatal error when importing logic7 ~, O3 m( w9 g) c7 m# X) a' L* H
951123 ALLEGRO_EDITOR INTERFACES IPC fails to output drill hole info in columns 33-37
; g: m; O7 H8 Y951557 CONCEPT_HDL CORE Cannot create the entity folder for old plumbing symbol
" l! }% n/ a$ l r( ~2 P3 [6 ]& U$ y+ k
DATE: 10-26-2011 HOTFIX VERSION: 009: b% _) Q7 u" _$ G
===================================================================================================================================4 a! u( u) w9 c# l6 \9 l
CCRID PRODUCT PRODUCTLEVEL2 TITLE
& D+ Q0 K1 H& f/ V6 f: @===================================================================================================================================2 i1 P) {: e+ @3 t
945788 CONCEPT_HDL CORE Some component properties on the parts are incorrectly changed after Import Sheet% }: G$ T! l B* U
945789 ADW LRM Some component instances are not updated by LRM even though cache ptf is updated from reference3 ]' D @& t, Y. l
* G8 @) F5 P% A* d
DATE: 10-21-2011 HOTFIX VERSION: 008( A1 ?6 c5 H: P9 R w2 W
===================================================================================================================================: k+ B" e# t! z
CCRID PRODUCT PRODUCTLEVEL2 TITLE
+ O2 @$ |! u) J" ^/ K! Z6 u7 B$ d7 m0 F6 o===================================================================================================================================
$ ~( V1 i2 G2 `$ F6 ?5 o/ t906827 ALLEGRO_EDITOR DATABASE Logic > Parts logic does not work correctly.
# |% n+ M$ c+ Y4 R0 b3 |/ N923346 CONCEPT_HDL CORE Not able to move the reference designators inside hierarchal blocks after uprev to 16.5
/ j& O) M3 x1 S0 R7 | O926347 ADW COMPONENT_BROWSE Usability- Libflow Part check in comment should end up in Comments attribute for UCB/Designer to see it5 T, _! A q' n% P2 k
929348 F2B BOM Warning 007: Invalid output file path name9 h0 b& c- h& e- ?& S# o8 [
929777 CONCEPT_HDL OTHER Component Revision Manager gives internal error3 P; d' |8 A% v8 S3 P* b6 g
930783 CONCEPT_HDL CORE Painting with groups with default colors
+ H3 ~! e, Q T$ l" A936748 ALLEGRO_EDITOR INTERACTIV "Unplace Component" menu inconsistent between General Edit and Placement Edit Mode.
8 \* @) m) K7 h8 \" [; B938143 ALLEGRO_EDITOR CREATE_SYM Why is this Extra Property 'ECSET_MAPPING_ERROR8 P. ~) ~8 D E. O; i1 M
938281 SIP_RF OTHER export_chips creating bad data when symbol is split and contains V- V+ pins: O( R( L3 d' V, q6 [
938812 ALLEGRO_EDITOR SYMBOL Cannot create a BSM with this DRA, errors out but does not state a reason.. s/ ?, Z l6 L2 r: _9 ~ Q
939075 CAPTURE TCL_INTERFACE Texts are getting garbled in command window& C+ c6 q z+ E* T- p7 ?
939193 F2B PACKAGERXL ERROR(SPCODD-439): Connectivity server is unable to load the design., E7 c) A, @% O
939199 CONCEPT_HDL DOC "Retain electrical constraint on net" mismatch between schematic (YES) and design (NO). F) Z7 {: v" }, \( M0 q
939346 ALLEGRO_EDITOR SHAPE Shape disappears when updating with variable shape_rki_autoclip set.
) ?9 k. I: q$ H4 f* H- j3 k$ O939901 CONCEPT_HDL INFRA NET_SPACING_TYPE shows �?� on lower hierarchy level nets after Upreving to 16.5 version.$ p/ [3 u3 w1 f% \$ ?# J* R
939918 PSPICE PROBE Print > Preview for output file causes Pspice crash.
' P" D. O/ g7 Q6 T' m6 W940217 CONCEPT_HDL COMP_BROWSER UCB reports 'No Symbol found for the part'
! }% h0 J& T/ w4 A, ~ [$ f940835 CONCEPT_HDL INFRA Desing package different after uprev to 16.5 where comp instance propeties are lost lost
( d; N/ K5 w: m4 W3 G! c941125 ALLEGRO_EDITOR DATABASE Performance advisor doesn't skip non plated slot padstacks4 z3 m+ c/ R( ]# P- I4 L7 v
941876 SIG_INTEGRITY OTHER Illegal model name cause pxl fail in 16.3
' h `9 m/ A$ B1 G& x& ?942210 SCM OTHER Is the Project File argument is being correctly passed?) |) a( V- V" g. T* P
942274 CAPTURE PROJECT_MANAGER Crash on renaming a Design Cache part in Project Manage after doing replace cache
% m# v+ h7 R, I$ J+ P, M942839 ALLEGRO_EDITOR GRAPHICS Graphics Issue- Pads are not visible
" V+ T' m; ?' X; f' i8 O8 Q943055 ALLEGRO_EDITOR SKILL axlDBCreatePropDictEntry causes application to crash+ I0 m( c" y' m) K# ^" n
3 e& R, F) J2 B/ o
DATE: 10-21-2011 HOTFIX VERSION: 007, n) _% T3 `* j/ q1 ^
===================================================================================================================================
" M7 h: @: W }3 n' u8 rCCRID PRODUCT PRODUCTLEVEL2 TITLE
! x @! B6 l9 |/ m# t/ t3 a===================================================================================================================================8 ?' Y& m0 S4 {' U
841096 APD WIREBOND Function required which to check wire not in die pad center.
7 B: b4 v( V, u+ C2 l& P$ f903263 CAPTURE SCHEMATIC_EDITOR ENH: Selecting parent netgroup must select the underlying netgroup bits." b- P0 v" ?" Z( m9 D2 G6 N! O
906692 ADW LRM LRM window is always in front when opening a project! b0 S. j( p2 t' C4 u
912942 APD WIREBOND constraint driven wire bonding
+ o! C: ]& A4 X5 w0 x912951 CONCEPT_HDL CONSTRAINT_MGR Need to manage temporary files on Linux systems
' t6 _% F! A; U5 r" C3 O0 l915178 SIP_LAYOUT DIE_STACK_EDITOR Die Pad names changing when updating Die in a design
8 k' O$ `& }: q! N7 P7 [- y917887 PCB_LIBRARIAN VERIFICATION Part should not be released if the alt_symbols has errors
4 l/ p0 E& C* Z* |7 W7 O923315 SIG_INTEGRITY GEOMETRY_EXTRACT crosstalk simulation fails with TMP popup failure6 C( U& N8 ]; I# c2 ^- d W
927382 CONCEPT_HDL CHECKPLUS 'Verify Symbol' forces the use of 'Concept_HDL_Studio' license: {3 { Q1 [: \8 O. C# E7 v
927664 CONCEPT_HDL CONSTRAINT_MGR Internal Error disposeipsp6 _4 Q" J4 o; t/ C' M
930152 CAPTURE NETGROUPS Scalar net names when being connected to net group overlap when connections are made one by one! @) ~* x' U' j
930180 CIS LINK_DATABASE_PA Visible property position on schematic get reset on "link database part" operation" {' q0 d. G* F" o# X$ S2 x
930188 CAPTURE DATABASE Capture 16.5 crashes in being re-invoked.3 T, c7 {" R9 d& s! _
930541 CAPTURE NETGROUPS NETGROUP element renaming doesn' renames the associated net ?
$ G: K5 y4 J x2 `7 G/ M930866 PDN_ANALYSIS SETUP OrCAD PCB SI Session crashes when we open PDN Analysis with "OrCAD PCB SI" license.
6 h$ @4 t5 P" g930926 ALLEGRO_EDITOR GRAPHICS Via and Holes not visible eventhough set to Visible in Color form4 @6 m! E1 ?* b! X3 c6 y
931274 ALLEGRO_EDITOR DRC_CONSTR Negative Plane Islands waived DRCs reappear after performing update DRC.$ [ L' t% {) B6 h
932091 CONCEPT_HDL CORE Prop attached to SIG_NAME property2 s7 B! U; }1 u: T# ^, k3 T0 H$ D, ]
932255 ALLEGRO_EDITOR GRAPHICS Change in Zoom level makes arc segment to disappear' @9 v! v$ v* Q( S7 `$ f! D; f: k
932292 ADW LRM LRM crashes during Update operation on a customer design: l) G8 q7 k+ L
932639 SIG_INTEGRITY OTHER Add Connect command hangs for about 14 seconds and then returns.
1 g+ d5 G. \* ]& P932704 APD DEGASSING Shape > Degass never finishes on large GND plane: g, R. z* S* }6 | T( V
932871 APD GRAPHICS could not see cursor as infinite
+ |- _9 ^ P8 Z4 ?: O" r- j' x932882 CAPTURE SCHEMATIC_EDITOR Capture crash with FIND command - ISR05
% i, O. [( a0 V932969 CONCEPT_HDL CORE ConceptHDL crashes when you save the design in 165 > hotfix #05, d. h( @1 G/ v
933024 CAPTURE NETGROUPS Naming restrictions for NetGroup members
8 L+ V. X/ _* s* E5 L933145 F2B PACKAGERXL Add Subdesign list is truncated in Force SubDesign Design Name pulldown
2 j) z1 x- @9 ?/ A9 V* z% I933214 APD ARTWORK Film area report is larger when fillets are removed
4 q# p- n7 j: }/ h9 r, S+ c4 o933356 CONCEPT_HDL CORE Net prop display size become 0 if it was attached to SIG_NAME prop.
5 Q D; r) h9 Q" E$ c; {- Y: O6 C# t933532 ALLEGRO_EDITOR COLOR Bad color assign and initialisation during creation of new subclass( v9 O- S8 o% N9 H
933549 ALLEGRO_EDITOR OTHER Chart text missing in export PDF file.6 K* }9 H# o# p4 \% }( T6 G
934008 ALLEGRO_EDITOR REFRESH refresh symbol updates symbol text to some unexpected values
+ v& Q' t: D4 F3 ~( c934031 ALLEGRO_EDITOR DRC_CONSTR Bug : Update DRC removes Waived status for some DRCs5 H: I: G4 l7 u
934087 CONCEPT_HDL CORE Opening DEHDL and Model Assignment before design loads causes crash3 c$ y6 h% m/ v1 z
934396 CAPTURE SCHEMATIC_EDITOR Find operation is not searching power symbols with + or - signs.* g/ q4 {+ h9 ?
934533 F2B DESIGNVARI The Variant Editor errors are not written to the variants.lst file
$ A# D3 n; b# n. {934811 SIP_LAYOUT UI_FORMS CDNSIP should not hang if contraction value in z-copy command is out-of-bound5 J1 s$ Z! S: \ K
934909 SCM UI Require support for running script on loading a design in SCM
1 V+ A% c2 |& j J, [! \7 ~; M935632 CAPTURE SCHEMATIC_EDITOR SHIFT+Mouse wheel scroll(horizontal) of page is not working in Auto Wire Mode.6 A; ?+ ~" g+ K& |
935794 ALLEGRO_EDITOR SHAPE BUG:Shape not filled in 16.5 but it does in 16.3
+ n' t' R. ~0 q8 p8 U/ m6 p" R935988 ALLEGRO_EDITOR INTERFACES When attempting to downrev this 16.5 design to 16.3 the tool will crash
4 h* X* V3 `, g, j! A Z |, ?. I, X936056 ALLEGRO_EDITOR DRC_CONSTR place_manual crash while moving mirrrored symbol
7 M; l3 e+ |5 u a, n4 \& U E936098 ALLEGRO_EDITOR SKILL axlDBCreateCloseShape does not work correctly.3 R: f' I6 G& Q1 Z' c0 t
936212 ALLEGRO_EDITOR INTERFACES DXF not created if Blocks created for Symbol and padstack) [) q) Z4 T3 P+ R
936797 CONCEPT_HDL COPY_PROJECT Copy Project crash
7 u) I3 Q4 g3 T2 b+ T# o936808 ALLEGRO_EDITOR DATABASE Allegro crash replace mechanical symbol( f6 q, K4 r4 b. ~* Q L( n% i
936853 CONCEPT_HDL CONSTRAINT_MGR DEHDL crashes when trying to extract net from CM1 _' w! z+ M( m0 q/ j8 Y8 @% @
937087 CIS DESIGN_VARIANT Upreved design becomes very slow in Variant view mode. DELEET THE DESIGN AFTER RESOLVING THE ISSUE
5 m# W2 {+ l6 i$ e937173 CAPTURE OTHER Wrong license information "UNLICENSED" in Capture >> Help >> About
5 A d6 f1 O( ~* `* T& f* B' E937290 APD PLATING_BAR Plating Bar checks does not recognize connection made through etchback through shape.& t6 d3 k$ ` U
937411 ALLEGRO_EDITOR DATABASE downrev_library reading from one directory and writing to another hangs the command.; {8 E7 _3 e8 e* }+ K; g
938235 SIP_LAYOUT STREAM_IF Die Orientation is not correct after importing a stream file.
/ M0 y( u& D) y m* N938273 ALLEGRO_EDITOR OTHER PDF export is is not opening viewer with ads_sdlog variable set {2 Z* c3 Y8 p) s& G B& B# ^
+ I. x4 B2 p3 U5 Q
DATE: 09-16-2011 HOTFIX VERSION: 006; c$ X* R1 x# M9 Q3 b- p
===================================================================================================================================
9 w: k7 l; i0 g* Y4 _CCRID PRODUCT PRODUCTLEVEL2 TITLE" {7 ~- h; E" _, O
===================================================================================================================================9 Q1 T8 x: q9 P. ^0 m0 n4 Y7 y8 y
820131 CONCEPT_HDL OTHER Moving symbols to other page will make Allegro components unplaced because logical_path changed.( i1 l0 v% [+ o# `+ ~) G3 O
863860 CONSTRAINT_MGR SCHEM_FTB CM should display or Local Interface and Global nets to help defining low level constraints
! R2 L% {0 ^7 J6 F$ D7 N) E$ T919822 TDA CORE Cannot configure LDAP to only list the login name
9 s! H, e6 Q/ W5 ]; \: i( K; s5 \0 l% d922907 ADW TDA 搇ast_callout_file� directive in the BOM section is empty causes tda for show Access Denied error) Q# Y9 S9 G" [" c9 H9 x+ `
924322 ADW COMPONENT_BROWSE Random - No instance properties are added on Add To Design (RMB or double click) from Search Results6 p6 C0 o8 j" _* p h
924448 F2B DESIGNVARI Design does not complete variant annotation5 H9 y$ p3 w0 e8 r4 ]
925584 CONSTRAINT_MGR SCHEM_FTB 16.3 upreved Design passes the SLOT/Function Properties to PCB7 _5 v6 N# ^. w6 k N
927102 ALLEGRO_EDITOR OTHER Question of Conductor Detailed Length Report
' R4 L: U2 ~! N# w927104 F2B DESIGNVARI Tools > Annotate variants crashes when there are ASCII characters in the property values6 S5 Q2 p3 S- }# D" T
927142 F2B DESIGNVARI Incorrect pop up asking while executing variant editor from the command line
7 K$ o+ U7 c7 n& i9 ^* \0 p: Q" Y% M927166 CAPTURE NETLIST_ALLEGRO ENH: Feature like NET_SHORT in Capture Allegro flow which allows user to short 2 or more power nets' b0 U. o8 Z& `" h" Y1 O
927410 ALLEGRO_EDITOR DATABASE ERROR(SPMHUT-144): Illegal arc specification error when Run DBDoctor# Q1 O1 n0 n8 c
927475 CONCEPT_HDL CORE About forcereset command of nconcepthdl
" P& F$ q0 ^, v2 Z927498 CONCEPT_HDL CORE Pin_Name starting with minus causes incorrect behavior for $PN display
& z% `% C' k) V( ^927608 ALLEGRO_EDITOR PADS_IN Import PADs fails with error message: Failed to close the Allegro database: B) Q( i6 ]" C$ Z7 Z
927637 SCM CONSTRAINT_MGR ASA crashes on change root and also performance is too slow.
8 Q/ J# Z1 H- i2 |928429 SIG_INTEGRITY OTHER Request - Package Wizard to work in PCB SI.
- q7 d x# G. B$ J3 n8 J( P; Z" @& D928483 ALLEGRO_EDITOR DRC_CONSTR Running Update DRC removes Via List DRC Error when via is actually not in the list# I* ~ N2 X. g& q. f0 ^; Q9 s
928738 PSPICE PROBE Y-axis grid settings for multiple plots9 V7 U ~, S% O9 R4 P/ k Q
928748 PSPICE PROBE Cursor width settings not saved/ Z7 g4 o& `0 ?0 b/ C- }
928779 CONCEPT_HDL CORE Error (1053) occurs on a copied part in SPB165 release
& c3 Z" Y2 K/ V5 T- z, T0 J928838 CONCEPT_HDL CONSTRAINT_MGR ECSets not migrated in 16.56 |8 D: X+ X1 I
928885 SIG_EXPLORER EXTRACTTOP PCB SI crashes when extracting a net from Probe
, B5 J) f4 H. \8 L, ^929284 CONCEPT_HDL ARCHIVER archive does not create a zip file
' |9 \ Z' p3 W* X1 j# k0 w; w0 ]929542 SIP_LAYOUT DIE_ABSTRACT_IF net issue of multiple ports of co-design die in SiP5 P( j1 K" P7 X7 Z- ^2 @; n
929656 ALLEGRO_EDITOR PADS_IN PADS translation fails with Microsoft Visual C++ Runtime Library error/ B2 x9 ?5 Q+ o6 S9 h6 F# E0 B) O$ L% m
930063 ALLEGRO_EDITOR TESTPREP Test prep crash Allego when it can not create pin escape9 Q2 f6 f# v4 z/ I1 H5 W
930217 CAPTURE NETGROUPS Net aliases doen't gets assigend to bus bits if bus name is checked in NETGROUP.
i! O# S; F; g) ^& x% U% ~. F; M; ^ _930355 SIP_LAYOUT WIREBOND about "wirebond add nonstandard" command
# `% y% H+ B9 V. u, Z930607 APD OTHER Layer mapping information is reomved from Layer conversion file upon exporting DXF from board file.
8 t# L/ h; O2 j. |$ L: v( q! u930646 ALLEGRO_EDITOR DRAFTING Bug - Adding Linear Dimenstion for ISO standard add the Angle information as well5 l! d$ g! Z% Y6 Z0 F2 L
930894 CAPTURE TCL_INTERFACE PDF export doesn't creates property file if some symbols are used in page name/folder name
1 p0 Z1 J7 L& v/ M( {930944 ALLEGRO_EDITOR OTHER Setting variable 'appmode' equal to 'none' is not changing the Application Mode when reinvoked E5 o! l6 r8 f7 h3 _
930978 ALLEGRO_EDITOR SCHEM_FTB 3rd party netin error - Pin is connected to net <netname> not reconnected no longer happens
! s) f( Q }2 b3 d, k1 k931248 ALLEGRO_EDITOR DRC_CONSTR Match Group was removed if member nets became xnets.2 Y- `8 w+ c$ g Z( E
931278 CONCEPT_HDL INFRA $PN gets copied when upreving design from 16.2 to 16.5 version
% B' q0 y" X: a* D6 r931349 CONCEPT_HDL COMP_BROWSER DEHDL craches and corrupts connectivity file when using Modify command extensivly.
* S. s! R l$ o) I& p! ?$ f/ O5 R' X# K( P' t3 u
DATE: 08-31-2011 HOTFIX VERSION: 0053 w. ^0 g2 b1 {- k9 b: l
===================================================================================================================================/ Q( W$ A3 F9 Q: B
CCRID PRODUCT PRODUCTLEVEL2 TITLE
2 S0 b! M* ^" v/ G$ B$ n! u$ j===================================================================================================================================
+ ~* ]$ R$ ]8 |9 d825848 ALLEGRO_EDITOR SHAPE Shape not filled when edges from 2 RKO shapes touch around mouting hole
, o N. D2 S0 D4 f837723 CAPTURE PROPERTY_EDITOR Occurrences of external design not related to current root should not show T7 w, v4 I* v8 P7 P( x% G' M
891079 CONCEPT_HDL CORE DEHDL crashes with large number of commands in Winodws mode4 r" C: D- r7 x8 D/ k
910908 SIG_EXPLORER OTHER Cannot open top if Tx AMI dll name contain more than 2 dot.
+ i. s* T9 O7 T914036 CAPTURE LIBRARY ENH: Option to delete a corrupted part from a library and leaving other parts intact in the library.! O& p4 S/ e( a& m0 A k
914679 ALLEGRO_EDITOR INTERACTIV Custom toolbars are not retained when switching between brd to dra and back to brd file using the File > Recent Designs
2 L; D; H- l9 ?' F: d1 d914870 MODEL_INTEGRIT OTHER mergedml fails to merger 2 DML files from the model integrity7 I0 X* b- b& _! ]* a3 {& s
915645 ALLEGRO_EDITOR MANUFACT Allow the user to place the cross-section chart at a desired location
* b u- Y4 ]' f& c" |1 d- l# }/ b915653 ALLEGRO_EDITOR INTERACTIV unable to delete non-etch shape; a/ U4 E2 _+ ?" J9 V- o4 U
915711 ALLEGRO_EDITOR MANUFACT dimensioning tolerancing by limit not working
$ G7 }. |9 y9 o4 L! v- `916321 CAPTURE GEN_BOM letter limitation in include file
9 D$ t3 Y# \3 H G4 U916907 CAPTURE SCHEMATICS 揂uto Connect to Bus� should place the wire through non-connectivity objects. l+ T6 `) N6 O- v) _
920327 CONSTRAINT_MGR ANALYSIS The TotalEtchLength predicate in Constraint Manager does not work for a netclass with a bus.
2 C) X( |/ }& S. ?920753 ALLEGRO_EDITOR GRAPHICS If I confirm to padshape with zoom-in after install the s002 It was changed to wrong shape.
* h+ \" \' ?7 y3 s' m- m* v921097 ALLEGRO_EDITOR GRAPHICS Padstack seen partail filled when Zoomed in even "static_shapes_fill_solid" is set; P6 `. p; U9 F1 ]& Y6 _
921226 ALLEGRO_EDITOR DRAFTING Unable to select Package Geometry class when dimensioning in the symbol editor.
& Y7 A2 n, b7 X7 N921623 ALLEGRO_EDITOR GRAPHICS Bug : Symbol not visible when zoomed in 16.5 S002
- o, i6 a e' Z; U5 A! r7 h' w921891 ALLEGRO_EDITOR DRAFTING dimensions are lost after downrev(ing) a SPB 16.5 design with associative dimensions8 I% q: W3 v& w" d$ _* [
921937 ALLEGRO_EDITOR COLOR Padstacks with shape symbol are not showing correctly
- ?: w2 U7 G0 y: E2 w0 R922066 CONSTRAINT_MGR ANALYSIS Custom measurement Actual not being cleared when layout changes. ?: H3 c' E: x# x" J
922117 PSPICE PROBE Label colors are not correct in Probe( Z. l& j6 a. b7 u' I2 z
922519 ALLEGRO_EDITOR SKILL add_bviaarray command fails for some clines but not all
C# Q" v; q! r' a$ W923224 ALLEGRO_EDITOR GRAPHICS Thermal flash Display problem in Allegro v16.5 Hotfix S002" f) n8 k+ k7 g3 o( Q L, u
923286 CAPTURE DRC DRC markers not reported for undefined RefDes9 c, b0 u1 y) N/ U# U% A
923362 ALLEGRO_EDITOR PLOTTING Print to Postscript file not correct in 16.58 L; w" {# f+ X8 g
923416 ALLEGRO_EDITOR PAD_EDITOR Pad Designer crash on clicking on the Arrow before Soldermask_top
/ S1 _/ ^8 b% Q7 G% `; ]923507 CONCEPT_HDL CONCEPT-PCBDW The function of Import Design in the SPB16.5 Design Entry HDL (for data of ADW15.5_S23 + SPB16.3)
9 E" R+ O7 |) I: l- _5 }( L* W923910 CIS PART_MANAGER Copy & Paste operation from Part Manager copies properties only to first section of the part.
, [/ j% @2 C8 e# P9 |923913 CAPTURE PROJECT_MANAGER Capture runs slow on attached design
6 T5 g2 N! i4 S; H- W p, i923937 CONCEPT_HDL CORE Back annotation time significantly increased with the metadata generation on
( Q2 E. ` V5 F( x923949 ALLEGRO_EDITOR INTERFACES Incremental DXF_IN gives 'Invalid subclass' error& `& |( j4 o C& _- z
924458 SCM OTHER Project > Export > Schematics crashes
. P" c" w6 H* y; j" V924621 ALLEGRO_EDITOR SHAPE Dynamic shapes are disappearing upon updating them to smooth.
6 J2 {9 N3 b. E" U. F925193 SIG_INTEGRITY FIELD_SOLVERS Diffential Impedance (DiffZ0) values computed in the layer stack-up is incorrect. { H+ f b% L: t
925195 ALLEGRO_EDITOR DRC_CONSTR Incorrect pin to shape DRC error8 h5 z9 ]8 s0 O M! ~
925338 CONCEPT_HDL CORE This application has requested the Runtime to terminate it in an unusual way
) M! ^2 I/ |/ z3 S925435 CAPTURE TCL_INTERFACE Capture crashes if 揝ave design as UPPERCASE� option is disabled.) h1 C8 r% U5 T- W$ V
925530 SIG_INTEGRITY OTHER Why the single line impedance value for Top and Bottom layers are different for this design?
; R: _4 w6 U6 E" u, }$ u6 r, q925864 ALLEGRO_EDITOR DRAFTING Ability to add dimensioning to different CLASS/SUBCLASS
: z+ ~& [9 _/ t925976 ALLEGRO_EDITOR MENTOR mbs2brd fails to import data/ W! @! t4 S! o2 z) V+ b2 }
926409 SIP_LAYOUT DRAFTING Exporting a 16.5 design to 16.3 will cause the leader/dimesion lines to be removed.; H/ `6 I) c5 q8 e5 q( w2 ?. ~% k
926443 CONCEPT_HDL CONSTRAINT_MGR In new 16.3 "035" ISR Concept2cm will crash with error. B6 k" l8 L) |. q7 t! M; C
926503 CAPTURE GENERAL Memory leak Capture/Pspice# V1 x8 C% [5 z& T! g& y8 K
926553 CONCEPT_HDL CONSTRAINT_MGR CMGR ERROR There is no net in the Cset that has pins matching those in net 1 in the Xnet* p2 N3 w1 [2 Z: \4 N
926691 ALLEGRO_EDITOR OTHER Crash while Importing Technology File in CM, with Overwrite Constraints." y2 ` ^6 L N4 }* A. I) g
926887 CONSTRAINT_MGR CONCEPT_HDL Pin pairs lost after Export Physical
% ^% B8 u6 W2 D7 h' F) m927159 CONCEPT_HDL CONSTRAINT_MGR Export Physical fails due to errors in ConCM.log when SIGNAL_MODEL injected property is ''
, t$ v, x2 C5 h! N% | P
1 {1 n7 H) l- W8 a3 z" A" Q; {5 iDATE: 08-19-2011 HOTFIX VERSION: 004
, \& I% y) n7 W) [6 b===================================================================================================================================
. i4 [: m. ]/ \CCRID PRODUCT PRODUCTLEVEL2 TITLE
& |; x# o! N* I! U6 D% i===================================================================================================================================
% @3 ^/ x! @; a$ t785417 CONCEPT_HDL COPY_PROJECT copyprojectui crashes with a Windows runtime error
/ P* A( j1 W) g) Y851044 CAPTURE GEN_BOM "Export BOM report to Excel" does not appear in the Standard Bill of Material Window.
% a0 V9 K) C9 @# r" [( N* h868216 PSPICE MODELEDITOR Encryption of subckt names, internal nodes, comments
4 j7 C4 d* w- Y% V: q' w870247 PSPICE SIMULATOR Encrypt a model and simulate it, info about inside nodes being dumped in the probe file
4 L5 O) D$ ?+ g877091 CAPTURE SCHEMATICS Save JPEG, GIF, PNG and other image formats in the database in its compressed form/ u V( V+ M# e7 X4 s
894059 CAPTURE OTHER Enhancement: Adding column in edit>browse>parts window7 r' v+ d. U( N& f* l0 c
895902 RF_PCB OTHER Alphanumerical allegro pin numbers are unusable in ADS 2009 Update 11 }1 l0 i9 w: T- {- T
895919 RF_PCB OTHER Round trip Allegro to ADS to Allegro requirement
2 U9 m7 U" H' O6 ^903102 ALLEGRO_EDITOR OTHER Zcopy shape command for cline seems not to work correctly.( m3 a1 B% T+ ]6 ~7 {
905562 SIG_INTEGRITY SIGWAVE Noise margin seems not to be measured correctly with Eye Measure function.
- I% v: r' R* B6 M) v909469 SCM TABLE ASA crashes when opening project: p/ G h' \: M6 T n
909595 APD LOGIC Inconsistency between export die text out and show element after pin swap- ]1 ?8 S; j- Q: V9 D1 H4 q
911123 CONCEPT_HDL CORE 16.2 Design uprev to 16.5 fails with ERROR SPCOCD-152
) i {) ]/ J. [911569 CAPTURE EE_INTERSHEET_RE Q: Why is capture assigning incorrect Irefs in attacehd design ?* v, `+ t& X1 ]/ L9 ^+ O
915657 ALLEGRO_EDITOR OTHER Allegro PDF Publisher Mirror capability
$ l5 r$ k, x2 f; Z) M$ w9 h& I4 s915755 CONCEPT_HDL CONSTRAINT_MGR Cannot view net in SigXP
3 T2 D, \9 n* v3 x( n, d# d916062 CAPTURE GENERAL Auto Wire Crashes Capture; G K W& r- K2 s$ g& _
916820 F2B OTHER RF create netlist with problem7 ]# p7 s4 m) S) A F3 x1 W& q* L2 u
917967 ALLEGRO_EDITOR REFRESH Update symbol resets refdes location for bottom side components only.
) X5 y# X" l. Y v& D* ^919343 ALLEGRO_EDITOR PLACEMENT Place Manual is crashing the board file
7 e& ?9 c7 Y5 o* m, S, V S919481 CONCEPT_HDL CHECKPLUS CheckPlus isGlobal function is not working; P0 d* G, `% W+ W/ z) U. N% K% U2 {
919510 CONCEPT_HDL PAGE_MGMT takes 10 min to insert page in DE HDL
+ p& p: p$ d5 p' k6 w919976 APD DATABASE Update Padstack to design crashed APD.
6 e: X" R4 w" W- F0 O( ]6 f920418 SIP_LAYOUT OTHER SiP enhancement to Auto Assign Pin Use to add ability to change the pin use definition+ z! V" r) E3 Z( ~' k2 |& z3 O
920420 SIP_LAYOUT LOGIC SiP enhancement to Logic Auto Assign Net to display a dialouge Auto Pin Use assignment should be run& X V4 R; I5 U' e
920712 ALLEGRO_EDITOR ARTWORK Program has encountered a problem ... error when creating artwork' O( u3 E: c* F3 x4 O/ a- r6 F4 k
920763 ALLEGRO_EDITOR ARTWORK Soldermask gerber missing thru-hole pins P* M7 ]2 N% f/ v& [. r+ E
920976 ALLEGRO_EDITOR GRAPHICS Question regarding the difference in the behavior of 3D Viewer w.r.t. height_min2 ]3 @( n6 N0 z) R. O
920993 ALLEGRO_EDITOR DRC_CONSTR Minimum Metal Spacing Error is detected on Same Net
; C! B* m$ z& j921727 ALLEGRO_EDITOR DRC_CONSTR Pad Boundary causing P/P drc to adjacent symbol.1 D) `* i! N- E, Z& x r
922579 CONCEPT_HDL CORE Xcon file gets corrupted upon Save of Hierarchical design with Global nets tied to interface nets
' f% U. t9 N: W922592 CONCEPT_HDL CORE DE-HDL does not report illegal connection when Global Net tied to interface net using an Port symbol and named
8 n1 E4 O! V# X" Y, _$ E922758 ALLEGRO_EDITOR DATABASE Allegro crashes while placing second mechanical symbol with route keepin+ Q; N7 C! q6 ^) U! A( x' g; p5 G' z
922839 ALLEGRO_EDITOR DFA The DFA drc display is unstable.
: D; k4 x* Y' T& G' n923293 ALLEGRO_EDITOR INTERFACES File> Export> IDX is failing for this design while creating an empty error log.7 |; q& s$ [2 n/ g( i4 Q; P' }0 q
924772 ADW PCBCACHE Import Sheet is not bringing in Parts used in the source pages into target cache ptf
. Q6 ~6 @, g* ^3 v9 t$ a' O& s5 z5 r/ r
DATE: 08-4-2011 HOTFIX VERSION: 003 }: x: [- K& J4 S1 E
===================================================================================================================================
! Q- d, ?5 Y; {: w4 v) j; nCCRID PRODUCT PRODUCTLEVEL2 TITLE
% ?6 J& y# U/ J V===================================================================================================================================) I f7 O4 f/ X8 P- @# a2 I/ x
787414 CAPTURE PROPERTY_EDITOR Part value can抰 be moved on schematic if a part has been copied to a new design and not saved yet.6 z& a- @6 i$ y8 I: W1 j
903898 PCB_LIBRARIAN GRAPHICAL_EDITOR PDV move symbol graphics and Undo causes corruption in graphics) x& o" _$ L+ S. p; r
904287 ALLEGRO_EDITOR ARTWORK some cline with arc is missed, when creating artwork.; a2 I/ n8 C! |/ s7 y+ h3 Q' J
904418 CHANNEL_ANALYS SIMULATION channel analysis sim does not give valid result3 R/ r% L+ v- j4 x! H% x6 Q; t5 i
905777 SIG_INTEGRITY SIMULATION User gets popup message that halts an analysis until it is acknowledged
: b2 w9 y. c% e8 l* }8 l906139 SIG_INTEGRITY OTHER Bus sim result were cleared at the next run even if no preference changed.
9 R1 P/ [+ @- b1 j908680 SIG_INTEGRITY OTHER Extra prop delay due to resistance
7 M% X6 |) Z; k# H. J- _6 h* @" s& y, S909583 ALLEGRO_EDITOR SKILL axlPolyOperation AND operation is not working correctly.
3 t) u; A: T& w2 e$ O" k, D910315 ADW LRM Import Design with ADW causes partmgr and pxl errors
' V5 f# \. x) n' P- [5 U! c910689 CONCEPT_HDL CONSTRAINT_MGR NO_SWAP_COMP warning after uprev to 16.5
" O- L3 Q& }# q! v* O6 o911684 CONCEPT_HDL CONSTRAINT_MGR Attribute Definitions are incompatible for attribute 'HEADER'. when attempting to place in 16.5
4 C/ [' N4 u' e* K4 @912343 APD OTHER APD crash on trying to modify the padstack6 P# |: P% d. i9 t+ a
912384 PCB_LIBRARIAN CORE PDV Symbol Editor often freezes when moving groups objects by arrow keys
4 ]0 l P. [3 ]' q( J912853 APD OTHER Fillets lost when open in 16.3.
y e7 x" m0 L9 h' K/ X! d913586 ALLEGRO_EDITOR ARTWORK Cannot create the drill figures in this design.) H# \8 b7 I' [0 Q8 ?+ g
914009 ALLEGRO_EDITOR DRC_CONSTR Diff impedance worksheet showing almost zero impedance for differential pair in attached testcase.! }4 V' p" @4 u
914110 CONCEPT_HDL OTHER DEHDL 16.5 Uprev overides property values on hierachical blocks* U& k; R- y( U/ c& o
914264 F2B OTHER Cross Probing from DEHDL for global nets present inside block doesn抰 highlight in PCB Editor.
; K1 [, H% l6 d6 n4 V* u% Y/ s. ]914309 CONCEPT_HDL CORE 16.5 DEHDL crash on saving the user design# \2 j2 q I+ R a3 z/ V1 C
914558 ALLEGRO_EDITOR ARTWORK Gerber6x00 output creates unpainted niche in a shape
* E m& u7 L x914633 ALLEGRO_EDITOR ARTWORK Artwork failing in v16.5 while the same design when downrev'd to 16.3 is working fine./ c/ F3 ]. {3 T
914634 ALLEGRO_EDITOR SKILL IsThrough flag for a padstack is reset
4 Z. f! A T( h$ I" e914746 ALLEGRO_EDITOR DRC_CONSTR DRC Update repeats takes longer on each successive pass.
) b- V# o; u# L9 L- p914962 ALLEGRO_EDITOR SHAPE Corruption with Shape filling" Q2 n0 |+ d* D3 T6 a6 W
915583 CONCEPT_HDL CORE performance issues in 16.5 compared to 16.3+ w' O) M% ?: o5 ]- F
915630 PCB_LIBRARIAN OTHER Error when running SI Model Interface Comparison using IBIS models
, f4 X* @" R7 n2 M1 r2 S6 ^6 G915742 CONCEPT_HDL HDLDIRECT I get a newgenasym error and crash when trying to save the symbol
9 |/ p5 i# {+ i916154 SCM NETLISTER scm crashes when exporting physical database to allegro' `! P9 c; |' A6 ^% b9 e7 R
916448 CAPTURE NETLIST_LAYOUT Capture 16.5 Layout netlist contains errors
+ b2 i( o# `. g6 ^0 R+ v& u* I6 O$ B916462 ALLEGRO_EDITOR DATABASE Edit>Split_plane>create hangs Allgro PCB Editor
8 }, M- `5 R: c( I916469 ALLEGRO_EDITOR REPORTS One Unrouted pin does not show in Unconnected Pins Report* s- ]* E4 L5 \6 ^. A
916495 ALLEGRO_EDITOR INTERACTIV Pick selects components from invisible (Off ) layer2 I/ B6 b% c- ^/ v: [' M
916889 CAPTURE NETGROUPS How to change unnamed net group name?2 c: ? B& Q0 a% a' w
917002 ALLEGRO_EDITOR OTHER Allegro PDF Publisher creates extra circles not available on film0 y Q5 h5 o2 `, j/ J. n
917434 APD OTHER Stream out GDSII has more pads in output data.
$ K3 D7 L# ?" J% t917739 CONCEPT_HDL INFRA Global Net tied to port is getting split into 2 nets in 16.5, in 16.3 it is treated as a single net* x) t) F9 s8 ~+ h7 ]+ i8 l4 o0 A6 C
918187 CONSTRAINT_MGR OTHER Missing acGetTotalEtchLength predicate.( S# @3 [+ V1 ?+ q/ A
918576 CAPTURE DRC Incorrect DRC is reported for visible power pins which are connected to power symbol: W6 e$ \! \* X3 V( c( ?
7 I( N, V: Q# u+ n2 L3 L7 oDATE: 07-24-2011 HOTFIX VERSION: 002
2 j- o4 x1 o9 F1 c: J$ t===================================================================================================================================( @) I( w; d& N: N" l. \' Z5 M
CCRID PRODUCT PRODUCTLEVEL2 TITLE- ]& J7 y: n# j [- _1 g8 |0 d6 S
===================================================================================================================================
" }. l0 D! H9 N6 c" F8 P527444 ALLEGRO_EDITOR EDIT_ETCH Slide command needs to be enhanced for same net spacings3 I& |, P- M0 v
583257 ALLEGRO_EDITOR EDIT_ETCH Add Connect and slide command needs to be enhanced for same net spacings.0 j" i7 v6 M, R
592956 ALLEGRO_EDITOR EDIT_ETCH Same net traces will not push and/or shove each other.5 _* i6 Q) m" J* Y) {% W7 `
745285 ALLEGRO_EDITOR EDIT_ETCH Requesting a true "shove" in Route > Slide for Same net routing.
+ \8 K5 a5 h9 I. A: r3 j773503 CAPTURE OTHER Doing "Mirror Horizontally" creates extra un-connects or extra junction dots in Capture V16.3.
9 P. n9 @) f# x6 o3 D0 _4 r. p- X774270 F2B PACKAGERXL Require to ignore space in Pattern setting to prevent duplicated Refdes.' d2 \0 Y* |3 p$ ~
799984 ALLEGRO_EDITOR INTERACTIV Enhance the Fix command to select just cline segs
4 z, z9 I* K3 v: f809008 CAPTURE SCHEMATIC_EDITOR New nodes get appeared within the design when we select the design and do "Mirror Horizontally".
. A# P* O. d7 {1 w8 B1 d# b2 n810058 CAPTURE SCHEMATIC_EDITOR New nodes get appeared within the design when we select the design and do "Mirror Horizontally".
; h# p* I- [' a0 a* a821133 ALLEGRO_EDITOR MANUFACT Output artwork for pad data that are suppressed unconnected pads with Gerber 6x00 format8 f6 J2 o; W$ _1 {/ ^
831710 CAPTURE SCHEMATIC_EDITOR Capture adds extra junctions to design by itself
K- x: b# w4 Q0 d; I. w6 T3 H" p$ p, `5 a842410 ALLEGRO_EDITOR EDIT_ETCH Ability to slide with "Shove" for "Same Net" segments/vias.& ~% @5 E/ n1 g& C
854971 ALLEGRO_EDITOR INTERACTIV Capability to add cline segment in a temp group" q! S" |& A! v5 e# B
860772 ADW PCBCACHE Save Shopping Cart (pcbcache) is crashing component browser# d& u+ E1 x4 I% x
867842 CAPTURE PROJECT_MANAGER Capture crash with 'Open File Location"
2 J- s+ K$ C- @; ]/ k" L5 `+ v* v868306 CAPTURE CONNECTIVITY mirror vertically removes junction creates extra nets
6 t5 I. |* ~" q! d5 _; q4 \882677 EMI RULE_CHECK bypass_plane_split fail if BYPASS_XXXX_EFFECT_DISTANCE2 h* G/ l0 L7 Z9 |: _0 d- H2 @) e
891439 ALLEGRO_EDITOR INTERACTIV moving cline segments
$ V+ C0 }" ]& G8 u- p% i# m! f893544 ALLEGRO_EDITOR INTERFACES IPC-D-356A netlist issue with BB vias.
M0 v2 m5 N! C6 [$ v+ z893765 ALLEGRO_EDITOR PARTITION Mail command not sending out email on Linux platforms.
# @; Q& ?, r. }0 R8 C, L894390 SIP_LAYOUT EXPORT_DATA Generate all balls in the xml file for export to EDI's readPackage command
# s5 \, l6 s$ u( _5 _+ \( ^% h895933 APD DATABASE Update Symbol shifts the center of the Dynamic Fillet and creating DRCs- l/ ~1 N' ?: D3 t Z
896598 ALLEGRO_EDITOR PLACEMENT error message is misleading, U" q: ~: }8 f. k" C, g/ Q! H
897196 CIS LINK_DATABASE_PA Schematic Contents are not shown in CIS window while link Dbase part for parts placed from library) y+ p& W7 l* s6 W
898598 ALLEGRO_EDITOR MENTOR Negative planes from Mentor Board Station not being translated.
* X" F Q/ |# v/ S5 B899556 ALLEGRO_EDITOR ARTWORK Import artwork seems not to work correctly.
- R0 y; B" V4 Q- g/ }8 D900501 ALLEGRO_EDITOR PLACEMENT "lace Replicate Apply" is showing lot of DRC's during placement of replicated circuit in 16.5; {; f& m2 S% D5 s" n3 Q7 [
901141 CIS EXPLORER Japanese character appear garbled in CIS explorer window.
/ W! Z7 v8 Q2 U- i; r! o' Z; _901666 CAPTURE OTHER Home page of Flowcad-Switzerland and Flowcal-Poland is not preserved on captre restart on start page
) E8 x+ \& j5 K$ e6 M902066 ALLEGRO_EDITOR DRC_CONSTR Shape in Region not follow the constrains
5 F k" w1 O! u902349 CAPTURE LIBRARY Capture crashes while closing library, u8 X* |& \) E' x7 M
902508 F2B PACKAGERXL SPB16.5 Packager-XL consumes much more memory than 16.3, p7 \: `, ?2 j4 i
902841 CAPTURE GENERAL Capture Start page does not show
0 G# G& X& G4 X2 O" O& c902876 F2B PACKAGERXL Packager fails on the design upreved in 16.57 `3 V% w" |, J6 P
902959 CONCEPT_HDL HDLDIRECT HDLDirect Error while saving design
( I, u. K/ x$ A' k; z903171 PSPICE NETLISTER Why Capture is treating hierarchical power ports as floting nets in complex heirarchy designs?6 J7 Z- K$ Q1 r2 \+ ?. p* M1 a
903713 ALLEGRO_EDITOR PARTITION Placement Replication do not work fine in the Design Partition
0 x+ |2 ^6 E% K" Q, }903799 SIP_LAYOUT DIE_EDITOR Disappear die pins after exiting co-design die editor5 _8 a2 N3 t; ?
904021 ALLEGRO_EDITOR OTHER Export PDF from SPB 16.5 produces a file not text searchable& {: \$ v' b! D7 M& d0 I. T0 p
904339 CONCEPT_HDL CORE new design crashes using the attached CDS_SITE
2 X- h5 O! b' W2 t2 m& W904522 F2B PACKAGERXL Part will not package in 16.5 but packages in 16.38 Q, o4 {$ F! H5 X/ b( C& h
904764 APD OTHER Enhance Scale Factor of Stream Out to support 4 decimal places
! X% Z- |: C, W1 t1 q904771 ALLEGRO_EDITOR MANUFACT Pin Number display issue.; {, m& h8 ?0 p+ g- h: v t
904853 ALLEGRO_EDITOR GRAPHICS Enhancement for showing Static shape as it was seen in 16.3; ]4 _# }6 \, D- H
905144 CONSTRAINT_MGR ECS_APPLY Min Line Spacing is larger than Primary or Neck Gap less(-) Tolerance but No Warning in CM. _, [+ Z* @4 w$ n! S$ B& Y) Z7 m
905314 F2B PACKAGERXL Import physical causes csb corruption
5 O* ^. h4 t4 K905337 CONCEPT_HDL CORE ConceptHDL crashes after Import Design process.8 N/ h0 ]' y) t5 A/ t, B5 R
905533 ALLEGRO_EDITOR INTERACTIV Pin numbers for components on BOTTOM Side are moved in Preselect mode,when the BOTTOM layer is invisible; d$ O+ ]) K3 P3 ?. Q; r2 X
905796 CONCEPT_HDL CONSTRAINT_MGR Fujitsu CM issue inaccurate concept2cm diff pair issues6 i; [) [- D n* T0 V) s2 T
905811 CAPTURE EE_INTERSHEET_RE interesheet references in the form of grid grid page number instead of page number grid
0 Y( c1 w. k; w- o1 I) C) ?1 [% r906118 CONCEPT_HDL CONSTRAINT_MGR Cannot open CM if SIGNAL_MODEL value was not assigned in ptf. T* ]9 M7 ~% _$ \
906153 ALLEGRO_EDITOR SCRIPTS Unable to run allegro script in batch mode on the attached board.5 U" g6 ` t7 f4 {
906182 APD EXPORT_DATA Modify Board Level Component Output format
. ?0 H2 m/ P2 K7 T& _6 B2 [4 C906200 ALLEGRO_EDITOR DFA Enh- DFA drc invoked in Batch mode returns false constraint value in Show Element
& }8 p+ {. ?; W906517 PSPICE PROBE PSpice new cursor window shows incorrect result.9 ~5 K# C4 C3 N+ Q# A
906627 ADW COMPONENT_BROWSE ppt options are not read if ucb is launched from FM. works fine if launched from dehdl.0 K9 \6 x$ D# a, J# x
906647 SIG_INTEGRITY LIBRARY lib_dist creates a signoise.log in current directory (with backup files like ,1 ,2 etc.) on each run
; z& n6 J$ j1 e; _0 p906673 F2B PACKAGERXL Ignore the signal model validity check during packaging& C% d: n4 G1 C: @/ y/ o1 L
906688 ADW LRM A copy of source design gets created in worklib of target design after 'Import Design'$ _) z4 W; P2 a4 t. y
906750 ALLEGRO_EDITOR PARTITION Importing design partition removes the testpoint reference designation
1 b `1 B+ g5 V* R9 M: z n0 j906874 PSPICE NETLISTER Error less than 2 connections for unconnected hierarchical pin: A- O c; @! f
907095 F2B OTHER Part Manager does not show Error as Undefined when directive ptf_mismatch_exclude_inj_prop is used
! L' r n3 ~) [# q" f9 j907424 ALLEGRO_EDITOR GRAPHICS Allegro add option for pre 16.5 shape display( O4 n& ?( ~1 F% N# P1 v6 k) b
907490 CAPTURE NETLIST_LAYOUT 16.5 Layout netlist is not correct. It differs form 16.3 layout netlist.% u# f1 b* i( Y1 T
907884 SIP_LAYOUT MANUFACTURING Need to add an "NC" pin text option for "Manufacturing Documentation Display Pin Text"1 [; A" ^) U2 \
907885 SIG_INTEGRITY OTHER Matchgroup targets lost when importing netlist to Allegro layout in HF31
3 W4 z% j( F" f907929 CAPTURE TCL_SAMPLE TCL command to delete a property from parts in a library is not working correctly
0 h. ?! C& _/ E- C! n8 n! q6 s8 D907933 SIG_INTEGRITY OTHER Single line impedence not working in OrCad PCB Professional
/ Y% ~+ O9 b4 K3 B3 H1 [ K& ]907963 CONCEPT_HDL CORE Design uprev issue when moving from 16.2 to 16.5
+ S$ K! C8 l0 V0 q* z1 ^1 F908000 SIG_INTEGRITY OTHER Inconsistence z-axis delay reported on Tpoint when define at via location.
9 B9 O/ u4 D/ a908057 CONCEPT_HDL CORE DE HDL crash with the cut and paste of a signal name) h, R3 U8 [# a' \/ Z1 L+ D, P1 u
908060 CONCEPT_HDL CORE CTRL+LMB Option not working correctly in 16.3+ c' E: K, M9 V
908210 CAPTURE CONNECTIVITY Connection is being lost while dragging a component
8 w; C4 n$ Y/ p# c908241 CAPTURE DRC DRC error column is blank in DRC markers window in 16.5
; F" n. e* H; [. y908339 RF_PCB BE_IFF_IMPORT mechanical holes VIAFC are not at the right place
8 N- r+ _6 @4 i! Q, u, a h% ?% b908534 SIP_LAYOUT SYMB_EDIT_APPMOD issues with symbol editor and copying pin arrays4 l! J; v' q, [+ S' l6 r
908535 F2B DESIGNVARI When I try to view my variant file the variant editor crashes3 c) [9 R1 M+ ?4 x/ R+ F
908595 APD 3D_VIEWER cadence Design 3D viewer" screen pops up and is all black because the colors have all converted to b' J* F8 A2 {7 G; b# m
908849 CAPTURE ANNOTATE Getting crash while annotating the attached design) S* x& T; V) H/ E+ V, \
908874 CONCEPT_HDL CORE Part Manager - No Part Found error when using CCR# 775788 feature1 `* z) `+ ?$ {- n+ K/ z" q$ h
909077 CONCEPT_HDL CORE After packaging pin numbers remains invisible even when $PN: N6 ^8 r( w h M7 }6 Q& V
909104 ALLEGRO_EDITOR SYMBOL Warning message needs to be modified. It does not save the symbol and also not tell the actual problem.
1 U( l2 x( i! y3 M909417 ALLEGRO_EDITOR REPORTS "report -v upc" returns 'Segmentation fault' on Linux' l ?1 D0 b5 F( {( L6 K' p
909635 SIP_LAYOUT DIE_STACK_EDITOR Add Interposer crashes in SiP Layout/ E. N1 X1 d) p7 c
909749 ALLEGRO_EDITOR MANUFACT Allegro Crash during dimensioning4 y% b, k6 V9 Q% t% I- N
909760 SIP_LAYOUT MANUFACTURING Create bond finger solder mask doesn't follow the mask opening as defined in the padstack
+ e( ?; s2 {$ c5 W* Z' g7 k+ V7 G909861 F2B PACKAGERXL NetAssembler broken within the latest 16.30.031
7 y4 W3 Q. r U( q910006 CONCEPT_HDL INFRA Motorola design fails to uprev from 16.3 to 16.5, xcon file is getting corrupted.
7 u2 [' e+ x* r, p4 W- f910141 CAPTURE NETGROUPS Modify NetGroup definition does not update Offpage Connector' |% u0 t$ g1 N+ P
910340 ADW LRM Import design in schematic, only 1 page import, the entire block is getting imported.4 T' H7 Y, g& d
910678 SIG_INTEGRITY OTHER The Analyze> Model Assignment> Auto setup is not creating/assigning models to discrete components in 16.59 k9 @# V4 l+ P& R5 {/ l' l9 Q
910713 F2B DESIGNVARI Variant Editor crashes when you click web link under Physical Part Filter window.
7 h: z" q D- E% |0 Z910936 F2B PACKAGERXL ConceptHDL subdesign net name is inconsistent' X9 Q/ x/ |( q ~5 ^6 F* i
911530 ALLEGRO_EDITOR SYMBOL Package Symbol Wizard does not create symbol with the name given# Z! d$ C4 c9 l) N$ I; F
911631 CONCEPT_HDL CORE DEHDL crashes when opening a design& M6 q! _5 a+ M* }9 U } e
912001 ALLEGRO_EDITOR OTHER option_licenses entries are made in allegro.ini even when not set as default' v# d7 `+ S2 E
912459 F2B BOM BOMHDL crashes before getting to a menu
# f* f9 |# h7 t H9 n3 m913359 APD MANUFACTURING Package Report shows incorrect data$ S, s" O7 @* g( A4 _' A
( w3 P7 U1 a: S6 V/ @
DATE: 06-24-2011 HOTFIX VERSION: 001
: S* g' P9 i. E) C===================================================================================================================================
: w- ?7 e- g, g9 S" K% M) ECCRID PRODUCT PRODUCTLEVEL2 TITLE
y& X- Y. C( Z" Z( I8 k( z===================================================================================================================================8 ]8 K; ?7 v! T5 x- I/ H9 t4 s
293005 ALLEGRO_EDITOR DATABASE Allegro crash when attempting to move mech. symbol
) }4 ?: ?1 Y0 H298289 CIS EXPLORER CIS querry gives wrong results, u6 Z% O* r1 \9 I1 F; O* e. D
366939 ALLEGRO_EDITOR OTHER Cannot attach refdes on silk subclass with add text0 p! S2 o, z1 E1 Y ~7 R
432200 ALLEGRO_EDITOR MANUFACT Fillets with an arc are required for Flexi designs
. a0 b" p% g5 D. u. Z443447 APD SHAPE Shapes not following the acute angle trim control setting.
: Q* }# _6 h/ F1 G473308 PSPICE AA_SENS Passing variables to lower level blocks using subparam! a5 ]% W8 O) U& q9 H% y
517556 PSPICE AA_SENS Advanced Analysis does not support variables being passed down the hierarchy% ~* e8 L8 n- E% @7 L. z$ F/ |1 t
548143 ALLEGRO_EDITOR SHAPE Dynamic shpe on Etch TOP will not void properly.$ l- Q- r6 U8 h I2 Z
606959 ADW COMPONENT_BROWSE Key properties with blank values are not getting read in shooping cart
7 W2 e2 F. F3 ~: _( K0 l: x616466 ALLEGRO_EDITOR SHAPE Solid shapes are not getting filled, }8 `$ D9 ^, n- F+ n
641358 SIP_LAYOUT DIE_STACK_EDITOR Request for Via and Multi Layer Pin support for DIE stack Area (blue region)7 f; M. w! z5 _! Y$ w) E$ f
644122 SIP_LAYOUT OTHER SiP Layout - xsection - ERROR Adjacent conductive layers are not allowed, but these are diestack layers not conductor$ V: a+ c$ {: b* V) P) g" r: O
645816 ALLEGRO_EDITOR SHAPE Slide a cline all removes gnd shapes on board
; k- v: |8 G) o( m$ |725355 ALLEGRO_EDITOR SHAPE User can not voided Logo correctly.8 I X8 l. N: y' P. A
763569 CONCEPT_HDL CORE Display status of Hide/Show unconnected pins icon in DE HDL UI4 c) ], G+ @# J1 a1 k9 U9 Y* j
770021 CAPTURE BACKANNOTATE Changing pin group property after pin swap resets pin numbers
. g, \ `9 R8 |' s. n9 X792126 CAPTURE PROPERTY_EDITOR Attempt to change display for occ prop resets
1 [8 @8 o+ p/ N799014 CONCEPT_HDL CONSTRAINT_MGR concept2cm errors not shown in export physical after hier_write
7 Y/ S' y: t! m/ o4 x803147 CIS LINK_DATABASE_PA Link DB part should not change RefDes of multi package part
& i9 b8 d1 I' G g& J804240 PSPICE DEHDL Problem in simulation result for a multi-section split part.. ^% B; t% W4 [2 i0 I
809118 CAPTURE NETLISTS ENH to compare two schematic Capture designs
+ Q& h, y! ^/ d! F/ `1 c816568 ALLEGRO_EDITOR SHAPE shape disappears when update to smooth.. State no etch
. J% j; k( `7 S% v C x830053 CAPTURE STABILITY DXF export fails if schematic folder name as /
- H6 M# ~2 H/ _& y832108 ALLEGRO_EDITOR SHAPE Shape void incorrectly.0 b4 f5 }* Y: h0 h, d8 r9 O+ h& N
833542 CONCEPT_HDL CORE PDF publisher font is NOT WYSIWIG with respect to what seen in DE HDL- _ y; o; g3 ^+ _% h5 R/ s
835777 CIS DERIVE_NEW_DB_PA For XLS, donot display table as worksheetName$worksheetName to avoid 8012 error
9 h$ T4 h. J2 _. f837640 CIS GEN_BOM date format of CIS BOM has broken macros of 16.2 in 16.3 version6 s# z" ^" x2 S4 A- @& C
844074 APD SPECCTRA_IF Export Router fails with memory errors.
. B3 c( \- n% ?4 R' z- g851595 CONCEPT_HDL CORE Pin numbers overlap on the pin and increase in size
) k$ N4 V5 \1 E/ m; m852832 CAPTURE BACKANNOTATE Why is Capture crashing with Mentor back annotation?! r- _ T, U& I& Q2 q
855015 ALLEGRO_EDITOR OTHER The rats are NOT connecting to the ends of the clines like they should be.
G8 L9 X: [ O- \859883 CAPTURE NETLISTS ENH to compare two schematic Capture designs
. Q2 w2 f( j- b" h8 I* F/ m( A4 W4 z4 t: b866009 SIG_INTEGRITY OTHER Net with Pull-up/down should not be used for Diff-pair.' _$ S h7 R# k; n8 U
866830 SCM REPORTS Multiple lines added as separator between title block and report header instead of single line. b+ B6 _- T' K4 W( b$ Y: A- M
866833 SCM REPORTS Extra indentation is left in the left side of the report when the Line Numbers are set to OFF' z0 B9 G) I0 D" C1 I' u
868618 SCM IMPORTS Block re-import does not update the docsch and sch view. }- \4 J$ [1 k$ T$ F7 H" S
873402 SIP_LAYOUT LOGIC pin swap for co-design die in SiP
& K0 `! q, Z, ~3 o874010 SIG_INTEGRITY OTHER PCB SI crashes when the Xnet is extracted with VARIANT_TO_IGNORE property.. Y0 [$ s$ r" x( ~' e( ]& U! G
874400 ALLEGRO_EDITOR INTERACTIV Flip mode issue with move command) U4 i4 d0 N1 i6 t8 z0 {
874966 ALLEGRO_EDITOR INTERFACES Placed mechanical component do not get Ref Des or part number in IDF file" ^- j- @7 G+ d" N0 g
875709 ALLEGRO_EDITOR REPORTS Film area report generated incorrect data at l1
) I$ u" m7 Z: l- ~876275 CONCEPT_HDL CONSTRAINT_MGR Constraint Manager not retaining target net
6 l4 j3 ^" ^! Z( @7 p4 E, ^879361 SCM UI SCM crashes when opening project5 h7 s4 Y( Z8 R, k: ?
879496 CONCEPT_HDL OTHER Customer wants to have the tabulation� key as separator in HDL BOM.
7 }! U- W4 S$ X1 H3 m879514 PSPICE AA_MC Monte Carlo to handle equation as comp VALUE. l" N2 W" Y# v2 |7 I
881845 ALLEGRO_EDITOR SHAPE Delete island deletes complete shape
4 k' n# ^: Z _, R882413 PDN_ANALYSIS PCB_PI PDN Analysis should support routed power nets% Y7 w; Y3 ]6 H& m
882427 PDN_ANALYSIS PCB_PI PDN Analysis target impedance should have a variable multiplier
: ~% i7 y1 v6 e7 A U* H* D882567 SIG_INTEGRITY OTHER PCB SI crash if boolean type prop was specified to VARIANT env.
- A) m6 u/ F/ H* g882644 ALLEGRO_EDITOR PLACEMENT PCB Place Replicate Function automatically match Enhancement
: Z0 i7 O$ O7 S% ]! l( r# m883164 ALLEGRO_EDITOR INTERACTIV Vias marked fanout moves away from position when moving component6 |& P" S0 O; X) ~, [
883224 SIG_INTEGRITY SIMULATION crash while reflection simulation from Constraint Manager
2 y6 p7 j7 R5 L9 B% G883760 PCB_LIBRARIAN METADATA Incorrectly formatted revision.dat file in the metadata folder1 V6 d; E' p" v3 x
885391 SIG_INTEGRITY SIMULATION RLGC data sampling algorithm and w-element interpolation.
2 u2 D# N5 _% r' z+ G9 f4 x885849 ALLEGRO_EDITOR MANUFACT Silkscreen Audit cannot find Solder mask for the text string
6 l' V9 I5 s2 X$ |% W885996 SIG_INTEGRITY OTHER The effect of sn_maxwidthlimit user preference is not seen in cross section impedance calculations
% R' j+ S- b$ _4 M& W9 X886090 ALLEGRO_EDITOR INTERACTIV Add Arc w/Radius does not snap to grid: ?0 Y0 ^$ O# n( M5 z
887180 CAPTURE SCHEMATIC_EDITOR Signals Navigation window doesnt get updated for Buses
4 v: }- y6 C/ [! Q1 i887442 APD SHAPE Copper pour of Dynamic shapes on Top layer which contains many existing signal traces fails.
0 t& I, d; m8 d' I& i* o887578 SCM AUTO_UI Component Replace pops-up the DSPANE-204 Message
- d% o# W# k* y: n/ P' p887926 SIG_INTEGRITY GEOMETRY_EXTRACT Field solution failed if diff trace on bottom doesn't have reference plane.
U" {/ Z6 ^' o. I- ?2 N888414 SIG_EXPLORER OTHER View Trace Parameter display the thickness of dielectric incorrectly.3 D6 @3 u6 B( F* |
888600 CONCEPT_HDL CREFER Cross References not added to Schegen schematic, Q7 w' G9 X, q: K" U1 k* K5 s
888679 SIP_LAYOUT SHAPE Can't create the Dynamic shape on layer M1_sig without unwanted horizontal openings appearing.! v6 _ j) Z" E2 l' w
888804 ALLEGRO_EDITOR OTHER Fillet will become static shape after import from partition board.
/ g+ o1 H2 @) d+ U1 M; U4 _888945 CONCEPT_HDL OTHER unplaced component after placing module
/ f( G ]5 H& L1 \ q889222 ALLEGRO_EDITOR SHAPE Allegro freezes/hangs when adding shape as Polygon with OpenGL ON.
7 d: M" \/ T( _& C$ N# I! l+ A889365 SIG_INTEGRITY GEOMETRY_EXTRACT top/bottom trace impedances extracted to sigxp are wrong in 16.3
/ ]3 @6 e+ r4 r889404 ALLEGRO_EDITOR OTHER Incorrect pad size for Top conductor padstack written to column 59-62.7 X# {& ]: S: Q, A6 G8 ~
889426 CONCEPT_HDL CHECKPLUS CheckPlus does not find single node net9 ^4 C/ h+ m( M3 z9 K4 x, A
889636 ALLEGRO_EDITOR MANUFACT Incorrect spelling of "Visibility" in "Film Control" tab in the Artwork Control Form
9 v2 i( [+ d) s) `& r891235 F2B PACKAGERXL Packager crashes without creating a pxl.log file
. { o- i0 \4 R& L9 p3 E891292 ALLEGRO_EDITOR SHAPE arc routing causes weird undesireable shape fill performance
2 @% p0 C, P: Q! _. c0 u( _891856 ALLEGRO_EDITOR EDIT_ETCH crash when sliding diff pairs# z1 `8 ]" U3 e3 ^ ^4 v
892375 ALLEGRO_EDITOR PLACEMENT Place Replicate Update disband other groups, irrespective Fixed property added or not.
: T7 ?) ^' [ g892455 ALLEGRO_EDITOR SYMBOL Why the overlapping pins are not reported with DRC?: Z9 A4 @( B. }$ j5 O
892541 SIG_EXPLORER OTHER Export/Import layerstack through the technology file is changing the layer thickness
) `/ _4 k+ R; w# H" \: d( {892766 APD WIREBOND Excuting Finger moving cannot push aside finger to move with together by shove all mode) g3 F; y7 |& L. @3 C8 F: O& ]
892907 ALLEGRO_EDITOR DRC_CONSTR DRC not reported for etch_turn_under_pin violations) o9 [$ I+ N- m9 ~' }4 h% h _
892963 ALLEGRO_EDITOR SKILL Bad shape boundary created after axlPolyOperation 'OR" |1 R' T; g$ D; q$ l
892964 SIP_LAYOUT LOGIC Request that Edit Parts List use Dashes "-".! ^" o& ~( S6 u1 `
893295 APD WIREBOND Why move wirebond command does not shove wirebonds? This result in drcs.
& a0 K. x2 R0 _% c# S893706 CONSTRAINT_MGR OTHER On line DRC hangs on partitioned board
* E" V) \9 \' T" G/ ^893743 APD EDIT_ETCH Route behavior when spanning pads not as expected.
# K% V* ~$ ]3 ^9 g% o# J) O893783 SIP_LAYOUT OTHER Padstack Design Editing update File menu with a Update to Design and Close instead of 2 operation9 O* t3 w% t2 y$ U% y" z
894456 ALLEGRO_EDITOR REPORTS Request Net names be added to Propagation delay lines of the DRC report.$ ^0 J( Y* f8 g" N X2 X
894499 SIG_INTEGRITY LIBRARY Tool crashes when moving a cline or selecting the Info icon with OpenGL on.# R$ t: {: }# h( ^
894582 APD SHAPE When making a dynamic xhatch Via shapes surrounding are abnormal.
7 D5 Q7 H7 ~4 d! @1 W% G' I895542 SIP_LAYOUT WIREBOND SIP design crashing when moving bond finger using blur mode BLUR_BONDFINGER_PRESRV_CON
) @ U2 g$ i5 G- Q4 _$ {/ |895591 ALLEGRO_EDITOR PCAD_IN Importing PCAD file fails to get to the point where we can map layers
8 Q8 ^9 u% a9 X" l: Q2 h# ?895757 APD ARTWORK Import Gerber command could not be imported Gerber data8 W7 I6 ]0 T! a0 h
895964 CONCEPT_HDL CHECKPLUS The CheckPlus command getFileSubstrings is not working correctly
- w) }: n: @3 S: @896428 SCM UI Changed Ref Des value not maintained in DEHDL block when part is replaced2 i& _% U0 K- f9 j
896655 CAPTURE EDIF Import/Export Design of Hierarcy design with OrCAD Capture
: v/ Q( {) s0 a( X" B2 ]. k+ T896846 CAPTURE IMPORT/EXPORT Import edif2cap and capture is crashing
" b& ~ F9 k2 v897155 ALLEGRO_EDITOR REPORTS Copper coverage in L2 and L7 looks like the same but film area report had large gap.
. u3 d% m& Z7 ^8 {" N897654 CAPTURE EE_INTERSHEET_RE Capture crashes on adding intersheet refernces in abbreviated format on attached design.
* w R# ?0 R# j/ K: ^2 E% z8 H# ^( f899344 RF_PCB BE_IFF_EXPORT dlibx2iff does not provide the component boundary drawing
8 H1 D* N/ D% R9 f4 B$ R899629 CONSTRAINT_MGR OTHER ECset for Total Etch Lenght is not present in OrCAD Prof
' X4 O' W1 z$ ?( [900175 CONCEPT_HDL CONSTRAINT_MGR Few Xnets are lost from Match Group after packaging and importing the netlist to board file.
9 [1 u; s! ^6 }; B2 ~( c2 |* I1 R900481 CONCEPT_HDL CORE Genview creates a larger symbol without taking the no. of pin in consideration
3 [8 Z1 m, r8 u$ D& Y900813 ALLEGRO_EDITOR DRC_CONSTR With rotated pads, pad (pin - via) soldermask spacing DRC is unreasonable. u8 g4 c. m& d2 E6 I
900905 PSPICE STABILITY Simsrvr crash and RPC Server unavailable error while running simulation.1 E5 K, U( y2 T8 r% S& c
901783 CONCEPT_HDL CORE CDS_PART_NAME is annotated on the schematic canvas after running back annotation in 16.59 V% @6 a, A4 L4 H
901909 APD EXPORT_DATA The "package_pin_delay_length.rpt" with Z-axis delay turned on seems wrong- V0 ]: l4 Y: J0 y8 ` H p
901987 CONCEPT_HDL OTHER SPB16.5 zoom fit does not center the page while ploting the schematic page: P7 i$ Q: q# ]0 x( Y1 E
902133 CIS OTHER The visible part property value are being shown very distant from part graphics on schematic7 b) i7 g- S: D% l8 J" [' j$ [
902166 SPECCTRA ROUTE Specctra crashes when reading in "bestsave.w" file5 c) m# X, w ~+ R2 R. p9 Q) M- o
902170 ALLEGRO_EDITOR DATABASE Diffpair Issues with OrCad PCB Designer Professional
8 R4 W* A$ v/ B D' ]902177 CONSTRAINT_MGR CONCEPT_HDL Option to view the layer thickness in CM worksheet through worksheet customization. j$ p7 [) n0 C6 J0 L+ J6 o1 o+ D$ r
902463 ALLEGRO_EDITOR INTERACTIV APD crashes when we click ( show element ) on certain components3 ]4 Q9 T% k$ t, J5 R& Y7 o
902621 CONCEPT_HDL OTHER Design Differences (vdd) Crashes% {$ k# Q% c* n" g
902909 APD WIREBOND die to die wirebond crash
9 C; r+ |5 I: t6 j- S {; k; B902933 ALLEGRO_EDITOR PADS_IN Pads_in fails while reading PADS ASCII file body! z# z' N) n3 c/ F) j3 q5 X
903284 PDN_ANALYSIS PCB_STATICIRDROP IRDrop voltage gradients are plotted outside of the PCB outline
3 \ [! o3 Y' P: i0 e! i3 W5 a903680 CONSTRAINT_MGR ECS_APPLY Constraint Manager not passing all hiearchical member objects to a custom measurement.
( l4 P' |/ F ]2 ^" {+ ]904403 ALLEGRO_EDITOR DATABASE Allegro crashes when refreshing module |
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发表于 2012-2-21 14:58
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