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DATE: 02-17-2012 HOTFIX VERSION: 016' ~2 `: n2 ~* n+ {8 v) A U! P
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. ]- e+ Z7 W& |7 L840105 PCB_LIBRARIAN USABILITY PTF subtype is getting changed when Save As option is used in PDV
9 E3 @1 y6 y6 w( A6 H: V873075 Pspice PROBE Decibel of FFT results are incorrect.
s6 a- g( G; _" O# x, M938744 ADW COMPONENT_BROWSE Need ability to customize shopping cart columns to include any Part property# a. H* ]) L+ E- W0 t& L/ ~
943003 SCM REPORTS The dsreportgen command fails with network located project5 b' o) Z+ t; A- _% f- d
961530 allegro_EDITOR INTERACTIV The problem of Display measure command
" D' R/ a; N; J$ S- j" x& A962157 concept_HDL CORE Where is the setting for enabling the Enable PSpice Simulator menu?
8 R$ @ }- o7 B5 q' F4 o5 v6 X962206 CONSTRAINT_MGR CONCEPT_HDL Import physical not passing all constraints from the board to frontend4 J0 l2 T0 p% p# P% y
968205 PSPICE DEHDL_NETLISTER Change SPLIT_INST property to PSICE_SPLIT_INST for Quad Switch type of design.
: G1 K( x& R* Y+ u, z4 ]968509 PCB_LIBRARIAN METADATA Incorrect pinlist.txt was generated if DIFF_PAIR_PINS_POS/NEG was set.
) `7 `0 }/ I$ g; P. K7 ^969450 LAYOUT TRANSLATORS orcad Layout to Allegro Translator crashes v& ^6 [" |! z* ~) l; J: E
969997 CONSTRAINT_MGR CONCEPT_HDL ERROR(SPCOPK-1053): Cannot find a ppt part that matches the instance pro~
0 M$ t. ]1 m D* P0 @- ]0 r7 F971193 CONSTRAINT_MGR UI_FORMS Copy and pasting a formula causes the application to crash on windows.
% B+ i3 B+ V- k* v' ~" i971601 CONSTRAINT_MGR CONCEPT_HDL ERROR(SPCOPK-1053) and WARNING(SPCODD-66) because of directory structure+ s# y! y1 o. _$ r) v( f+ @* i( r
973398 CONCEPT_HDL OTHER It should be not packaged with error while working the packaging process if the design has a ERROR
6 N5 p. \, E3 X' U2 s ^! J) a973859 PSPICE ENCRYPTION Pspice crashes with encrypted model& i2 w: \4 n/ z$ i, B
973938 PCB_LIBRARIAN VERIFICATION pc.db is missing0 ?$ ]* O4 y- C# R1 N" g
974540 CONCEPT_HDL CORE Graphics updates are real slow
4 l9 m' q: Q( B$ \974791 F2B DESIGNVARI Variants are not back-annotating to schematic and turning to ?
" o$ r7 D3 Y( a# ]. }974818 ALLEGRO_EDITOR NC Backdrilling produces 0 plunges yet no errors reported.
% c7 q; c. L$ s0 B. B$ Q" B- d7 J974945 ALLEGRO_EDITOR skill Why is axlPolyOperation is giving different result and not working' x% _3 d% ]9 O3 m; e+ s
974946 MODEL_INTEGRIT TRANSLATION ibis2signoise returns the error - Delay measurement fixture must contain V for ECL technology3 L5 z d$ h/ O; ^9 f
975396 CONCEPT_HDL CONSTRAINT_MGR Constraints are dropped after migrating from 16.3 to 16.52 X) p' N* y2 v J. x4 ^
975633 ALLEGRO_EDITOR GRAPHICS 'dynamic_layer_visibility' option in 3D Viewer when checked or unchecked should not change (until next change)' V/ {! x% y* X* ~( N, d
975720 ALLEGRO_EDITOR DRAFTING Datum dimension lines not adjusting to text move$ u, A8 C! n" {& v* F! `0 m
975745 ALLEGRO_EDITOR SKILL cdsServIpc different 16.2 vs 16.5 when Allegro exits
; G5 z4 T8 Y, Q% q3 \% q& S& a7 t976013 CONCEPT_HDL INFRA Power pin connection of FPGA symbol is missing in netlist.
- l; q* G9 H( @& Q4 {* x+ U976058 CONCEPT_HDL COPY_PROJECT SCM Copy project does not create the con and dcf files in tbl_1 views
( K3 x$ X7 i1 m9 O" ]$ ]976073 CONCEPT_HDL COPY_PROJECT All the constraint data is lost in the SCM copied design
5 [9 R7 F T: L6 E0 p3 k" _4 l, E, Z976160 CONCEPT_HDL CREFER Cref fails due to some Caeviews error in the design; C( `6 Q: o- P. P4 ~5 X4 h
976204 ALLEGRO_EDITOR DRC_CONSTR Application falsely reporting Mechanical Pin Antipad to Shape Spacing DRC$ F+ X3 ~ r: h0 z, j) b/ }: E
976448 F2B PACKAGERXL ERROR(SPCOPK-1069): Invalid POWER_GROUP property value9 Y, b- R/ I9 c( t" q* Y: K
976521 ALLEGRO_EDITOR DRC_CONSTR multi-thread update DRC causes the application to crash
0 {2 Y: L4 m- T/ B7 ~1 S976838 SIG_INTEGRITY OTHER Unable to create XNET for highlighted nets on attached database even after assigning proper Signal Models.; ^! `7 s* _# t
977517 F2B PACKAGERXL Export physical fails after update to 16.5 from 16.3( `( N# U# U$ w' c8 Y$ Y' ]! _
977902 ALLEGRO_EDITOR DATABASE generate module is crashing allegro2 G7 R) S# S( x0 h4 W0 A' }
978652 ALLEGRO_EDITOR pads_IN PADS_IN fails with ERROR: Finished with errors.
9 m# J( u1 ^+ i- b! E6 r978744 APD DEGASSING Some shapes will not DeGas on this design
8 k- h" u/ P8 k% e' O C7 @979940 SIP_LAYOUT OTHER SiP Layout Leadframe autobonding with profile selection8 [) g$ X4 p7 e( `, F) m o0 \ x
981699 CAPTURE HELP Start Page still shows Hotfix 14 after installing Hotfix 157 m) H, @" s9 }& g0 P' X2 ~
0 {; o- E3 a3 E7 _
DATE: 02-03-2012 HOTFIX VERSION: 015
7 W( S8 i* Q3 s* L# p===================================================================================================================================! _$ ]+ y; T; Z$ g7 s
CCRID PRODUCT PRODUCTLEVEL2 TITLE
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871567 CONSTRAINT_MGR SCHEM_FTB Ability to filter out Single Node Nets from Constraint Manager
9 A, O' o" L, o9 z921436 ALLEGRO_EDITOR MANUFACT Change in 'decimal place' for new dimension changes the already placed dimension6 `, h2 y0 K/ t# |' D8 N4 ^ ^
941433 CONCEPT_HDL COPY_PROJECT 16.5 Copy Project should warn if trying to copy a 16.3 design
( H0 }/ X6 \' i% L+ B. @/ E* }954375 ALLEGRO_EDITOR MANUFACT Change dimension accuracy for few instaces of associative dimensioning% O# y; t. y( a4 R
961646 PDN_ANALYSIS EMVIEWER EMViewer Help > About shows wrong version
! @4 X/ N1 p- _$ @964912 CONCEPT_HDL COPY_PROJECT ASA project crash after using copy project
. n" ?/ I( ]' J! \- S0 J967223 ALLEGRO_EDITOR MANUFACT Bug:Oval slots orientation in one direction only. H$ q* N6 I' H% v1 P R
968865 SIP_LAYOUT DIE_ABSTRACT_IF load of die abstract fails due to differences between component and symbol# z: `, ~; H( F6 y
969485 ALLEGRO_EDITOR SHAPE Shape does not update correctly in 16.5
" `0 _% i% Z+ ?" S0 C970331 CONSTRAINT_MGR ANALYSIS Impedance worksheet shows a zero value for impedance
4 Q. ^3 P8 I# ~0 j8 }- T* X/ w970600 SIP_LAYOUT SYMB_EDIT_APPMOD Option in Die Editor to be able to "physically swap" pins
' S7 h7 l$ L& v8 w970910 F2B PACKAGERXL Our customer has problem with pin color after pxl 16.5.9 Z3 Q1 j9 m9 z5 ?: L
970970 SPECCTRA FANOUT Fanout Vias is placed far away from decaps and does not change the Fanout length even when max_length is reduced.6 r( V& G9 l. Q# D
970985 SIP_LAYOUT OTHER Importing a .spd2 database file using NA2 will cause the APD/SiP tool crash. p4 Z4 ]/ W7 o) X1 m
971757 CONCEPT_HDL INFRA Crash while Saving/Packaging the Design1 L- E1 ]* q, D! g) S; }0 w
971923 ALLEGRO_EDITOR MANUFACT Allow to change decimal accuracy for dimension instances
6 T2 u5 {2 \9 l! \- z972568 CONSTRAINT_MGR UI_FORMS Tools >Excel missing from CM5 }: I6 C! B0 ]4 {* @/ W
972821 CONSTRAINT_MGR CONCEPT_HDL connectivity server warning: Unable to add property WEIGHT h/ ?* H V `' C3 O
973185 SCM CONSTRAINT_MGR ASA2 block not seeing all instances in a package.
$ b5 t" H+ {. R2 R5 Y973211 ALLEGRO_EDITOR INTERFACES IDX Object Type Change not recognized
! j! ^- J8 a7 W' ~( `973214 ALLEGRO_EDITOR INTERFACES IDX import package keepout height value change assigns incorrect value
) }6 w. u; q; q973384 CONCEPT_HDL CHECKPLUS The multiple SIG_NAME has to be occurred an ERROR at the SPB16.5.
/ f8 B8 W2 I' O0 E% d+ C0 u& M973514 SIG_INTEGRITY OTHER Mapping error when Ecset is updated to constraint manager from extracted net
/ R3 h0 W3 e; v5 A$ g8 L& Q973950 ALLEGRO_EDITOR SHAPE Update to smooth crashes application
+ e, | P3 l2 M. Y+ y6 E974533 SIP_LAYOUT OTHER Crashes in Edit > Die Properties and obviously has a setup problem.3 ^% c6 h1 J% w. r! p8 G
974809 ALLEGRO_EDITOR SKILL argument available for hiding a property with function axlDBCreatePropDictEntry is not working
# I4 ]; D% P" U* ~0 U# ?) v976179 INSTALLATION ISR Installation of ISR S014 to 16.5 on windows is breaking the documentation index0 R, _ E6 v) _3 c; v5 T
. H+ U3 @) S! E6 y; |2 b# y
DATE: 01-20-2012 HOTFIX VERSION: 014# H9 t5 A. K" [5 E
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/ e" i+ i1 U8 LCCRID PRODUCT PRODUCTLEVEL2 TITLE; V' h2 E e, E7 P7 ]" E
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733285 PSPICE SIMULATOR Enhancement:In server-client installation use existing index file from server
! r3 {" P/ d* D. Z+ X& J941020 SIP_LAYOUT OTHER Soldermask enhancement) V+ U0 n6 r' D3 V' ~9 d
946407 CONSTRAINT_MGR TDD When is it safe to open a 16.5 design in 16.3?
7 t8 u9 h9 H. Z Z953067 CONCEPT_HDL OTHER Variant Editor "Error/Warning messages" form is unusable
" a1 r+ _. F1 l954818 CONCEPT_HDL COMP_BROWSER Replace button turns to Add in component browser when a component replace is done on the schematic
* O0 T ^$ y& W: _6 b956450 ALLEGRO_EDITOR DRC_CONSTR Analysis always shows analysis failed in uncoupled length in some diffpairs
( c7 a4 V# v' |+ k8 n958259 F2B DESIGNSYNC ds.exe crashes on a big design when accessing the design from network drive
: Z8 C! ~/ G- s) F- m: S958395 ALLEGRO_EDITOR SHAPE shape voids won't merge
; [5 R7 p5 W1 B) |! \959212 MODEL_INTEGRIT PARSE Attempting to use "Mark qualified" option on DML File results in dmlcheck and Modelsim wanrings.
3 H3 }% }1 C& S) z4 K: K2 e* y959940 APD AUTOVOID Void all command gets result as no voids being generated.8 |" h( x! q% V' G+ I1 {6 V
960252 PCB_LIBRARIAN CORE Splash screen in PDV prevents showing error message
; m1 e+ c4 e8 h961634 PDN_ANALYSIS EMVIEWER Cannot launch PDN EMViewer from withing PCB SI" {! m* @$ {! h5 [' n
961645 PDN_ANALYSIS EMVIEWER Standalone EMViewer will crash when opening any result file in the form of *.emv file.3 @ G- T; {6 W3 ]
961700 ALLEGRO_EDITOR SHAPE dbdoctor reports ERROR(SPMHUT-144): Illegal arc specification
w0 i+ U9 o' h' g961733 ALLEGRO_EDITOR SKILL Allegro crashes. Appears to have a memory leak.) F1 g6 Q. Y9 p; ^3 H/ Q+ c6 ]! C. R
961758 ALLEGRO_EDITOR DRC_CONSTR DFA check produces no DRC when the dfa bounds are not a rectangle.
/ U8 P& q, l" q961887 CONCEPT_HDL CONSTRAINT_MGR Match Group created from ECSet cannot be deleted in the same session of CM
* V, N2 x' j2 y7 H5 M7 G8 t962552 APD EDIT_ETCH BUG:APD crashing when we try to slideget information but move works fine
{ l. r' x. c2 n962869 CAPTURE STABILITY Capture crashes after RMB click on rotated parallel wires. W; H+ @# R% r% k1 q+ e6 \
963232 CAPTURE MACRO Macros not being played in Windows7
7 T/ _2 j4 |% P* q: }5 V" G: U; Y" y963300 ALLEGRO_EDITOR DATABASE Create > Module crashes in 16.5 but not in 16.3
: j: X9 {7 C9 n963651 CONSTRAINT_MGR CONCEPT_HDL ECsets are renamed after packaging on linux4 y, b5 V* x/ |* S% R6 _
963663 CONSTRAINT_MGR ANALYSIS Q- Why the customized worsheet for Diff pair Impedance not analysing at all for this SIP design
0 L5 `* A D1 m+ \, W8 Q/ s963715 SIG_INTEGRITY OTHER Application only adds the bottom conductor thickness for the via z-axis length
* Z9 _5 g" {/ Z8 a3 C964068 ALLEGRO_EDITOR INTERACTIV Allegro crash when using move alt sym mirror alt sym...
# [+ G" d1 a$ ]8 D( |! p964267 CIS PART_MANAGER Capture become non-responsive, working on Part Manager and creating CIS BOM, for large designs/ ^( i) o" y0 L/ m$ U- e
964597 ADW LRM Issue of LRM license checkout after renewal license by 16.5 (ADW15.5_S23+SPB16.3)# B$ I7 w& `8 f- v3 L# v
966148 APD INTERFACES Character Limit for DIE Files (*.die) Import) e( F; w! `; i) P
966416 F2B PACKAGERXL Cannot package this design
* M$ S- Y4 f( g& \! Z* p' P( X+ T966421 CONCEPT_HDL CORE DEHDL Crash when applying property on components in duplicated blocks8 I( V/ X; B q" o! T7 J v5 X: w
966693 CONCEPT_HDL CORE DEHDL crashes when doing model assignment if CM is open
1 s- g) ?/ d, ^4 s966795 ADW ROLLBACK rollback utility does not honor -product option from command line
0 ~5 F* g0 K& Z967089 SIG_INTEGRITY OTHER Matchgroups created by ECSet not deleted when ECset is removed from object.% K1 e9 I4 H. x
967222 ALLEGRO_EDITOR OTHER PDF export is leaving data off the drawing
O ?* l6 Z) z% e V0 W967240 SIP_LAYOUT WIREBOND Change default bond fingers selected on multi-site leads during "bond to leads" program/ D @/ J$ J* S9 _, }- ]6 [2 C
967297 ALLEGRO_EDITOR OTHER Dynamic Fillet&Eliminate unused stacked vias cannot be used as the Miniaturization option.
7 d5 d: d# l. [967576 CONCEPT_HDL CREFER Occurrence location property values do not appear in flattened schematic generated by CreferHDL
8 N0 I, e; E7 y* x; \: U0 R/ w* d968096 ALLEGRO_EDITOR DRC_CONSTR Mechanical Pin to conductor spacing is not followed.% M0 P( B/ j4 _% `0 I
968222 SIP_LAYOUT DIE_EDITOR die pin loses IC net for a co-design die with multiple ports within IO-cell& J6 v7 s6 G: Y# { l
968358 CIS PART_MANAGER Capture crash on removing a part from subgroup in part manager
! v, ~# h8 q3 k' A; N9 E969594 CONCEPT_HDL CORE The dcf file is not updated with schematic changes$ u: [2 W" d- v! j9 |0 q
% e, H' [) M7 w) iDATE: 12-16-2011 HOTFIX VERSION: 013& ^6 ^# r" {8 m, t. L a" F! i
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CCRID PRODUCT PRODUCTLEVEL2 TITLE+ m. s+ m$ d- n) u6 Q* j1 h
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& J! m4 P1 N3 G0 x875695 SIG_EXPLORER INTERACTIV Enforce Causality check box doesn't work.! x0 G- }) o! y: U' f3 B$ g* `
927148 CAPTURE PROJECT_MANAGER Capture crashes on creating scehmatic folder with name which already exists in design2 k v2 V8 y( Z/ {9 d! j
938013 CAPTURE NETLIST_OTHER The netlist in RINF Format contained two identical lines for PCB FOOTPRINT6 T3 N; T% Y* }# n! \$ a
941409 PSPICE PROBE BUG : Search accuracy wrong in new cursor window
, g; r: [6 S1 Y, E" Z945242 SIG_INTEGRITY SIMULATION Unable to select "shapes" in find filter for 'show parasitic ' command
8 E4 i& [1 |; J9 i946293 CONCEPT_HDL ARCHIVER Archiver hangs if there is a whitespace at the end of the path of cref.dat
: F+ [) y( M! C( h$ H8 z7 E946770 CONCEPT_HDL CORE 揤iew Design� function is missing in Windows Mode after reseting the menus.- J+ ~) }- I8 ]" l* t
950994 CAPTURE NETGROUPS Problem in expanding the netgroup in Auto Connect to Bus function* @% |8 f4 ?' K6 h/ G/ k
953530 SIG_INTEGRITY GEOMETRY_EXTRACT Display Parasitics is displaying wrong results for EMS2D Field Solver compared to topology extraction using Probe.4 V1 t/ `: o2 c7 y
953713 CONCEPT_HDL PAGE_MGMT Random page replacement/duplication in block$ F/ [: ~9 c- L# T( K4 W4 z
953917 CONCEPT_HDL ARCHIVER archcore should handle errors correctly
9 U# o i' j3 d6 B4 a953971 ALLEGRO_EDITOR MANUFACT NC Drill files not generated correctly when using the option "搒eparate files for plated/nonplatedholes�
- u4 D* m* m! z9 I3 k% z954400 CAPTURE NETGROUPS BUS members of NetGroup are getting converted to Scalars in Export-Import NetGroup.3 u. k9 I6 Q- R5 F+ A% W
954498 SCM B2F SCM crashes when importing physical3 z# l* l+ Q+ T) B# c8 h/ l
954623 ALLEGRO_EDITOR EDIT_ETCH Unable to complete connection with Add Connect - related to soldermask to cline check?
. C1 C& a6 t" |954894 ALLEGRO_EDITOR MANUFACT Dimensions disappear when opening database in v16.5 from v16.3
" l9 u* `8 M e. @955029 CONCEPT_HDL CORE custom text font size not recognized in symbol view& \; k, y5 ]) d3 U& v, [
955133 SIG_INTEGRITY FIELD_SOLVERS The Field solver creates the differential trace model which is reversed T(D1) and T(D2) of bottom side.6 K& n6 T- G2 O
955290 CAPTURE DRC Description for UPD0014 missing in the Browse DRC markers window6 @8 t f6 O( a* u2 w+ N, U& ^" @
955299 ALLEGRO_EDITOR DRC_CONSTR drc text to smd pin does not work any more on this database in 16.3 S0394 c6 O( P5 k9 G6 E
955338 CONCEPT_HDL CHECKPLUS Need to change PART_NAME
* s# ]: V/ ~. G# J7 n955447 SIG_EXPLORER OTHER Model path set in DE HDL Model Assignment not used by SigXP from CM in DE HDL a! U, T$ Z( j" Y
955740 SIG_INTEGRITY GEOMETRY_EXTRACT Crosstalk with Timing Windows does not work correctly; V8 E# E( C/ Z; @
955749 ALLEGRO_EDITOR MANUFACT show element Info shows symbol dimensions on incorrect subclass6 A* V; W/ Z u
955912 ALLEGRO_EDITOR OTHER Shapes with voids that are exported to PDF have gray filled area over the void% {/ n" b( x: n
956129 CONCEPT_HDL INFRA DEHDL uprev hierachical design from 16.2 to 16.5 packaging failure.
+ \) S; P( R( y8 u+ z956373 ALLEGRO_EDITOR NC drawing name doesn't display in the log file
) V2 `- `9 N# k# Z3 h956393 CAPTURE PROJECT_MANAGER "GENERAL" and "TYPE" tabs are missing from " roperties" dialogue box.# c+ o6 {1 O+ t) X8 q/ O/ R
956448 PSPICE MODELEDITOR Can not generate a DEHDL symbol from Model Editor, because no Capture license found
+ k$ G/ j' ]6 d: K g956456 CAPTURE NETLIST_OTHER OrTelesis netlist not transferring user properties defined under combined i1 n _# t1 V( l! B& l
956489 ALLEGRO_EDITOR MANUFACT dimensions lost when symbol with diemnsions attached to symbol origin placed on board
* j) a$ m6 y2 k8 q9 ^( P956603 CONCEPT_HDL OTHER Part Manager "has stopped working" after changing a component$ f" m1 t& F7 K: }
956751 ALLEGRO_EDITOR ARTWORK Import Gerber command does not work correctly4 z# _6 [0 G* k# Q- V
956847 PCB_LIBRARIAN METADATA PDV - Partdeveloper symbol to function linkage broken/changed in 16.5
5 W* F5 o, `; t) w956987 CAPTURE OTHER Find from "Search toolbar" doesn't gives complete results
8 S( k7 c" b, p7 w' `) J4 f& }956996 CONCEPT_HDL INFRA Correction to ERROR(SPCODD-7): Following Primitive instance causes CM to empty
( y* A, p4 [/ F957009 CAPTURE NETLIST_OTHER Problem getting database property in mentor PADS PCB netlist
* d2 _. J1 v7 H957137 APD DXF_IF DXF out command dose not work correctly.+ S7 Y$ d* I- R; o
957167 APD GRAPHICS Highlighting for Static shape with display_nohilitefont environment variable. N S+ T3 O/ e- P* O
957232 SIG_INTEGRITY OTHER Allegro crash during Model Assignment.
1 z4 ]- M. Z/ p: s9 g957267 CONCEPT_HDL INFRA Packager Error after Import Design
& T: e! E. H, Q8 Q, }957866 SIP_LAYOUT DATABASE Cavity outline is not getting deleted from symbol file* Q6 U, \8 s' @( _" l! X
958010 ALLEGRO_EDITOR REPORTS Wants the ability to extract "Batch" reports from Partition ".dpf" files.' r8 \: R3 V6 ]2 P# M' O
958252 ALLEGRO_EDITOR TESTPREP Resequence testprep with the option - Delete probes too close crashes the design$ ~7 Y5 q: [2 y8 a2 D
958253 ALLEGRO_EDITOR REPORTS Shape did not have thermal relief connected to pin but unrouted nets still shows zero.% t m2 N/ S0 U9 R7 z% W) [
958433 ALLEGRO_EDITOR DRC_CONSTR False embedded component DRCs
' h3 f3 v8 g o" j. x7 F: {958753 ALLEGRO_EDITOR SHAPE Dynamic shape is getting corrupted in 16.5
) L5 z' j' X/ I6 ^# R5 K" R959011 ALLEGRO_EDITOR OTHER copy problem of via and cline* s/ L. l- S. O, u7 S
959101 ALLEGRO_EDITOR EXTRACT Using extracta with excluding Thermal reliefs9 f/ D7 F9 B% a
959253 CONCEPT_HDL INFRA Design will not open) m$ L" c+ S4 T6 h# _- V
959299 APD MODULES Getting ERROR(SPMHDB-279) when trying to update modules placed on the Top side' ~: x& T" Q1 | _! p% p
959884 CONCEPT_HDL INFRA Design Uprev/concept2cm crashes with Application Error/Out of Memory Error.) j- S4 e" x8 z0 x) V' \, @, y
959909 ALLEGRO_EDITOR SCHEM_FTB Site level propflow.txt file is ignored property is transferred# ?! Z: p; U/ }' n/ J
960067 SIP_LAYOUT PLATING_BAR Creation of plating bar removes "NODRC_ETCH_OUTSIDE_KEEPIN" property from the clines.$ X/ g0 p$ l b0 f
960126 SIG_EXPLORER EXTRACTTOP Allegro PCB SI license is used automatically at Topology Extraction of Allegro Physical Viewer.6 { j) y) o0 w
960143 SIG_INTEGRITY GEOMETRY_EXTRACT Running simulation in Bus sim happened crash while enable Coulpled Via model to S parameter. U7 c- g6 R; b: a0 F: x5 l; i1 L
961349 CONCEPT_HDL HDLDIRECT Motorola designs have broken connectivity compared to 16.3
6 h/ r r0 q5 u1 i4 f! X% Y961816 ALLEGRO_EDITOR INTERFACES Normal Export > DXF fails and offsets the pins of the BGA symbol2 u* {" a0 `- G; Q
962519 SIP_LAYOUT WIREBOND Align option doesn't work for wb_tackpoint fingers
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DATE: 11-30-2011 HOTFIX VERSION: 012- e' a. s+ n! X' z. W+ m" W
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5 B( l6 s5 n1 WCCRID PRODUCT PRODUCTLEVEL2 TITLE
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- s- ]/ Y& m4 n; ]0 m959581 CAPTURE NETLIST_OTHER PCB Footprint is getting replaced by VALUE in OTHER netlist formats) d" N+ V, Q% N+ k6 \8 ^ I7 C! Q
* P1 R; s) D7 F/ Z7 [ S3 M0 ^0 ]! a7 JDATE: 11-18-2011 HOTFIX VERSION: 011
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CCRID PRODUCT PRODUCTLEVEL2 TITLE
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3 ^% H" B" G, q/ ?8 P4 ]9 v0 S- u; g735439 PCB_LIBRARIAN CORE PDV Moving line-dot pinshapes by arrow keys breaks the pinshape- ~4 p! t( U8 X6 P' _4 }
894815 CONCEPT_HDL COMP_BROWSER Why does genlibmetadata command give 'Aborted $PROG' Message?
4 }8 d7 Z7 g0 O/ F903073 ADW COMPONENT_BROWSE datasheetl_url directive should support a display string for URL
/ x2 E3 t9 C* h; U, u* b6 O909919 CONCEPT_HDL OTHER Why is the PublishPDF UNIX command line looking for "true" script?" ?/ }) u4 o; t4 ?& @3 V
911561 CAPTURE CORRUPT_DESIGN Capture crashes on trying to save the design.' |0 ]2 P9 t7 x0 A
919579 CAPTURE PRINT/PLOT/OUTPU Print mode be selected based on schematic mode0 u4 U3 H0 ^, \- Y9 ^% V
921247 CONCEPT_HDL COMP_BROWSER genlibmetadata.bat file does not have err defined
& D! p" o9 I) N. m% N! H" f+ i# X925182 CAPTURE PROJECT_MANAGER ENH: Feature to run update cache on all the parts in design cache at once.
: i3 a- I, _" D926858 CONCEPT_HDL CORE Usability- Modify Component dialog forces user to do 'Reset Filters' to see other ppt rows, {3 U( `* r* O h) O
927657 CAPTURE NETGROUPS Enhancement: Placement of netgroup definitions under design cache list. r3 D$ _5 ~# d r; @
934684 ALLEGRO_EDITOR MANUFACT The relation between the linear dimension and the symbol breaks.
6 N8 \, N% P: ~9 I935836 SCM SCHGEN ASA crashes when generating Flat Document Schematic6 p* T! w. c" h
937165 SCM SCHGEN Can't generate Schematic7 B ]/ \; \; r5 o
937292 CAPTURE GENERAL Memory usage keeps on growing and finally gets exhausted while search: L$ a7 _9 V. ^- o
937322 CONCEPT_HDL CORE Master.tag file alters the sequence of the files and Genview fails q% _; P& A4 `9 D: D( ~
939135 CONCEPT_HDL CORE Unable to uprev a 16.3 Design to 16.5 with DEHDL-L License
- q0 c1 S& x; R) p$ v$ C& J; U940373 CAPTURE TCL_INTERFACE Enhancement: TCL command to add nets to Netgroup
( H, x3 U* X; H2 Y( V5 c* E+ b940547 TDA CORE ERROR(SPDWSD-69): highspeed cannot be checked in! {4 K& g' h9 Z2 U6 S* D
940607 SIG_EXPLORER OTHER Inconsistancy in License usage for opening sigxp -orcad0 r8 p. {9 y) T+ e+ n. `& p* ]/ t
940790 F2B PACKAGERXL User doesn't want to display pin numbers after Export Physical 16.5.3 V. {0 ^/ u# W! e8 I; w* s
940944 SIG_EXPLORER OTHER Inconsistant license usage while opening Orcad PCB SI using allegro -sq -orcad and allegro -sq$ j/ b2 f" P# X1 r1 Y( [+ G& ~
941354 CAPTURE NETGROUPS Enhancement: Option to rename the unnamed NetGroups ~" I! I* W* J4 Q, a$ e/ ]; ~
941455 ALLEGRO_EDITOR MANUFACT The Dimensioned mechanical symbol when placed in the board does not show all the dimensions.
: n a2 _+ s: x. _941863 ALLEGRO_EDITOR EDIT_ETCH Different behavior of design in v16_3 & v16_5 when add connect is executed on a segment thru script5 @ [ R+ ~! J9 [) t; b4 y
941881 CONCEPT_HDL COMP_BROWSER How can I suppress the dialog from universalbrowser -genlibindex?1 X" O6 `% D- R( H8 V1 \# G) B
942474 CAPTURE NETGROUPS NetGroup member type of last added member must be remembered by Capture3 y% G. P3 T+ q+ L' H: `5 ^
942522 CAPTURE GEN_BOM Export in excel check mark doesn't invoked BOM in Excel
5 I _4 y/ F3 D% E- h2 R942557 PCB_LIBRARIAN EXPORT_OTHER PDV Export to Capture crash/ z! D' l8 ?' |
942569 ALLEGRO_EDITOR MANUFACT Dimension move and change text deletes leaderless balloon
& S$ t' E$ N9 l# A, @1 {942573 ALLEGRO_EDITOR MANUFACT Balloon type parameter has no effect on leaderless balloon.
k6 T/ B$ `+ |: x1 t942613 CONCEPT_HDL CORE Genview supports only SCHEMATIC/SYMBOL/VERILOG/VHDL views as input type. .xcon not recongnised$ C0 Q- e! {! M. W
943032 SCM OTHER ASA is not passing the correct reuse_module name to Allegro PCB layout.# h) J( m# O) q# @8 I/ m
943401 CAPTURE NETGROUPS Alphabetical ordering of NetGroups in Place NetGroup$ L" e9 E) K$ l! [( |5 b
944006 ALLEGRO_EDITOR EDIT_ETCH Vias added to shapes behave differently$ s. H Y5 P- a$ u' Y6 t
944367 CONCEPT_HDL OTHER Too late to do Model Assingment in conceptHDL 16.5! s: N, B- ~- m/ F ?: E
944788 ALLEGRO_EDITOR GRAPHICS Oblong Pad shows unexpected lines
" B* e) z$ _% U945221 CONSTRAINT_MGR RETAIN_CNS CM Conflict Resolution fails on more complex designs using ECSets and constraints5 g) W3 G8 b5 T3 O9 }7 K0 E
946270 ALLEGRO_EDITOR PLACEMENT The Rotation Type was changed to "Absoute" if the "iangle 90" use at placementedit mode of spb16.5' Y2 \* i' J8 V) K# e2 B1 c; S
946350 F2B DESIGNVARI Variant Editor rename function removes all components; U n6 g- {+ U$ M' V% p; V& U
946380 F2B DESIGNVARI Some VARIANTX properties are hard some soft - why?3 g/ w" ~3 u# [ ? ?" W
946419 SIG_INTEGRITY SIMULATION Cannot select component on BoardModel for controller in bus setup form/ U0 o9 V+ P" p
946458 SCM SCHGEN Schematic generator adding an unnecessary page- J0 Y/ m Y/ V) x5 W
947667 ALLEGRO_EDITOR PADS_IN Need support for PADS-POWERPCB-V9.3-BASIC* I+ T: Q0 ?+ v' h- ?0 {+ X
947789 ALLEGRO_EDITOR MENTOR mbs2brd crashes during translation on the attached design.
4 s" ?' ]) y! j! {948110 CONCEPT_HDL CONSTRAINT_MGR Concept HDL craches when opening SigXP from CM9 P2 u1 b. T/ m8 A2 S! i
950970 ALLEGRO_EDITOR MANUFACT Unable to generate artwork, dbdoctor fails to fix errors.
, o2 J, C0 v' n# ]8 ~951901 ALLEGRO_EDITOR EDIT_ETCH In 16.5 add connect to same net is shoved, a; D2 J2 Y* P4 w) o
951919 ALLEGRO_EDITOR OTHER Exported package symbol soldermask and pastemask padstack locations not the same as original
" E, `6 D/ C$ r5 I- [951926 CONSTRAINT_MGR OTHER What is MaestroNotifyNotSetReport.txt file?
) \, I9 U: W! U* W951939 F2B PACKAGERXL Uprev to 16.5 is changing refdes for some pages7 N$ N# M$ [* c: a4 M
951983 CONCEPT_HDL INFRA Problems converting an Allegro design from 16.3 to 16.5
$ Z5 i9 u5 h, R: F; ?952057 SCM PACKAGER Export Physical does not works correctly from SCM
6 z2 U* v* x$ j952217 ALLEGRO_EDITOR GRAPHICS crash when opening 3d viewer in PCB Editor8 }4 }3 S- Y5 h' m5 q
952634 CONCEPT_HDL CHECKPLUS Checkplus logical rule fails on a design which packages fine in 16.5
( e0 n" s4 e/ d9 \6 h+ x5 `953018 APD REPORTS Shape affects Package Report result.
1 Q9 i2 _' Q( Z953337 ALLEGRO_EDITOR OTHER Allow netname and padstack names to be visible for testpoint vias when viewed in Allegro PDF Publisher.. q0 \2 ?( C" i4 e) e( M
953827 ALLEGRO_EDITOR EDIT_ETCH Snake Breakout function crashed Allegro
* W. a$ e8 i) k8 q6 ]' l953918 GRE CORE GRE cannot route second and third row of pad in die symbol.% k! Q7 j& [) ?: ~4 P* f3 ?. {+ W; u' Q
954055 CONCEPT_HDL CREFER Crefer fails with UNC install path' ^& ^5 g4 f: @# i# t2 n
954920 SIG_INTEGRITY CIRCUIT_BUILDER Each neighbor crosstalk simulation crashes or returns blank report
; Z1 f0 _' z( }# N6 }8 }! i( ^/ d, @* r4 H7 P* \4 S
DATE: 11-7-2011 HOTFIX VERSION: 010, t. l& r. Q2 O/ b& J E4 u' x
===================================================================================================================================( [$ t2 Q3 T0 K' A8 n2 l" A5 o7 w% A
CCRID PRODUCT PRODUCTLEVEL2 TITLE. e8 M6 W) L( c0 D1 ^2 y6 i
===================================================================================================================================' u+ \7 \+ v9 D/ a1 M6 a8 K
658866 ALLEGRO_EDITOR EDIT_ETCH enhancement option - so that Sliding a via inside a pad does not create a cline
; Q( ?. c2 p/ t928624 ALLEGRO_EDITOR GRAPHICS Layer visibility control for 3D Viewer" ?6 s# H [6 k: o9 v+ G6 E
934991 SPECCTRA LICENSING Specctra_adv option is not working correctly for PA3100 plus PS3500 license in v16.5 tiering profile$ R2 O, T( W9 w k6 n" _
938073 ALLEGRO_EDITOR PLOTTING Plot Page size A0 and A1 with problem# x$ @& _8 p2 W4 X: Z$ ^
938128 ALLEGRO_EDITOR DRC_CONSTR DRC changes when do update DRC.
; Q0 Q6 L3 l1 \4 s938648 ALLEGRO_EDITOR GRAPHICS Enh - Requesting a way such that Package keepout appears transparent in 3D Viewer8 ]2 T) C8 B; ]4 Y* I$ X
940518 SIP_LAYOUT SYMB_EDIT_APPMOD Swap pins command doesn't complete9 e& J2 W4 H; y
941426 CONCEPT_HDL COPY_PROJECT Copy Project fails - Updating opf view This can't happen!
8 g" V8 R! H5 V I" \6 D( Q. h941499 ALLEGRO_EDITOR DRAFTING BUG imit Tolerance isnot working for Dimensioning
/ |4 r. x( N% J# I; b9 _1 W941814 CONCEPT_HDL CREFER CreferHDL crashes during ScheGen3 L6 t0 K" }# V' j# `
942914 SIG_INTEGRITY OTHER ZAxis delay calculation
$ O+ n2 L3 f. M* `# K943053 ALLEGRO_EDITOR SHAPE Modifying the Board Outline shape will cause the tool to crash
$ M% ~" e8 y$ P. H7 O3 E945321 SIP_LAYOUT EXPORT_DATA generation of a xml file from cdnsip for shrunken die, o& I& h5 A* k" y/ m
945350 ALLEGRO_EDITOR SHAPE iPick does not work on shape boundary edit.
0 y/ d v1 s- C) P7 X945449 APD SKILL When they create a new menu entry with skill APD crashes with next menu selection.
; g) l$ Q( t6 ?& L0 Y946390 ALLEGRO_EDITOR DRAFTING refresh_symbol crash when trying to refresh mech sym that has dimensions
' V3 i! Y; d: `* k5 x9 J5 ^0 q946401 APD EXPORT_DATA stream out gdsII results in shorting of PWR/GND nets due to elongated etch5 t6 }, u1 b. l+ Q, N# Z
946819 SIP_LAYOUT DEGASSING Shape degass command
' s% b) \& I) U- ]+ e2 N& b$ d- Y946869 ALLEGRO_EDITOR OTHER Allegro PDF arc representation needs cleaned up
) O2 T) J+ q7 r% C, F947230 ALLEGRO_EDITOR SKILL Skill execution crash Allegro 16.5 but work correctly with Allegro 16.35 \0 [# _* @$ g/ S2 N% o3 O4 s& r
947603 ALLEGRO_EDITOR OTHER Component Properties (Default or User Defined) not transferred to PDF file
6 R( y j, p* v: d/ R950995 SIG_INTEGRITY OTHER Netrev fatal error when importing logic
5 u8 y) G* f0 z3 J( B( E2 D951123 ALLEGRO_EDITOR INTERFACES IPC fails to output drill hole info in columns 33-37
5 @! E# {1 O% T* C# E4 v4 |951557 CONCEPT_HDL CORE Cannot create the entity folder for old plumbing symbol! e6 P* p' |3 e
% x! ]8 }8 Q) w0 E6 hDATE: 10-26-2011 HOTFIX VERSION: 009
_/ w* I; r* W6 S# w===================================================================================================================================
1 C3 @& n% M+ T( F6 T# @CCRID PRODUCT PRODUCTLEVEL2 TITLE
+ s# j" [ q+ c3 Y7 O3 `9 D9 ~! C===================================================================================================================================
1 {( k/ {+ B6 o$ A1 i945788 CONCEPT_HDL CORE Some component properties on the parts are incorrectly changed after Import Sheet
- I m% N. O0 @$ F2 l9 N6 W# e8 C945789 ADW LRM Some component instances are not updated by LRM even though cache ptf is updated from reference& d# c: p2 F2 A4 t' T9 M
$ J( g7 k" o& C+ @' D
DATE: 10-21-2011 HOTFIX VERSION: 008
9 v$ _, W1 |0 a' t===================================================================================================================================
' V. @5 r5 ?0 A1 Z6 CCCRID PRODUCT PRODUCTLEVEL2 TITLE
* \- `* o, f" w6 |" k# \2 h===================================================================================================================================8 N; `; v3 A) f4 w8 z$ D' l
906827 ALLEGRO_EDITOR DATABASE Logic > Parts logic does not work correctly.4 D, Z/ D: Y y3 j( ?9 _
923346 CONCEPT_HDL CORE Not able to move the reference designators inside hierarchal blocks after uprev to 16.55 U; g. J" a, i+ n5 y0 z
926347 ADW COMPONENT_BROWSE Usability- Libflow Part check in comment should end up in Comments attribute for UCB/Designer to see it
: A! A: W* r* V# K929348 F2B BOM Warning 007: Invalid output file path name
: e* Y: s9 N1 F. a* `+ y929777 CONCEPT_HDL OTHER Component Revision Manager gives internal error( n- @$ T0 O* i. f
930783 CONCEPT_HDL CORE Painting with groups with default colors
0 ]% F, T) }; |" f. m7 h0 o0 W936748 ALLEGRO_EDITOR INTERACTIV "Unplace Component" menu inconsistent between General Edit and Placement Edit Mode.
: X/ m) L" O- H" l9 {; v938143 ALLEGRO_EDITOR CREATE_SYM Why is this Extra Property 'ECSET_MAPPING_ERROR
# d1 L& O g6 u6 @6 c7 n938281 SIP_RF OTHER export_chips creating bad data when symbol is split and contains V- V+ pins
1 m) T+ V0 |( C9 b9 R938812 ALLEGRO_EDITOR SYMBOL Cannot create a BSM with this DRA, errors out but does not state a reason.1 G1 j' I, e7 a; A5 R
939075 CAPTURE TCL_INTERFACE Texts are getting garbled in command window9 C4 k5 t; R( I) O
939193 F2B PACKAGERXL ERROR(SPCODD-439): Connectivity server is unable to load the design.$ P* ^0 @8 l1 C+ M, Y' l7 p) ^
939199 CONCEPT_HDL DOC "Retain electrical constraint on net" mismatch between schematic (YES) and design (NO)1 o l; K; k: j& h* ?1 L
939346 ALLEGRO_EDITOR SHAPE Shape disappears when updating with variable shape_rki_autoclip set.
4 T5 D0 z& }" }) X939901 CONCEPT_HDL INFRA NET_SPACING_TYPE shows �?� on lower hierarchy level nets after Upreving to 16.5 version.
7 M3 h* l1 L- |: x$ J" K939918 PSPICE PROBE Print > Preview for output file causes Pspice crash.
5 E B; |1 v# u; M) J4 d940217 CONCEPT_HDL COMP_BROWSER UCB reports 'No Symbol found for the part'
- r1 A: b! E$ g7 h" S7 ? y a# l940835 CONCEPT_HDL INFRA Desing package different after uprev to 16.5 where comp instance propeties are lost lost4 D, _6 k! F2 X: j5 Z
941125 ALLEGRO_EDITOR DATABASE Performance advisor doesn't skip non plated slot padstacks% c' \4 s' O2 }
941876 SIG_INTEGRITY OTHER Illegal model name cause pxl fail in 16.3
. b. H& X7 i8 c7 t8 R! S2 T942210 SCM OTHER Is the Project File argument is being correctly passed?
/ y: F- k9 _1 _( ?942274 CAPTURE PROJECT_MANAGER Crash on renaming a Design Cache part in Project Manage after doing replace cache; U/ e: ^1 d) V1 h4 Y% y1 Y
942839 ALLEGRO_EDITOR GRAPHICS Graphics Issue- Pads are not visible% s8 T1 }4 |8 k* {! [' s7 a
943055 ALLEGRO_EDITOR SKILL axlDBCreatePropDictEntry causes application to crash
! i9 n: U6 O& i. n) ^: T' i/ e8 i( G, P5 Z) o7 ^. i
DATE: 10-21-2011 HOTFIX VERSION: 007
1 m: n% _3 S- r* A===================================================================================================================================% P8 P* D* K8 @3 ~- ^
CCRID PRODUCT PRODUCTLEVEL2 TITLE# e$ J v/ K( I/ s. U
===================================================================================================================================
! x# U! K5 Z3 g* y; g0 b841096 APD WIREBOND Function required which to check wire not in die pad center.
. S$ n% |/ l8 b5 B% n903263 CAPTURE SCHEMATIC_EDITOR ENH: Selecting parent netgroup must select the underlying netgroup bits./ ^2 o3 i( E4 x+ K( a6 i
906692 ADW LRM LRM window is always in front when opening a project
6 a: |, T5 G$ X+ ^0 u" f8 ?+ X# \912942 APD WIREBOND constraint driven wire bonding) x0 c: @# A1 m [1 c
912951 CONCEPT_HDL CONSTRAINT_MGR Need to manage temporary files on Linux systems) G% i) ]! a5 J0 v0 ~; d3 P) Y# t/ @
915178 SIP_LAYOUT DIE_STACK_EDITOR Die Pad names changing when updating Die in a design
I6 i0 H4 R( |. H: \9 c917887 PCB_LIBRARIAN VERIFICATION Part should not be released if the alt_symbols has errors
+ j j7 |# ~, x# `- m923315 SIG_INTEGRITY GEOMETRY_EXTRACT crosstalk simulation fails with TMP popup failure
7 Z. l* H4 o K7 `5 T3 `927382 CONCEPT_HDL CHECKPLUS 'Verify Symbol' forces the use of 'Concept_HDL_Studio' license
& o3 t2 g- Z4 [: S& ?& j. {927664 CONCEPT_HDL CONSTRAINT_MGR Internal Error disposeipsp2 N' i9 c6 r. l# J
930152 CAPTURE NETGROUPS Scalar net names when being connected to net group overlap when connections are made one by one
- N3 M$ i6 ^5 x+ N7 E" @2 ]6 U930180 CIS LINK_DATABASE_PA Visible property position on schematic get reset on "link database part" operation8 M+ _) g, ^4 [
930188 CAPTURE DATABASE Capture 16.5 crashes in being re-invoked.
" z6 r+ R; J& S8 I7 B i930541 CAPTURE NETGROUPS NETGROUP element renaming doesn' renames the associated net ?
2 @4 ~2 X2 S G6 h( g930866 PDN_ANALYSIS SETUP OrCAD PCB SI Session crashes when we open PDN Analysis with "OrCAD PCB SI" license.$ K3 D! q$ Y# @5 ~. z9 z. |5 w
930926 ALLEGRO_EDITOR GRAPHICS Via and Holes not visible eventhough set to Visible in Color form
; L' [7 G7 v9 A931274 ALLEGRO_EDITOR DRC_CONSTR Negative Plane Islands waived DRCs reappear after performing update DRC.
8 |: g; m% Y( p" w. u932091 CONCEPT_HDL CORE Prop attached to SIG_NAME property
; a5 W$ l& ]9 Y: P4 U932255 ALLEGRO_EDITOR GRAPHICS Change in Zoom level makes arc segment to disappear
R- @, s; O" i& n. z932292 ADW LRM LRM crashes during Update operation on a customer design
& v6 [& _# O C ?3 O# V932639 SIG_INTEGRITY OTHER Add Connect command hangs for about 14 seconds and then returns.
( ~& |# u/ {& d+ O5 P0 i932704 APD DEGASSING Shape > Degass never finishes on large GND plane6 S3 _8 i- r6 }
932871 APD GRAPHICS could not see cursor as infinite, E. Z4 t V5 H; o( L
932882 CAPTURE SCHEMATIC_EDITOR Capture crash with FIND command - ISR054 s" t* J: b5 V" S- _9 |# C$ a& a7 R
932969 CONCEPT_HDL CORE ConceptHDL crashes when you save the design in 165 > hotfix #05
* j0 c3 f" t! s# P! r- f933024 CAPTURE NETGROUPS Naming restrictions for NetGroup members
# J% x0 M: R2 ^, S! q933145 F2B PACKAGERXL Add Subdesign list is truncated in Force SubDesign Design Name pulldown! N+ W! l2 \+ i: N y- z1 O! u
933214 APD ARTWORK Film area report is larger when fillets are removed$ r1 h9 a- }$ v# D. O8 q
933356 CONCEPT_HDL CORE Net prop display size become 0 if it was attached to SIG_NAME prop.
. q" Q' A' F) W3 q933532 ALLEGRO_EDITOR COLOR Bad color assign and initialisation during creation of new subclass2 O& _4 {5 p) }! ?* C8 h: n. C) _
933549 ALLEGRO_EDITOR OTHER Chart text missing in export PDF file.
1 l5 C% s2 [# o# C3 ]) r! M3 Z934008 ALLEGRO_EDITOR REFRESH refresh symbol updates symbol text to some unexpected values+ E& I4 v$ B7 \* f0 Q* {# \4 k
934031 ALLEGRO_EDITOR DRC_CONSTR Bug : Update DRC removes Waived status for some DRCs
+ S# C) k: S+ @7 h9 o1 A q934087 CONCEPT_HDL CORE Opening DEHDL and Model Assignment before design loads causes crash$ m4 L6 s' ^+ F$ t. j; {, {3 f" B9 p
934396 CAPTURE SCHEMATIC_EDITOR Find operation is not searching power symbols with + or - signs.
$ y1 E" V' F$ O: w. M1 F1 |934533 F2B DESIGNVARI The Variant Editor errors are not written to the variants.lst file
* r4 I- V j5 e8 m' H3 F z934811 SIP_LAYOUT UI_FORMS CDNSIP should not hang if contraction value in z-copy command is out-of-bound- X# f& U; v8 w6 y! W
934909 SCM UI Require support for running script on loading a design in SCM
* m6 {% q3 E# y- ]935632 CAPTURE SCHEMATIC_EDITOR SHIFT+Mouse wheel scroll(horizontal) of page is not working in Auto Wire Mode.) e4 I4 Z! g4 ^: N" Z. s0 s
935794 ALLEGRO_EDITOR SHAPE BUG:Shape not filled in 16.5 but it does in 16.33 N& x4 U1 w' ^+ j/ h- {: F4 S
935988 ALLEGRO_EDITOR INTERFACES When attempting to downrev this 16.5 design to 16.3 the tool will crash8 X: ] ~; g4 H' `2 g- x, _
936056 ALLEGRO_EDITOR DRC_CONSTR place_manual crash while moving mirrrored symbol
* S; C2 V4 |3 u. @ D: P3 v* X936098 ALLEGRO_EDITOR SKILL axlDBCreateCloseShape does not work correctly.
8 @- z) d$ w1 T$ r3 \% B9 K936212 ALLEGRO_EDITOR INTERFACES DXF not created if Blocks created for Symbol and padstack) M. ?6 r4 v* C- O7 b V
936797 CONCEPT_HDL COPY_PROJECT Copy Project crash- T- Q7 T) e. x6 M2 d9 B+ a
936808 ALLEGRO_EDITOR DATABASE Allegro crash replace mechanical symbol: i( V' @- E( `* s2 i
936853 CONCEPT_HDL CONSTRAINT_MGR DEHDL crashes when trying to extract net from CM
& x% c4 ]4 l2 ~+ K5 X/ t& L937087 CIS DESIGN_VARIANT Upreved design becomes very slow in Variant view mode. DELEET THE DESIGN AFTER RESOLVING THE ISSUE$ G' e! t- L n8 m& H4 w0 L
937173 CAPTURE OTHER Wrong license information "UNLICENSED" in Capture >> Help >> About
$ B* Q; n: x1 c E" H) w937290 APD PLATING_BAR Plating Bar checks does not recognize connection made through etchback through shape.9 ^4 R3 O' e% H3 _
937411 ALLEGRO_EDITOR DATABASE downrev_library reading from one directory and writing to another hangs the command.; K+ s: Z% H: e$ l( @
938235 SIP_LAYOUT STREAM_IF Die Orientation is not correct after importing a stream file.
8 f5 y5 M: `" h: `/ [0 c938273 ALLEGRO_EDITOR OTHER PDF export is is not opening viewer with ads_sdlog variable set
' u+ K/ w- c" |
4 M; k5 J6 E& T0 YDATE: 09-16-2011 HOTFIX VERSION: 006
/ r( F' X% }2 f8 v1 z. L9 ^7 w' h===================================================================================================================================* \0 t$ s, X& `" O1 H b
CCRID PRODUCT PRODUCTLEVEL2 TITLE
: N( m; o0 x F- |2 D===================================================================================================================================- e8 X5 i9 x/ p
820131 CONCEPT_HDL OTHER Moving symbols to other page will make Allegro components unplaced because logical_path changed." |! }" S4 @! z& {* b+ v& W
863860 CONSTRAINT_MGR SCHEM_FTB CM should display or Local Interface and Global nets to help defining low level constraints
, [6 j2 x$ u A q w) u* [919822 TDA CORE Cannot configure LDAP to only list the login name
$ b$ d: n, P3 S# `' t4 p! E922907 ADW TDA 搇ast_callout_file� directive in the BOM section is empty causes tda for show Access Denied error' i/ ?; M4 i4 R) M: D7 J
924322 ADW COMPONENT_BROWSE Random - No instance properties are added on Add To Design (RMB or double click) from Search Results8 x) x) H7 _ g0 U2 s
924448 F2B DESIGNVARI Design does not complete variant annotation
: l+ X6 E/ i y) b$ D4 z925584 CONSTRAINT_MGR SCHEM_FTB 16.3 upreved Design passes the SLOT/Function Properties to PCB
% l, v9 R1 |; }# s6 e; L2 g# b6 O927102 ALLEGRO_EDITOR OTHER Question of Conductor Detailed Length Report
5 { b& c0 o) W927104 F2B DESIGNVARI Tools > Annotate variants crashes when there are ASCII characters in the property values
% l& Z# S3 z, {" U# K4 ?927142 F2B DESIGNVARI Incorrect pop up asking while executing variant editor from the command line
# O- C. v/ {( _; F927166 CAPTURE NETLIST_ALLEGRO ENH: Feature like NET_SHORT in Capture Allegro flow which allows user to short 2 or more power nets( c! B) @4 }: Y% A
927410 ALLEGRO_EDITOR DATABASE ERROR(SPMHUT-144): Illegal arc specification error when Run DBDoctor
, d9 C% R* o* z8 k% X927475 CONCEPT_HDL CORE About forcereset command of nconcepthdl
: l7 r* g+ `" p) s; a927498 CONCEPT_HDL CORE Pin_Name starting with minus causes incorrect behavior for $PN display
5 ^8 b* [2 |$ P) ~927608 ALLEGRO_EDITOR PADS_IN Import PADs fails with error message: Failed to close the Allegro database
+ W2 Y! M! g8 {3 a927637 SCM CONSTRAINT_MGR ASA crashes on change root and also performance is too slow.% ^# }0 @1 c7 }7 n' o- c4 [
928429 SIG_INTEGRITY OTHER Request - Package Wizard to work in PCB SI.
: Y/ n5 ~) |( ?928483 ALLEGRO_EDITOR DRC_CONSTR Running Update DRC removes Via List DRC Error when via is actually not in the list5 D) C$ _! J# K
928738 PSPICE PROBE Y-axis grid settings for multiple plots1 k9 K/ j/ y: j- |/ `
928748 PSPICE PROBE Cursor width settings not saved. e9 g3 \+ l4 b$ b4 O# Q
928779 CONCEPT_HDL CORE Error (1053) occurs on a copied part in SPB165 release3 O- E1 Q9 `+ e
928838 CONCEPT_HDL CONSTRAINT_MGR ECSets not migrated in 16.5
2 c% U) o( Y, B( q928885 SIG_EXPLORER EXTRACTTOP PCB SI crashes when extracting a net from Probe
) n) k) t7 M* }929284 CONCEPT_HDL ARCHIVER archive does not create a zip file, k. b7 [: d; K* F! k
929542 SIP_LAYOUT DIE_ABSTRACT_IF net issue of multiple ports of co-design die in SiP
+ G3 u) Q, z* x2 D t929656 ALLEGRO_EDITOR PADS_IN PADS translation fails with Microsoft Visual C++ Runtime Library error% ?9 C2 Q4 R1 j8 u
930063 ALLEGRO_EDITOR TESTPREP Test prep crash Allego when it can not create pin escape+ Z+ K& c9 ^- N
930217 CAPTURE NETGROUPS Net aliases doen't gets assigend to bus bits if bus name is checked in NETGROUP.
( b8 e/ S" C+ F% m9 v930355 SIP_LAYOUT WIREBOND about "wirebond add nonstandard" command
: s/ t% l! Z" K) w M+ ?930607 APD OTHER Layer mapping information is reomved from Layer conversion file upon exporting DXF from board file.! k j3 t! ]1 K1 |, X! r) D. t
930646 ALLEGRO_EDITOR DRAFTING Bug - Adding Linear Dimenstion for ISO standard add the Angle information as well
/ I) a7 F7 r- S930894 CAPTURE TCL_INTERFACE PDF export doesn't creates property file if some symbols are used in page name/folder name
4 |# V& p% F7 c, h930944 ALLEGRO_EDITOR OTHER Setting variable 'appmode' equal to 'none' is not changing the Application Mode when reinvoked1 y* L5 k4 P# H3 ^- E @' ?- O2 M
930978 ALLEGRO_EDITOR SCHEM_FTB 3rd party netin error - Pin is connected to net <netname> not reconnected no longer happens
% F# M# L) J" W! M$ V$ G931248 ALLEGRO_EDITOR DRC_CONSTR Match Group was removed if member nets became xnets.5 U1 M5 Y6 g S
931278 CONCEPT_HDL INFRA $PN gets copied when upreving design from 16.2 to 16.5 version5 e% h% y" w+ l7 s* s0 ]3 j5 {
931349 CONCEPT_HDL COMP_BROWSER DEHDL craches and corrupts connectivity file when using Modify command extensivly.( P* s8 P( h. W, w
1 y' ~. T8 C! ?0 y; X4 R: M9 bDATE: 08-31-2011 HOTFIX VERSION: 005
& N0 a: c) W; d; U1 t& j* l===================================================================================================================================* e( C. M$ n# d; v6 P! C- q
CCRID PRODUCT PRODUCTLEVEL2 TITLE) y6 l3 u% Q3 m ?$ e3 i2 i0 T
===================================================================================================================================- o# B* u' T, W- A0 A
825848 ALLEGRO_EDITOR SHAPE Shape not filled when edges from 2 RKO shapes touch around mouting hole7 q4 i/ H6 j' K. d p
837723 CAPTURE PROPERTY_EDITOR Occurrences of external design not related to current root should not show. z& f$ F0 ]4 A5 R
891079 CONCEPT_HDL CORE DEHDL crashes with large number of commands in Winodws mode
8 z( u2 @4 O, U8 ^910908 SIG_EXPLORER OTHER Cannot open top if Tx AMI dll name contain more than 2 dot.. V2 X- Z6 s8 E ~+ d8 R# @1 Z4 W7 C
914036 CAPTURE LIBRARY ENH: Option to delete a corrupted part from a library and leaving other parts intact in the library.
$ V% q6 s& ~/ [! K+ o# r914679 ALLEGRO_EDITOR INTERACTIV Custom toolbars are not retained when switching between brd to dra and back to brd file using the File > Recent Designs
6 h8 n2 B% L# j4 O2 P914870 MODEL_INTEGRIT OTHER mergedml fails to merger 2 DML files from the model integrity
; I- v+ `2 a0 ]- z) f# q915645 ALLEGRO_EDITOR MANUFACT Allow the user to place the cross-section chart at a desired location
+ t, H5 T8 f1 J7 z% E2 a# Q4 [- a915653 ALLEGRO_EDITOR INTERACTIV unable to delete non-etch shape
7 S! E% h" q h915711 ALLEGRO_EDITOR MANUFACT dimensioning tolerancing by limit not working4 C. f# P' t# m `( d5 ^+ |
916321 CAPTURE GEN_BOM letter limitation in include file$ I- q* C2 ^" z) r+ q
916907 CAPTURE SCHEMATICS 揂uto Connect to Bus� should place the wire through non-connectivity objects
$ h, v; z8 ^7 m0 K1 x920327 CONSTRAINT_MGR ANALYSIS The TotalEtchLength predicate in Constraint Manager does not work for a netclass with a bus.
' `8 O/ v: n! Q. `2 Q4 ^/ A8 v920753 ALLEGRO_EDITOR GRAPHICS If I confirm to padshape with zoom-in after install the s002 It was changed to wrong shape.* i7 K( E* @6 _# x6 f7 ]
921097 ALLEGRO_EDITOR GRAPHICS Padstack seen partail filled when Zoomed in even "static_shapes_fill_solid" is set
! a* n+ M$ N# R5 W. F C921226 ALLEGRO_EDITOR DRAFTING Unable to select Package Geometry class when dimensioning in the symbol editor.
1 X5 q [/ M- d; S& `921623 ALLEGRO_EDITOR GRAPHICS Bug : Symbol not visible when zoomed in 16.5 S002
) _+ r$ D% ~3 N921891 ALLEGRO_EDITOR DRAFTING dimensions are lost after downrev(ing) a SPB 16.5 design with associative dimensions& \5 [5 X" D% u# ^ |3 B$ j# r
921937 ALLEGRO_EDITOR COLOR Padstacks with shape symbol are not showing correctly( G3 @ U. t3 h# C' G/ c0 E2 j% ?% D
922066 CONSTRAINT_MGR ANALYSIS Custom measurement Actual not being cleared when layout changes.
: C( L; y7 _7 g2 A2 `- Y922117 PSPICE PROBE Label colors are not correct in Probe
& N+ t& G: h+ ~2 {! ^& }922519 ALLEGRO_EDITOR SKILL add_bviaarray command fails for some clines but not all
+ M; s* ~& x" @1 J0 ]923224 ALLEGRO_EDITOR GRAPHICS Thermal flash Display problem in Allegro v16.5 Hotfix S002$ b( O2 q2 |2 e8 U1 u
923286 CAPTURE DRC DRC markers not reported for undefined RefDes- F$ f3 R! W- T7 F V6 c
923362 ALLEGRO_EDITOR PLOTTING Print to Postscript file not correct in 16.5
9 P1 |6 p) _; J& [% F$ t v6 f923416 ALLEGRO_EDITOR PAD_EDITOR Pad Designer crash on clicking on the Arrow before Soldermask_top+ g) }; G6 E6 Z* C
923507 CONCEPT_HDL CONCEPT-PCBDW The function of Import Design in the SPB16.5 Design Entry HDL (for data of ADW15.5_S23 + SPB16.3)
& X% j5 X8 x! H+ u5 |- e9 }1 ^1 J923910 CIS PART_MANAGER Copy & Paste operation from Part Manager copies properties only to first section of the part.
* |. d0 A8 F. D) w- s923913 CAPTURE PROJECT_MANAGER Capture runs slow on attached design6 N8 ~5 z) ^) h6 Z* A9 Z
923937 CONCEPT_HDL CORE Back annotation time significantly increased with the metadata generation on
4 u) i! ^! m" w P923949 ALLEGRO_EDITOR INTERFACES Incremental DXF_IN gives 'Invalid subclass' error% @ }# W: B# N; K" [; |
924458 SCM OTHER Project > Export > Schematics crashes
! o4 |) I5 Y* n$ k924621 ALLEGRO_EDITOR SHAPE Dynamic shapes are disappearing upon updating them to smooth.
, R a k$ K0 Y, a Y2 j925193 SIG_INTEGRITY FIELD_SOLVERS Diffential Impedance (DiffZ0) values computed in the layer stack-up is incorrect
2 \$ m1 s: x+ x925195 ALLEGRO_EDITOR DRC_CONSTR Incorrect pin to shape DRC error$ |& J E- C7 n5 f! T( o
925338 CONCEPT_HDL CORE This application has requested the Runtime to terminate it in an unusual way. M5 @$ @0 A4 C
925435 CAPTURE TCL_INTERFACE Capture crashes if 揝ave design as UPPERCASE� option is disabled.3 b( l$ R, n2 S" c4 u' e
925530 SIG_INTEGRITY OTHER Why the single line impedance value for Top and Bottom layers are different for this design?1 ]" W b5 C* `3 p* o
925864 ALLEGRO_EDITOR DRAFTING Ability to add dimensioning to different CLASS/SUBCLASS& l( ^! j4 J4 G# T! l3 `
925976 ALLEGRO_EDITOR MENTOR mbs2brd fails to import data) A, B( h6 V2 c' h$ p8 f- L
926409 SIP_LAYOUT DRAFTING Exporting a 16.5 design to 16.3 will cause the leader/dimesion lines to be removed.' U, }. L* W* Y2 _- ?* n* G
926443 CONCEPT_HDL CONSTRAINT_MGR In new 16.3 "035" ISR Concept2cm will crash with error.
4 j0 Q' @" x0 e5 I926503 CAPTURE GENERAL Memory leak Capture/Pspice
" A7 `$ v8 z6 X& K4 ?926553 CONCEPT_HDL CONSTRAINT_MGR CMGR ERROR There is no net in the Cset that has pins matching those in net 1 in the Xnet
7 A+ E' I4 [. \6 |/ F) v926691 ALLEGRO_EDITOR OTHER Crash while Importing Technology File in CM, with Overwrite Constraints.- T' v6 c5 p2 q, D$ N9 P
926887 CONSTRAINT_MGR CONCEPT_HDL Pin pairs lost after Export Physical5 l! Z/ a3 s) y7 T5 N0 s m$ \
927159 CONCEPT_HDL CONSTRAINT_MGR Export Physical fails due to errors in ConCM.log when SIGNAL_MODEL injected property is ''
, M$ |$ J7 y, y! [: J
E6 G# U& r) D7 ?' x3 Z+ d$ ]DATE: 08-19-2011 HOTFIX VERSION: 004
2 S3 @# q/ ^5 a. L2 V. s7 N, B$ F===================================================================================================================================( f5 b$ b; }, ]9 w* [
CCRID PRODUCT PRODUCTLEVEL2 TITLE: c8 G) A3 U y
===================================================================================================================================
4 @$ i7 g; y! `785417 CONCEPT_HDL COPY_PROJECT copyprojectui crashes with a Windows runtime error
4 Y2 D1 i( A- {6 |: ?0 I" N851044 CAPTURE GEN_BOM "Export BOM report to Excel" does not appear in the Standard Bill of Material Window.
2 W2 c. ~% F) w* z7 J4 B868216 PSPICE MODELEDITOR Encryption of subckt names, internal nodes, comments
) Q: k7 W4 o$ _3 o$ |870247 PSPICE SIMULATOR Encrypt a model and simulate it, info about inside nodes being dumped in the probe file
2 R& \; X8 L: j* a7 k/ Z877091 CAPTURE SCHEMATICS Save JPEG, GIF, PNG and other image formats in the database in its compressed form9 i: J% |& M' [
894059 CAPTURE OTHER Enhancement: Adding column in edit>browse>parts window
8 `' I0 ?! W* N+ D) {& }5 v- r895902 RF_PCB OTHER Alphanumerical allegro pin numbers are unusable in ADS 2009 Update 1
3 e$ U8 a& G1 K6 T' D895919 RF_PCB OTHER Round trip Allegro to ADS to Allegro requirement, n4 W: t/ R1 r3 R1 V5 X7 U% n
903102 ALLEGRO_EDITOR OTHER Zcopy shape command for cline seems not to work correctly.( G) f. W! a" L. f( h: x
905562 SIG_INTEGRITY SIGWAVE Noise margin seems not to be measured correctly with Eye Measure function.
2 |8 E+ F! K- G/ z% F+ }' A$ G909469 SCM TABLE ASA crashes when opening project
K$ b3 Y, S9 d2 G3 }- |909595 APD LOGIC Inconsistency between export die text out and show element after pin swap
. v$ Q2 F/ ?/ w) W( L/ ]# ~; Q911123 CONCEPT_HDL CORE 16.2 Design uprev to 16.5 fails with ERROR SPCOCD-152) E4 y& A H" d$ m* x
911569 CAPTURE EE_INTERSHEET_RE Q: Why is capture assigning incorrect Irefs in attacehd design ?
7 f' [# I1 b. M915657 ALLEGRO_EDITOR OTHER Allegro PDF Publisher Mirror capability- e9 V5 e+ b; L7 Q) t
915755 CONCEPT_HDL CONSTRAINT_MGR Cannot view net in SigXP, _2 Z' _; C# O5 H6 U$ p" ^9 i
916062 CAPTURE GENERAL Auto Wire Crashes Capture; ?* h" M) y j0 L+ k
916820 F2B OTHER RF create netlist with problem
" e$ [% H3 W! I# J* J917967 ALLEGRO_EDITOR REFRESH Update symbol resets refdes location for bottom side components only.
4 {) s* X$ n3 v919343 ALLEGRO_EDITOR PLACEMENT Place Manual is crashing the board file
$ P$ V) q G! O ]- r; i: d919481 CONCEPT_HDL CHECKPLUS CheckPlus isGlobal function is not working
c5 O/ ?3 D$ ? p" u919510 CONCEPT_HDL PAGE_MGMT takes 10 min to insert page in DE HDL
$ _3 c, ]1 T: x" g! x% W5 k919976 APD DATABASE Update Padstack to design crashed APD.
# N' A& n. i/ A2 s; K* q+ l" h920418 SIP_LAYOUT OTHER SiP enhancement to Auto Assign Pin Use to add ability to change the pin use definition) E) h3 ~2 L. t8 S! w9 n# V
920420 SIP_LAYOUT LOGIC SiP enhancement to Logic Auto Assign Net to display a dialouge Auto Pin Use assignment should be run
' k8 Z8 t& t" d: K920712 ALLEGRO_EDITOR ARTWORK Program has encountered a problem ... error when creating artwork; k; q6 x5 _( g
920763 ALLEGRO_EDITOR ARTWORK Soldermask gerber missing thru-hole pins
$ b' ^( t Z7 M- g" f4 d/ A920976 ALLEGRO_EDITOR GRAPHICS Question regarding the difference in the behavior of 3D Viewer w.r.t. height_min* C6 i A% N( p% I
920993 ALLEGRO_EDITOR DRC_CONSTR Minimum Metal Spacing Error is detected on Same Net
' F% Y" z+ u+ g* Q1 b2 h: m921727 ALLEGRO_EDITOR DRC_CONSTR Pad Boundary causing P/P drc to adjacent symbol.
( M/ Q" I1 w+ S/ W6 \/ N# `922579 CONCEPT_HDL CORE Xcon file gets corrupted upon Save of Hierarchical design with Global nets tied to interface nets
. K$ V9 }: ]) u7 H1 f9 \922592 CONCEPT_HDL CORE DE-HDL does not report illegal connection when Global Net tied to interface net using an Port symbol and named
* x, n, w( b0 g! w. f4 X8 N922758 ALLEGRO_EDITOR DATABASE Allegro crashes while placing second mechanical symbol with route keepin5 I/ a' ^9 A* R8 `8 c
922839 ALLEGRO_EDITOR DFA The DFA drc display is unstable.4 @/ d. e q; }
923293 ALLEGRO_EDITOR INTERFACES File> Export> IDX is failing for this design while creating an empty error log./ ]4 H, D" r1 x7 w0 p
924772 ADW PCBCACHE Import Sheet is not bringing in Parts used in the source pages into target cache ptf; M$ M7 c, F _; \$ ~4 S i6 `! ~
# @: S. }6 k6 @8 kDATE: 08-4-2011 HOTFIX VERSION: 003" A6 `; K# S) @. {! W2 a& G" ]- y
===================================================================================================================================
b; |! D" N& `4 q5 qCCRID PRODUCT PRODUCTLEVEL2 TITLE$ A0 p) T: w+ r. l# E- L+ {5 `
===================================================================================================================================
/ [: h! P# t& G7 W2 ]+ v787414 CAPTURE PROPERTY_EDITOR Part value can抰 be moved on schematic if a part has been copied to a new design and not saved yet.
4 b u/ u( H4 E D0 L, R903898 PCB_LIBRARIAN GRAPHICAL_EDITOR PDV move symbol graphics and Undo causes corruption in graphics0 y, C& r7 C9 j: v M+ e5 I s
904287 ALLEGRO_EDITOR ARTWORK some cline with arc is missed, when creating artwork.2 A0 n3 q8 z# |- o
904418 CHANNEL_ANALYS SIMULATION channel analysis sim does not give valid result2 Z) B7 P$ m1 i( H' U
905777 SIG_INTEGRITY SIMULATION User gets popup message that halts an analysis until it is acknowledged/ j7 T6 [) f* g$ `8 o2 s) j5 T
906139 SIG_INTEGRITY OTHER Bus sim result were cleared at the next run even if no preference changed.
- W# @: t5 D) C! f" h908680 SIG_INTEGRITY OTHER Extra prop delay due to resistance
) r0 Z7 _3 C, Y9 S2 S. e909583 ALLEGRO_EDITOR SKILL axlPolyOperation AND operation is not working correctly.8 X; V# h8 f* K1 g9 E4 W' L; I" n
910315 ADW LRM Import Design with ADW causes partmgr and pxl errors) i% v% h2 S: ?; {+ \! w
910689 CONCEPT_HDL CONSTRAINT_MGR NO_SWAP_COMP warning after uprev to 16.5
3 O3 k6 _5 x; a( { k, j- E911684 CONCEPT_HDL CONSTRAINT_MGR Attribute Definitions are incompatible for attribute 'HEADER'. when attempting to place in 16.5' l& z b, n0 D/ p4 T Z: _- U
912343 APD OTHER APD crash on trying to modify the padstack
; @( Z1 ]: Z) C) y912384 PCB_LIBRARIAN CORE PDV Symbol Editor often freezes when moving groups objects by arrow keys" _& }& U6 ], z3 D) W- m! Y
912853 APD OTHER Fillets lost when open in 16.3.
1 j: O2 e% f' y& O) `" A913586 ALLEGRO_EDITOR ARTWORK Cannot create the drill figures in this design.9 j/ d4 a# H/ M
914009 ALLEGRO_EDITOR DRC_CONSTR Diff impedance worksheet showing almost zero impedance for differential pair in attached testcase.) N3 A! M) _ `' c4 H3 d$ N
914110 CONCEPT_HDL OTHER DEHDL 16.5 Uprev overides property values on hierachical blocks
5 }/ V/ }& z) {! _: U `5 M5 k$ Z914264 F2B OTHER Cross Probing from DEHDL for global nets present inside block doesn抰 highlight in PCB Editor.
8 h+ @" u' o; H6 D914309 CONCEPT_HDL CORE 16.5 DEHDL crash on saving the user design
+ T2 R2 ~/ z, [; B( y, Y914558 ALLEGRO_EDITOR ARTWORK Gerber6x00 output creates unpainted niche in a shape* O: w6 `9 b2 \: J
914633 ALLEGRO_EDITOR ARTWORK Artwork failing in v16.5 while the same design when downrev'd to 16.3 is working fine.
1 O9 E3 E/ V1 v4 z4 \914634 ALLEGRO_EDITOR SKILL IsThrough flag for a padstack is reset1 o0 d! M# I7 i% j
914746 ALLEGRO_EDITOR DRC_CONSTR DRC Update repeats takes longer on each successive pass.
# t1 v+ G# \* U+ `* z914962 ALLEGRO_EDITOR SHAPE Corruption with Shape filling, U. g* U: ~/ C( Q
915583 CONCEPT_HDL CORE performance issues in 16.5 compared to 16.3
3 H- d. H. X. v8 a9 k& z' j915630 PCB_LIBRARIAN OTHER Error when running SI Model Interface Comparison using IBIS models2 T; D7 x$ Q/ b
915742 CONCEPT_HDL HDLDIRECT I get a newgenasym error and crash when trying to save the symbol& z9 ?: ^5 \2 \9 u& {! L4 a
916154 SCM NETLISTER scm crashes when exporting physical database to allegro
5 r' p: ]; u A O8 l l D" L916448 CAPTURE NETLIST_LAYOUT Capture 16.5 Layout netlist contains errors
6 Q8 { q9 _$ N+ Z7 ~6 E916462 ALLEGRO_EDITOR DATABASE Edit>Split_plane>create hangs Allgro PCB Editor* e7 q( T7 `, v8 Q7 ~" s
916469 ALLEGRO_EDITOR REPORTS One Unrouted pin does not show in Unconnected Pins Report
8 Q3 t3 h8 S5 G3 D3 A916495 ALLEGRO_EDITOR INTERACTIV Pick selects components from invisible (Off ) layer
3 [/ b7 e, h8 h' G916889 CAPTURE NETGROUPS How to change unnamed net group name?% D2 Z, y& _9 G
917002 ALLEGRO_EDITOR OTHER Allegro PDF Publisher creates extra circles not available on film
- {8 T2 s) I4 k. G5 }1 B8 S% g917434 APD OTHER Stream out GDSII has more pads in output data.
' a& W1 n2 E& ^$ V. d917739 CONCEPT_HDL INFRA Global Net tied to port is getting split into 2 nets in 16.5, in 16.3 it is treated as a single net' {7 Q$ w" C0 e' @: S9 H. g! j
918187 CONSTRAINT_MGR OTHER Missing acGetTotalEtchLength predicate.
1 D# f3 J9 ~$ s- M- M* |# m918576 CAPTURE DRC Incorrect DRC is reported for visible power pins which are connected to power symbol% e4 d5 W& b# O4 C5 O% h/ C
+ B1 `) n2 A2 Y0 j8 _1 G$ N
DATE: 07-24-2011 HOTFIX VERSION: 002
0 w- D }3 L$ B3 l===================================================================================================================================, F: g0 x8 [' W
CCRID PRODUCT PRODUCTLEVEL2 TITLE
5 H9 c, ~0 }$ Q( }" J f' U===================================================================================================================================
/ z7 }7 S- A1 |3 z( T' ~527444 ALLEGRO_EDITOR EDIT_ETCH Slide command needs to be enhanced for same net spacings
- d4 ~! R0 c# Q# w583257 ALLEGRO_EDITOR EDIT_ETCH Add Connect and slide command needs to be enhanced for same net spacings.# ?/ v; x Q& w/ D. i& T
592956 ALLEGRO_EDITOR EDIT_ETCH Same net traces will not push and/or shove each other.
7 }6 b1 v7 h8 H3 u745285 ALLEGRO_EDITOR EDIT_ETCH Requesting a true "shove" in Route > Slide for Same net routing.
4 t: Z1 \' w/ h3 d2 d0 ?773503 CAPTURE OTHER Doing "Mirror Horizontally" creates extra un-connects or extra junction dots in Capture V16.3.
: {2 n7 K4 ]6 d9 _774270 F2B PACKAGERXL Require to ignore space in Pattern setting to prevent duplicated Refdes.
' k/ u# m w# \1 V/ Z7 j. H799984 ALLEGRO_EDITOR INTERACTIV Enhance the Fix command to select just cline segs
2 P: z' S4 o7 P; V9 t% i) }) a809008 CAPTURE SCHEMATIC_EDITOR New nodes get appeared within the design when we select the design and do "Mirror Horizontally".
* o2 A. A) P* k+ I810058 CAPTURE SCHEMATIC_EDITOR New nodes get appeared within the design when we select the design and do "Mirror Horizontally".7 L' V! L0 b2 `& X# J& R) d
821133 ALLEGRO_EDITOR MANUFACT Output artwork for pad data that are suppressed unconnected pads with Gerber 6x00 format
$ V+ Q# d2 ]0 g" `831710 CAPTURE SCHEMATIC_EDITOR Capture adds extra junctions to design by itself
& c# M2 `& J, r* Y6 L+ M842410 ALLEGRO_EDITOR EDIT_ETCH Ability to slide with "Shove" for "Same Net" segments/vias.& B3 W, ?* i! ?0 Y' K
854971 ALLEGRO_EDITOR INTERACTIV Capability to add cline segment in a temp group% C8 H5 J! E/ f9 G
860772 ADW PCBCACHE Save Shopping Cart (pcbcache) is crashing component browser* m& d, {: p' T% V l2 ?) b
867842 CAPTURE PROJECT_MANAGER Capture crash with 'Open File Location"5 B" \' h; ]2 m# G
868306 CAPTURE CONNECTIVITY mirror vertically removes junction creates extra nets7 [. H3 ?. F u+ C- R: D9 P% r
882677 EMI RULE_CHECK bypass_plane_split fail if BYPASS_XXXX_EFFECT_DISTANCE
3 i. S/ N7 w( O: U+ _- R; Z! l8 Q891439 ALLEGRO_EDITOR INTERACTIV moving cline segments
% s* t* f( ?0 J6 z( Y8 E4 s) ^) y893544 ALLEGRO_EDITOR INTERFACES IPC-D-356A netlist issue with BB vias.
+ Z4 J' V! o- ~' j; ?9 O893765 ALLEGRO_EDITOR PARTITION Mail command not sending out email on Linux platforms.
0 h- T1 n2 x$ n6 `1 N ^7 Y. y5 C894390 SIP_LAYOUT EXPORT_DATA Generate all balls in the xml file for export to EDI's readPackage command$ ^+ v# J1 o& D0 v" ?. i" d
895933 APD DATABASE Update Symbol shifts the center of the Dynamic Fillet and creating DRCs! G1 ^* { M+ p L8 ?
896598 ALLEGRO_EDITOR PLACEMENT error message is misleading
8 J1 C% H6 H* s% _* o+ I: }897196 CIS LINK_DATABASE_PA Schematic Contents are not shown in CIS window while link Dbase part for parts placed from library
% j% \8 Y; d3 q898598 ALLEGRO_EDITOR MENTOR Negative planes from Mentor Board Station not being translated.
' c9 T1 G1 d5 g4 s9 \2 W' `899556 ALLEGRO_EDITOR ARTWORK Import artwork seems not to work correctly.3 f9 O. s; s# T B
900501 ALLEGRO_EDITOR PLACEMENT "lace Replicate Apply" is showing lot of DRC's during placement of replicated circuit in 16.5* j7 ?1 a, H; p0 s
901141 CIS EXPLORER Japanese character appear garbled in CIS explorer window.
& Z; j$ E5 U; F5 j! W+ j1 x2 w! P& a901666 CAPTURE OTHER Home page of Flowcad-Switzerland and Flowcal-Poland is not preserved on captre restart on start page
. L) R4 J* ]8 N902066 ALLEGRO_EDITOR DRC_CONSTR Shape in Region not follow the constrains
8 D( R) i0 L4 _902349 CAPTURE LIBRARY Capture crashes while closing library" p. L: f( x6 v$ l" Y5 O
902508 F2B PACKAGERXL SPB16.5 Packager-XL consumes much more memory than 16.3
& f2 g! T2 E( Q, {902841 CAPTURE GENERAL Capture Start page does not show
2 X/ x1 B& a2 Q! ?9 p902876 F2B PACKAGERXL Packager fails on the design upreved in 16.5
. R( }9 k+ @2 }4 \902959 CONCEPT_HDL HDLDIRECT HDLDirect Error while saving design
/ F1 B7 z3 U3 N903171 PSPICE NETLISTER Why Capture is treating hierarchical power ports as floting nets in complex heirarchy designs?
e3 o! ?2 ]+ d' {; T$ q903713 ALLEGRO_EDITOR PARTITION Placement Replication do not work fine in the Design Partition
`% T+ d& {3 E9 Q, D7 R6 N903799 SIP_LAYOUT DIE_EDITOR Disappear die pins after exiting co-design die editor& G" l3 Z( v! ~9 B
904021 ALLEGRO_EDITOR OTHER Export PDF from SPB 16.5 produces a file not text searchable- T6 J6 T8 r+ H9 P/ g7 s. h7 u( a
904339 CONCEPT_HDL CORE new design crashes using the attached CDS_SITE7 q$ f% ]; ]- @
904522 F2B PACKAGERXL Part will not package in 16.5 but packages in 16.3/ R% J6 u% L$ c( {
904764 APD OTHER Enhance Scale Factor of Stream Out to support 4 decimal places l& `1 n8 I4 X- h, Z
904771 ALLEGRO_EDITOR MANUFACT Pin Number display issue.) \ [0 R% S* F4 u% g0 V/ K. E( i
904853 ALLEGRO_EDITOR GRAPHICS Enhancement for showing Static shape as it was seen in 16.3
- P Q q I% M7 U" Q0 I. t905144 CONSTRAINT_MGR ECS_APPLY Min Line Spacing is larger than Primary or Neck Gap less(-) Tolerance but No Warning in CM4 `7 [; q) ~9 q& x4 J
905314 F2B PACKAGERXL Import physical causes csb corruption
/ _- s6 T u! f905337 CONCEPT_HDL CORE ConceptHDL crashes after Import Design process.
2 c# V$ o6 c8 q$ b9 X905533 ALLEGRO_EDITOR INTERACTIV Pin numbers for components on BOTTOM Side are moved in Preselect mode,when the BOTTOM layer is invisible
9 J7 P5 D; _8 l, \9 O% e; t- }8 I905796 CONCEPT_HDL CONSTRAINT_MGR Fujitsu CM issue inaccurate concept2cm diff pair issues
! F" u: H) d, T) S P905811 CAPTURE EE_INTERSHEET_RE interesheet references in the form of grid grid page number instead of page number grid
6 r& f7 S9 Y' a' u+ X3 s906118 CONCEPT_HDL CONSTRAINT_MGR Cannot open CM if SIGNAL_MODEL value was not assigned in ptf.
! v2 {. t! m# |3 {6 y+ P! ~906153 ALLEGRO_EDITOR SCRIPTS Unable to run allegro script in batch mode on the attached board.
# N L K1 d# F& G) o906182 APD EXPORT_DATA Modify Board Level Component Output format
: \: h* m. C8 n7 p3 G906200 ALLEGRO_EDITOR DFA Enh- DFA drc invoked in Batch mode returns false constraint value in Show Element
$ {7 u' p1 v* X7 @7 F906517 PSPICE PROBE PSpice new cursor window shows incorrect result.
6 {. m9 b M# ~ w4 m906627 ADW COMPONENT_BROWSE ppt options are not read if ucb is launched from FM. works fine if launched from dehdl.# ]8 \( t# y* Q) J* d$ n Y" t
906647 SIG_INTEGRITY LIBRARY lib_dist creates a signoise.log in current directory (with backup files like ,1 ,2 etc.) on each run
) \; p. k" w; c* [' [2 ~906673 F2B PACKAGERXL Ignore the signal model validity check during packaging
$ I" g; J" x; H: q, n906688 ADW LRM A copy of source design gets created in worklib of target design after 'Import Design'
" g8 c2 F7 F7 s4 k/ D906750 ALLEGRO_EDITOR PARTITION Importing design partition removes the testpoint reference designation
! R. |( V/ |" H/ `4 B906874 PSPICE NETLISTER Error less than 2 connections for unconnected hierarchical pin
2 a7 w2 j6 @1 L9 h907095 F2B OTHER Part Manager does not show Error as Undefined when directive ptf_mismatch_exclude_inj_prop is used
2 z5 |( n- {8 C6 U, x7 @" f0 n907424 ALLEGRO_EDITOR GRAPHICS Allegro add option for pre 16.5 shape display
' f% t U: R L. Q/ R: p7 z907490 CAPTURE NETLIST_LAYOUT 16.5 Layout netlist is not correct. It differs form 16.3 layout netlist.
( T8 X6 w( b. F9 j$ B% m8 {/ D907884 SIP_LAYOUT MANUFACTURING Need to add an "NC" pin text option for "Manufacturing Documentation Display Pin Text"! D% C6 a7 a' \
907885 SIG_INTEGRITY OTHER Matchgroup targets lost when importing netlist to Allegro layout in HF314 x0 V5 [) j7 X* d3 w/ d. v! w
907929 CAPTURE TCL_SAMPLE TCL command to delete a property from parts in a library is not working correctly9 E: H4 x. p# F8 `& p
907933 SIG_INTEGRITY OTHER Single line impedence not working in OrCad PCB Professional
( m$ V$ z0 y' a4 s; B3 S907963 CONCEPT_HDL CORE Design uprev issue when moving from 16.2 to 16.58 m4 b0 { d% |
908000 SIG_INTEGRITY OTHER Inconsistence z-axis delay reported on Tpoint when define at via location.4 s2 f* _& W9 h1 J4 t% k
908057 CONCEPT_HDL CORE DE HDL crash with the cut and paste of a signal name7 N' [0 t4 Y3 Z9 I1 y) ]2 J1 \) J
908060 CONCEPT_HDL CORE CTRL+LMB Option not working correctly in 16.30 ]( i2 j3 a. n t p' o
908210 CAPTURE CONNECTIVITY Connection is being lost while dragging a component
w) |: i; c% H8 E908241 CAPTURE DRC DRC error column is blank in DRC markers window in 16.5
, N4 V+ i2 Y. ?908339 RF_PCB BE_IFF_IMPORT mechanical holes VIAFC are not at the right place y9 v) V! B% \' o: J2 B
908534 SIP_LAYOUT SYMB_EDIT_APPMOD issues with symbol editor and copying pin arrays9 X6 g3 M, f" I2 |; B
908535 F2B DESIGNVARI When I try to view my variant file the variant editor crashes% L; `( R R$ J6 g
908595 APD 3D_VIEWER cadence Design 3D viewer" screen pops up and is all black because the colors have all converted to b- v6 x! l" @6 d' i
908849 CAPTURE ANNOTATE Getting crash while annotating the attached design
. R6 K H, ]3 U2 P/ N908874 CONCEPT_HDL CORE Part Manager - No Part Found error when using CCR# 775788 feature
2 D. a) k ~3 q" a2 w6 f K909077 CONCEPT_HDL CORE After packaging pin numbers remains invisible even when $PN5 z: ]/ m5 w- I# o0 u4 F( i# A$ n
909104 ALLEGRO_EDITOR SYMBOL Warning message needs to be modified. It does not save the symbol and also not tell the actual problem.8 I: v" C9 C& B2 ]& c( N1 }6 T) D, }
909417 ALLEGRO_EDITOR REPORTS "report -v upc" returns 'Segmentation fault' on Linux
- F7 | s# @2 t6 U6 G909635 SIP_LAYOUT DIE_STACK_EDITOR Add Interposer crashes in SiP Layout8 m, q) F1 A, A* d( j
909749 ALLEGRO_EDITOR MANUFACT Allegro Crash during dimensioning
: G* ?" x% q% |2 q) t909760 SIP_LAYOUT MANUFACTURING Create bond finger solder mask doesn't follow the mask opening as defined in the padstack
$ V" S5 D/ {. W4 O$ G! b909861 F2B PACKAGERXL NetAssembler broken within the latest 16.30.031
6 y% h- a4 w7 D6 W- H910006 CONCEPT_HDL INFRA Motorola design fails to uprev from 16.3 to 16.5, xcon file is getting corrupted., E5 t0 h' a2 F4 `
910141 CAPTURE NETGROUPS Modify NetGroup definition does not update Offpage Connector
! U$ x6 |" {( b9 d4 i9 @910340 ADW LRM Import design in schematic, only 1 page import, the entire block is getting imported.
{! q F* ~$ s8 {910678 SIG_INTEGRITY OTHER The Analyze> Model Assignment> Auto setup is not creating/assigning models to discrete components in 16.5
" g/ |: S9 a$ k& }910713 F2B DESIGNVARI Variant Editor crashes when you click web link under Physical Part Filter window.
% u2 p8 e- w& d$ \) i% s910936 F2B PACKAGERXL ConceptHDL subdesign net name is inconsistent
\) o" b( ?6 c911530 ALLEGRO_EDITOR SYMBOL Package Symbol Wizard does not create symbol with the name given6 C( F- _: a. [5 F) s6 M9 r
911631 CONCEPT_HDL CORE DEHDL crashes when opening a design, C8 v' c# X9 @" n
912001 ALLEGRO_EDITOR OTHER option_licenses entries are made in allegro.ini even when not set as default
, w0 e$ S" c' \$ R0 P912459 F2B BOM BOMHDL crashes before getting to a menu
& Q' B+ v4 L1 e, X! S) ]6 x1 S2 P" E913359 APD MANUFACTURING Package Report shows incorrect data
z N' _/ S, r4 w/ v
5 y& m" G4 w5 m6 G# bDATE: 06-24-2011 HOTFIX VERSION: 001
' ]) v; d- T' m===================================================================================================================================
. y+ s! S6 \* }. JCCRID PRODUCT PRODUCTLEVEL2 TITLE& V# j; K: M( ^/ m D- { m3 [
===================================================================================================================================
" a& n1 O$ H4 z5 V" o! I" w293005 ALLEGRO_EDITOR DATABASE Allegro crash when attempting to move mech. symbol
6 i/ C Q5 E) @% h- |4 ]+ R8 B1 K298289 CIS EXPLORER CIS querry gives wrong results
! }1 O: d0 T/ n366939 ALLEGRO_EDITOR OTHER Cannot attach refdes on silk subclass with add text# o5 x: [+ h+ Z1 M" J/ A) D% h
432200 ALLEGRO_EDITOR MANUFACT Fillets with an arc are required for Flexi designs9 ]. z, O+ w1 D+ p* N) n4 z% X
443447 APD SHAPE Shapes not following the acute angle trim control setting.5 k; o. E `3 [; {/ K& f9 V- U4 R
473308 PSPICE AA_SENS Passing variables to lower level blocks using subparam* i3 Y& X8 V) W9 |# w' C1 x
517556 PSPICE AA_SENS Advanced Analysis does not support variables being passed down the hierarchy
- Q! w& ]1 d1 H& W! v548143 ALLEGRO_EDITOR SHAPE Dynamic shpe on Etch TOP will not void properly." u! M8 \- w: ?, M; r
606959 ADW COMPONENT_BROWSE Key properties with blank values are not getting read in shooping cart
+ z( z* V. z/ ?4 Y616466 ALLEGRO_EDITOR SHAPE Solid shapes are not getting filled6 d# u1 t' p0 e
641358 SIP_LAYOUT DIE_STACK_EDITOR Request for Via and Multi Layer Pin support for DIE stack Area (blue region)) \* S$ E% s/ ^( N( S2 p1 M
644122 SIP_LAYOUT OTHER SiP Layout - xsection - ERROR Adjacent conductive layers are not allowed, but these are diestack layers not conductor! T2 u+ X5 o; I- y% d' O% |
645816 ALLEGRO_EDITOR SHAPE Slide a cline all removes gnd shapes on board
4 a7 H |8 ~! F9 J' m" a725355 ALLEGRO_EDITOR SHAPE User can not voided Logo correctly.$ N) B: z/ \2 [
763569 CONCEPT_HDL CORE Display status of Hide/Show unconnected pins icon in DE HDL UI5 S! H( p& y$ Z# U* S2 j4 }$ f
770021 CAPTURE BACKANNOTATE Changing pin group property after pin swap resets pin numbers5 A' b6 V4 [& ^. v4 _* ]* q/ q
792126 CAPTURE PROPERTY_EDITOR Attempt to change display for occ prop resets7 s( t, H0 Z0 z% V6 \
799014 CONCEPT_HDL CONSTRAINT_MGR concept2cm errors not shown in export physical after hier_write- z; H; l' H" x! h! V
803147 CIS LINK_DATABASE_PA Link DB part should not change RefDes of multi package part" ]) j) g( ?% i$ z4 O: C
804240 PSPICE DEHDL Problem in simulation result for a multi-section split part.# T* T: C' Z' ^# y8 j- T4 {
809118 CAPTURE NETLISTS ENH to compare two schematic Capture designs
4 }( I I @5 o3 \' Z$ i* b7 G q816568 ALLEGRO_EDITOR SHAPE shape disappears when update to smooth.. State no etch+ k0 _$ p% [4 j1 |
830053 CAPTURE STABILITY DXF export fails if schematic folder name as /
# k( V k. r. e) t. U" M; b832108 ALLEGRO_EDITOR SHAPE Shape void incorrectly.
2 q8 g6 o) y: x833542 CONCEPT_HDL CORE PDF publisher font is NOT WYSIWIG with respect to what seen in DE HDL
! M& o/ _: ?4 V! K% O835777 CIS DERIVE_NEW_DB_PA For XLS, donot display table as worksheetName$worksheetName to avoid 8012 error
# H. }+ ^/ k! f. v837640 CIS GEN_BOM date format of CIS BOM has broken macros of 16.2 in 16.3 version7 m5 d$ T4 w" I2 F8 u2 e
844074 APD SPECCTRA_IF Export Router fails with memory errors.9 H) Y0 f3 p1 B! i4 z/ ^
851595 CONCEPT_HDL CORE Pin numbers overlap on the pin and increase in size
- t8 O2 i* K! z3 w852832 CAPTURE BACKANNOTATE Why is Capture crashing with Mentor back annotation?# f! n* [, z2 i8 k) G
855015 ALLEGRO_EDITOR OTHER The rats are NOT connecting to the ends of the clines like they should be.. l1 ^8 e B8 x+ N
859883 CAPTURE NETLISTS ENH to compare two schematic Capture designs
/ x6 V# [4 m5 W3 t- g866009 SIG_INTEGRITY OTHER Net with Pull-up/down should not be used for Diff-pair.
3 u! |$ b, k: m" M% g- ]5 Q6 ^% {866830 SCM REPORTS Multiple lines added as separator between title block and report header instead of single line% s, ]* d9 l% ^" |: ^% w
866833 SCM REPORTS Extra indentation is left in the left side of the report when the Line Numbers are set to OFF5 l) r i H' }2 F" P4 W9 ~
868618 SCM IMPORTS Block re-import does not update the docsch and sch view
6 N1 p# ?4 q' n- y873402 SIP_LAYOUT LOGIC pin swap for co-design die in SiP
3 T7 P% M+ e# t* c' y `874010 SIG_INTEGRITY OTHER PCB SI crashes when the Xnet is extracted with VARIANT_TO_IGNORE property.
0 Q" e& \# w/ m! K3 n. b874400 ALLEGRO_EDITOR INTERACTIV Flip mode issue with move command5 R. ^; e7 A& Z$ V- c. ?
874966 ALLEGRO_EDITOR INTERFACES Placed mechanical component do not get Ref Des or part number in IDF file
2 `$ q' D5 N: w* m8 ^875709 ALLEGRO_EDITOR REPORTS Film area report generated incorrect data at l1+ p: f4 ~( K5 w$ c
876275 CONCEPT_HDL CONSTRAINT_MGR Constraint Manager not retaining target net, ~; o0 L5 V: K" a3 D
879361 SCM UI SCM crashes when opening project
& A: Z0 m3 O# }; I# e+ ]3 r879496 CONCEPT_HDL OTHER Customer wants to have the tabulation� key as separator in HDL BOM.
) i) S f! k+ {/ S5 u2 y3 p879514 PSPICE AA_MC Monte Carlo to handle equation as comp VALUE.2 N! L8 M+ m+ Q8 j* d7 J
881845 ALLEGRO_EDITOR SHAPE Delete island deletes complete shape; H% e) m, P! I' x
882413 PDN_ANALYSIS PCB_PI PDN Analysis should support routed power nets
+ b( f& V# v! @# H882427 PDN_ANALYSIS PCB_PI PDN Analysis target impedance should have a variable multiplier% G6 p4 n2 P" o1 ?
882567 SIG_INTEGRITY OTHER PCB SI crash if boolean type prop was specified to VARIANT env.
8 ~' G& k) r& u6 t% A$ h- N882644 ALLEGRO_EDITOR PLACEMENT PCB Place Replicate Function automatically match Enhancement
" ?: e0 b/ c6 L3 Z" ]883164 ALLEGRO_EDITOR INTERACTIV Vias marked fanout moves away from position when moving component/ u1 y: H; k& y9 l+ a5 N, ~
883224 SIG_INTEGRITY SIMULATION crash while reflection simulation from Constraint Manager& |5 e6 K1 D3 L) s0 f
883760 PCB_LIBRARIAN METADATA Incorrectly formatted revision.dat file in the metadata folder
) q/ v& a" X: c2 U1 m885391 SIG_INTEGRITY SIMULATION RLGC data sampling algorithm and w-element interpolation.
) E' O! t: _- o; T" `885849 ALLEGRO_EDITOR MANUFACT Silkscreen Audit cannot find Solder mask for the text string9 B: A4 _% w: z! ]
885996 SIG_INTEGRITY OTHER The effect of sn_maxwidthlimit user preference is not seen in cross section impedance calculations4 {; T( J; @# ?+ U/ B
886090 ALLEGRO_EDITOR INTERACTIV Add Arc w/Radius does not snap to grid
, i- D8 w @% r a5 C" Q( F887180 CAPTURE SCHEMATIC_EDITOR Signals Navigation window doesnt get updated for Buses
: ^# N/ m e6 M9 z p3 H$ }887442 APD SHAPE Copper pour of Dynamic shapes on Top layer which contains many existing signal traces fails.7 D( V; n6 B$ y; \8 ^& w$ A
887578 SCM AUTO_UI Component Replace pops-up the DSPANE-204 Message
4 V1 L' N7 M- `8 ?. l D887926 SIG_INTEGRITY GEOMETRY_EXTRACT Field solution failed if diff trace on bottom doesn't have reference plane.! T+ E, n% y! q7 w, o& S5 s- n( y
888414 SIG_EXPLORER OTHER View Trace Parameter display the thickness of dielectric incorrectly.
8 V: x+ ~2 p3 g# S3 O888600 CONCEPT_HDL CREFER Cross References not added to Schegen schematic
9 d$ m: v0 S! n& |" t$ Y5 u7 j888679 SIP_LAYOUT SHAPE Can't create the Dynamic shape on layer M1_sig without unwanted horizontal openings appearing.$ E8 X+ i% E" n/ S
888804 ALLEGRO_EDITOR OTHER Fillet will become static shape after import from partition board.
, Q$ x# \" i/ ?$ D# q888945 CONCEPT_HDL OTHER unplaced component after placing module* g- L ~1 y; b2 g. U3 g
889222 ALLEGRO_EDITOR SHAPE Allegro freezes/hangs when adding shape as Polygon with OpenGL ON.) Q% P/ V# f3 `$ i# Q/ A6 _
889365 SIG_INTEGRITY GEOMETRY_EXTRACT top/bottom trace impedances extracted to sigxp are wrong in 16.3, I6 }+ |- j* @/ G3 Q9 z
889404 ALLEGRO_EDITOR OTHER Incorrect pad size for Top conductor padstack written to column 59-62.: X1 r& K0 a e$ j+ w2 t& o/ |" Y2 x
889426 CONCEPT_HDL CHECKPLUS CheckPlus does not find single node net
* ]/ {. q# z* F$ V7 I6 H889636 ALLEGRO_EDITOR MANUFACT Incorrect spelling of "Visibility" in "Film Control" tab in the Artwork Control Form) z( G6 l& ~& p, n8 O6 X) Z: n
891235 F2B PACKAGERXL Packager crashes without creating a pxl.log file( @% i: T* d, f3 \6 I' C6 D
891292 ALLEGRO_EDITOR SHAPE arc routing causes weird undesireable shape fill performance& A* x! \& u% E' u
891856 ALLEGRO_EDITOR EDIT_ETCH crash when sliding diff pairs
7 o8 X$ W+ ~1 J: S+ B" H6 u892375 ALLEGRO_EDITOR PLACEMENT Place Replicate Update disband other groups, irrespective Fixed property added or not.
9 R# i6 s3 S. b, N7 C/ b5 B$ [+ B892455 ALLEGRO_EDITOR SYMBOL Why the overlapping pins are not reported with DRC?; f9 i* M* D$ }% i1 r
892541 SIG_EXPLORER OTHER Export/Import layerstack through the technology file is changing the layer thickness# l) l) E0 r' x
892766 APD WIREBOND Excuting Finger moving cannot push aside finger to move with together by shove all mode
o# y5 o" Y! f8 v892907 ALLEGRO_EDITOR DRC_CONSTR DRC not reported for etch_turn_under_pin violations
2 A+ f! c1 }7 y9 R, W. L1 W892963 ALLEGRO_EDITOR SKILL Bad shape boundary created after axlPolyOperation 'OR
! X0 s6 v& D; [3 z892964 SIP_LAYOUT LOGIC Request that Edit Parts List use Dashes "-".5 g$ b3 M! n9 c( b5 D: y
893295 APD WIREBOND Why move wirebond command does not shove wirebonds? This result in drcs.# a: D* F/ U0 a1 L: q2 ?
893706 CONSTRAINT_MGR OTHER On line DRC hangs on partitioned board% D2 F! \: N" B+ z: ~$ [! I3 f
893743 APD EDIT_ETCH Route behavior when spanning pads not as expected.
+ ~1 ~8 S7 b6 P6 P. a4 x& q8 y893783 SIP_LAYOUT OTHER Padstack Design Editing update File menu with a Update to Design and Close instead of 2 operation
3 k3 S3 w3 J& r2 k! z H894456 ALLEGRO_EDITOR REPORTS Request Net names be added to Propagation delay lines of the DRC report.
+ [/ d% r( D0 g2 s894499 SIG_INTEGRITY LIBRARY Tool crashes when moving a cline or selecting the Info icon with OpenGL on.6 Z: [+ _$ v9 }7 t5 a2 G
894582 APD SHAPE When making a dynamic xhatch Via shapes surrounding are abnormal.
$ T; a$ m: i6 ~" `895542 SIP_LAYOUT WIREBOND SIP design crashing when moving bond finger using blur mode BLUR_BONDFINGER_PRESRV_CON
. R; z& `7 r- D) q895591 ALLEGRO_EDITOR PCAD_IN Importing PCAD file fails to get to the point where we can map layers ?" R8 J+ a: ~9 X5 T
895757 APD ARTWORK Import Gerber command could not be imported Gerber data- P) U# ?+ X; w7 {
895964 CONCEPT_HDL CHECKPLUS The CheckPlus command getFileSubstrings is not working correctly
8 A$ _- p+ Y! t+ z- f896428 SCM UI Changed Ref Des value not maintained in DEHDL block when part is replaced& e/ W2 ]; }0 \8 _9 O
896655 CAPTURE EDIF Import/Export Design of Hierarcy design with OrCAD Capture
5 N. ]# S/ y: L2 d9 O- j* B896846 CAPTURE IMPORT/EXPORT Import edif2cap and capture is crashing
4 w6 ?( t1 z* {897155 ALLEGRO_EDITOR REPORTS Copper coverage in L2 and L7 looks like the same but film area report had large gap.( \. \% T' j% d+ p; |1 ]
897654 CAPTURE EE_INTERSHEET_RE Capture crashes on adding intersheet refernces in abbreviated format on attached design.- s) ]0 K8 g: }" z7 Z) b. H- t0 Y
899344 RF_PCB BE_IFF_EXPORT dlibx2iff does not provide the component boundary drawing8 v; H, w+ x. I9 s
899629 CONSTRAINT_MGR OTHER ECset for Total Etch Lenght is not present in OrCAD Prof
5 t0 f, U0 j% o900175 CONCEPT_HDL CONSTRAINT_MGR Few Xnets are lost from Match Group after packaging and importing the netlist to board file.
4 `1 i i7 b; b900481 CONCEPT_HDL CORE Genview creates a larger symbol without taking the no. of pin in consideration7 s6 v# p7 K! h* P0 \3 u6 u
900813 ALLEGRO_EDITOR DRC_CONSTR With rotated pads, pad (pin - via) soldermask spacing DRC is unreasonable.
i( W5 c2 F0 _: y900905 PSPICE STABILITY Simsrvr crash and RPC Server unavailable error while running simulation.7 L* ~! ^. S" N; ?4 E
901783 CONCEPT_HDL CORE CDS_PART_NAME is annotated on the schematic canvas after running back annotation in 16.5* [! k; F! V9 ?& c5 K
901909 APD EXPORT_DATA The "package_pin_delay_length.rpt" with Z-axis delay turned on seems wrong- k) E) j) J. {7 m' b b# e: X
901987 CONCEPT_HDL OTHER SPB16.5 zoom fit does not center the page while ploting the schematic page
y3 A0 U3 V& z902133 CIS OTHER The visible part property value are being shown very distant from part graphics on schematic Q3 E# y0 o) k1 |5 i
902166 SPECCTRA ROUTE Specctra crashes when reading in "bestsave.w" file G8 n" }: q* P. V
902170 ALLEGRO_EDITOR DATABASE Diffpair Issues with OrCad PCB Designer Professional
# R. U7 d. w: a- m. V- Z+ C; _902177 CONSTRAINT_MGR CONCEPT_HDL Option to view the layer thickness in CM worksheet through worksheet customization1 l$ ^7 Z h) i. ~# ?1 f
902463 ALLEGRO_EDITOR INTERACTIV APD crashes when we click ( show element ) on certain components' R* d5 Q# H7 D
902621 CONCEPT_HDL OTHER Design Differences (vdd) Crashes
2 W" t+ _# ^3 ^% Y* p' P8 r, \4 a) [902909 APD WIREBOND die to die wirebond crash% _8 [1 r( O; a' g, v1 h6 v. \
902933 ALLEGRO_EDITOR PADS_IN Pads_in fails while reading PADS ASCII file body/ r' w3 |8 B* {" F2 V# E3 P% b
903284 PDN_ANALYSIS PCB_STATICIRDROP IRDrop voltage gradients are plotted outside of the PCB outline! ?. c- Q" W& @, P+ g& m$ e; e
903680 CONSTRAINT_MGR ECS_APPLY Constraint Manager not passing all hiearchical member objects to a custom measurement.
! U/ R3 i( u, F( X5 U8 Z2 T904403 ALLEGRO_EDITOR DATABASE Allegro crashes when refreshing module |
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发表于 2012-2-21 14:58
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