Hotfix_$PB16.50.013

yulizi

http://kuai.xunlei.com/d/DGOHIFKLICUP
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. T1 |2 u; _1 ]$ v3 sDATE: 12-16-2011   HOTFIX VERSION: 013
4 Z3 @% F2 d) Y3 p, a===================================================================================================================================
CCRID   PRODUCT        PRODUCTLEVEL2   TITLE
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875695  SIG_EXPLORER   INTERACTIV       Enforce Causality check box doesn't work.
4 A8 }  b& `/ M- w9 u927148  CAPTURE        PROJECT_MANAGER  Capture crashes on creating scehmatic folder with name which already exists in design
938013  CAPTURE        NETLIST_OTHER    The netlist in RINF Format contained two identical lines for PCB FOOTPRINT
941409  Pspice         PROBE            BUG : Search accuracy wrong in new cursor window
945242  SIG_INTEGRITY  SIMULATION       Unable to select "shapes" in find filter for 'show parasitic ' command
946293  concept_HDL    ARCHIVER         Archiver hangs if there is a whitespace at the end of the path of cref.dat
1 x& I3 D6 j9 @& U- |946770  CONCEPT_HDL    CORE             揤iew Design?function is missing in Windows Mode after reseting the menus.
, z0 I" h1 ]- O) u  R7 }950994  CAPTURE        NETGROUPS        Problem in expanding the netgroup in Auto Connect to Bus function
4 z! E. r$ f/ _- e6 X+ J% O7 W953530  SIG_INTEGRITY  GEOMETRY_EXTRACT Display Parasitics is displaying wrong results for EMS2D Field Solver compared to topology extraction using Probe.
953713  CONCEPT_HDL    PAGE_MGMT        Random page replacement/duplication in block
953917  CONCEPT_HDL    ARCHIVER         archcore should handle errors correctly
953971  allegro_EDITOR MANUFACT         NC Drill files not generated correctly when using the option "搒eparate files for plated/nonplatedholes?
" x8 {) i- v8 r9 F9 G+ z954400  CAPTURE        NETGROUPS        BUS members of NetGroup are getting converted to Scalars in Export-Import NetGroup.
$ {/ @+ e$ E0 k" b9 E954498  SCM            B2F              SCM crashes when importing physical
1 _/ j; k3 q3 J4 l! o954623  ALLEGRO_EDITOR EDIT_ETCH        Unable to complete connection with Add Connect - related to soldermask to cline check?
954894  ALLEGRO_EDITOR MANUFACT         Dimensions disappear when opening database in v16.5 from v16.3
- ^+ F3 O- d* E955029  CONCEPT_HDL    CORE             custom text font size not recognized in symbol view
955133  SIG_INTEGRITY  FIELD_SOLVERS    The Field solver creates the differential trace model which is reversed T(D1) and T(D2) of bottom side.
955290  CAPTURE        DRC              Description for UPD0014 missing in the Browse DRC markers window
955299  ALLEGRO_EDITOR DRC_CONSTR       drc text to smd pin does not work any more on this database in 16.3 S039
0 c2 T* V* N  e! |/ i5 Y, ^4 C955338  CONCEPT_HDL    CHECKPLUS        Need to change PART_NAME
" d! V  Y. B, }3 ^; M. W955447  SIG_EXPLORER   OTHER            Model path set in DE HDL Model Assignment not used by SigXP from CM in DE HDL
955740  SIG_INTEGRITY  GEOMETRY_EXTRACT Crosstalk with Timing Windows does not work correctly
% n6 P$ g* F- B  F2 z8 g! J+ z955749  ALLEGRO_EDITOR MANUFACT         show element Info shows symbol dimensions on incorrect subclass
' E2 p7 a, J$ p& k( I3 A955912  ALLEGRO_EDITOR OTHER            Shapes with voids that are exported to PDF have gray filled area over the void
956129  CONCEPT_HDL    INFRA            DEHDL uprev hierachical design from 16.2 to 16.5 packaging failure.
956373  ALLEGRO_EDITOR NC               drawing name doesn't display in the log file
  T, A: I( M: q4 C956393  CAPTURE        PROJECT_MANAGER  "GENERAL" and "TYPE" tabs are missing from "Properties" dialogue box.
9 \) b/ K$ w5 c* o5 U8 T956448  PSPICE         MODELEDITOR      Can not generate a DEHDL symbol from Model Editor, because no Capture license found
6 Q- N% o. }! R3 j' f0 w956456  CAPTURE        NETLIST_OTHER    OrTelesis netlist not transferring user properties defined under combined
956489  ALLEGRO_EDITOR MANUFACT         dimensions lost when symbol with diemnsions attached to symbol origin placed on board
/ ]3 k/ w# k6 J' |! H956603  CONCEPT_HDL    OTHER            Part Manager "has stopped working" after changing a component
6 \6 ]2 C- J* N5 p( I956751  ALLEGRO_EDITOR ARTWORK          Import Gerber command does not work correctly
956847  PCB_LIBRARIAN  METADATA         PDV - Partdeveloper symbol to function linkage broken/changed in 16.5
956987  CAPTURE        OTHER            Find from "Search toolbar" doesn't gives complete results
9 |3 y2 Y1 ^" n1 {# a" K956996  CONCEPT_HDL    INFRA            Correction to ERROR(SPCODD-7): Following Primitive instance causes CM to empty
  c* h; c# S+ g" r) ^957009  CAPTURE        NETLIST_OTHER    Problem getting database property in mentor pads PCB netlist
957137  APD            DXF_IF           DXF out  command dose not work correctly.
957167  APD            GRAPHICS         Highlighting for Static shape with display_nohilitefont environment variable.
957232  SIG_INTEGRITY  OTHER            Allegro crash during Model Assignment.
5 h- M/ m. w& C0 c957267  CONCEPT_HDL    INFRA            Packager Error after Import Design
. ^7 Y* p8 H# ~8 S6 E957866  SIP_LAYOUT     DATABASE         Cavity outline is not getting deleted from symbol file
1 f2 S3 |- p, Y( x0 p958010  ALLEGRO_EDITOR REPORTS          Wants the ability to extract "Batch"  reports from Partition ".dpf" files.
5 X) a& Y4 k# F958252  ALLEGRO_EDITOR TESTPREP         Resequence testprep with the option - Delete probes too close crashes the design
5 D6 l8 M2 c8 Z% L958253  ALLEGRO_EDITOR REPORTS          Shape did not have thermal relief connected to pin but unrouted nets still shows zero.
2 f$ ]& F6 K, [4 Z$ q: y3 Y/ M4 S7 ^958433  ALLEGRO_EDITOR DRC_CONSTR       False embedded component DRCs
9 T" e$ }. M4 Y5 {2 }0 \- h958753  ALLEGRO_EDITOR SHAPE            Dynamic shape is getting corrupted in 16.5
! w  G+ r/ f1 c! m) ]959011  ALLEGRO_EDITOR OTHER            copy problem of via and cline
4 J9 M8 Q; L. ?9 R959101  ALLEGRO_EDITOR EXTRACT          Using extracta with excluding Thermal reliefs
959253  CONCEPT_HDL    INFRA            Design will not open
959299  APD            MODULES          Getting ERROR(SPMHDB-279) when trying to update modules placed on the Top side
959884  CONCEPT_HDL    INFRA            Design Uprev/concept2cm crashes with Application Error/Out of Memory Error.
: X) V2 u8 `# G' ^959909  ALLEGRO_EDITOR SCHEM_FTB        Site level propflow.txt file is ignored property is transferred
3 y2 K1 y, |% t$ M960067  SIP_LAYOUT     PLATING_BAR      Creation of plating bar removes "NODRC_ETCH_OUTSIDE_KEEPIN" property from the clines.
960126  SIG_EXPLORER   EXTRACTTOP       Allegro PCB SI license is used automatically at Topology Extraction of Allegro Physical Viewer.
960143  SIG_INTEGRITY  GEOMETRY_EXTRACT Running simulation in Bus sim happened crash while enable Coulpled Via model to S parameter
0 M! ~) n2 j; o, Y4 K) `2 F961349  CONCEPT_HDL    HDLDIRECT        Motorola designs have broken connectivity compared to 16.3
961816  ALLEGRO_EDITOR INTERFACES       Normal Export > DXF fails and offsets  the pins of the BGA symbol
962519  SIP_LAYOUT     WIREBOND         Align option doesn't work for wb_tackpoint fingers

nbhand

s013，感谢楼主分享。

pmp_mcu

多谢分享。。。。。。。。。。。。。。。

bazhonglei

顶！！！！！谢谢分享！

fangqwas

谢谢分享

ZXCLH

15没装成功过,但还是谢谢你...
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cotterie

非常感谢楼主yulizi 的无私奉献，有了你这个论坛充满了生机和希望。

koncc

感謝分享{:soso_e100:}

reval

都更新些什么呢？？

luluman

大神啊，顶
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john22ppo

1 _7 Q; n+ V- R7 `+ u* w3 I" C+ e8 q感謝分享

interrupt

说什么好呢

suiwinder

楼主好人啊.
太感谢了.
现在这cadence也太差了把

adolfchen

感謝分享{:soso_e179:}

mengshang

太感谢您了