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本帖最后由 yulizi 于 2011-12-22 11:18 编辑 + l4 _+ F' _% a( C+ J5 u7 y h
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http://kuai.xunlei.com/d/DGOHIFKLICUP
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DATE: 12-16-2011 HOTFIX VERSION: 013
3 ~' a. D8 k; t, l0 p6 O===================================================================================================================================
" K, _9 S, t$ Q% N6 o" oCCRID PRODUCT PRODUCTLEVEL2 TITLE
; k0 x- y1 L$ u% C2 H. e===================================================================================================================================, ^1 M9 C# {# r! G+ ?6 v7 X
875695 SIG_EXPLORER INTERACTIV Enforce Causality check box doesn't work.' m5 G6 V! u7 n) f0 h
927148 CAPTURE PROJECT_MANAGER Capture crashes on creating scehmatic folder with name which already exists in design
5 e% n, B- }3 {$ B938013 CAPTURE NETLIST_OTHER The netlist in RINF Format contained two identical lines for PCB FOOTPRINT
2 @" b3 I4 f- b$ u4 |941409 Pspice PROBE BUG : Search accuracy wrong in new cursor window& v1 J: K( G. A7 l$ y
945242 SIG_INTEGRITY SIMULATION Unable to select "shapes" in find filter for 'show parasitic ' command
6 A- _8 U# @) Z3 C946293 concept_HDL ARCHIVER Archiver hangs if there is a whitespace at the end of the path of cref.dat
7 ^8 a6 z" Y1 s. l: e# x946770 CONCEPT_HDL CORE 揤iew Design?function is missing in Windows Mode after reseting the menus.$ c6 c* n; |% V9 q4 @: v& I
950994 CAPTURE NETGROUPS Problem in expanding the netgroup in Auto Connect to Bus function
6 D6 @+ U4 k1 ]( w1 m953530 SIG_INTEGRITY GEOMETRY_EXTRACT Display Parasitics is displaying wrong results for EMS2D Field Solver compared to topology extraction using Probe.
( L9 a" Q( d* a953713 CONCEPT_HDL PAGE_MGMT Random page replacement/duplication in block" ?0 k7 p; g f, y6 w) m1 E% [
953917 CONCEPT_HDL ARCHIVER archcore should handle errors correctly, g' ]4 Y8 y* N" d z; K& w
953971 allegro_EDITOR MANUFACT NC Drill files not generated correctly when using the option "搒eparate files for plated/nonplatedholes?
& e0 D1 q" T9 c$ H+ J3 [" I954400 CAPTURE NETGROUPS BUS members of NetGroup are getting converted to Scalars in Export-Import NetGroup.! w. Q) [6 D6 P3 B5 J
954498 SCM B2F SCM crashes when importing physical# ]4 ^& M" \! `$ n5 K; B5 {: ~
954623 ALLEGRO_EDITOR EDIT_ETCH Unable to complete connection with Add Connect - related to soldermask to cline check?, m7 v4 Z( k$ \# c \3 i
954894 ALLEGRO_EDITOR MANUFACT Dimensions disappear when opening database in v16.5 from v16.3
& _/ S# U; I* }955029 CONCEPT_HDL CORE custom text font size not recognized in symbol view) K7 x) ]7 `8 h8 w$ ]. A' {& X
955133 SIG_INTEGRITY FIELD_SOLVERS The Field solver creates the differential trace model which is reversed T(D1) and T(D2) of bottom side.
+ F6 ?/ v/ E# n9 l. \955290 CAPTURE DRC Description for UPD0014 missing in the Browse DRC markers window l: I5 b0 O* U+ X6 F: V* A( @
955299 ALLEGRO_EDITOR DRC_CONSTR drc text to smd pin does not work any more on this database in 16.3 S039
, A6 u9 [( r; Z2 @9 {- k955338 CONCEPT_HDL CHECKPLUS Need to change PART_NAME
( i! m( Q* U# Z5 c955447 SIG_EXPLORER OTHER Model path set in DE HDL Model Assignment not used by SigXP from CM in DE HDL
6 P$ t* C( A) h% ]. g955740 SIG_INTEGRITY GEOMETRY_EXTRACT Crosstalk with Timing Windows does not work correctly
) Z. N$ l+ h2 J* w955749 ALLEGRO_EDITOR MANUFACT show element Info shows symbol dimensions on incorrect subclass
- d! p! @ T% b/ t) ?4 I3 y955912 ALLEGRO_EDITOR OTHER Shapes with voids that are exported to PDF have gray filled area over the void
' L- ~$ p; m4 H3 C a z956129 CONCEPT_HDL INFRA DEHDL uprev hierachical design from 16.2 to 16.5 packaging failure.! @' l+ D) x0 O7 Q4 T2 G0 J
956373 ALLEGRO_EDITOR NC drawing name doesn't display in the log file" t# m' v: ?- I6 K2 {2 M. B1 S
956393 CAPTURE PROJECT_MANAGER "GENERAL" and "TYPE" tabs are missing from "Properties" dialogue box.
. s& l# m% \1 Z956448 PSPICE MODELEDITOR Can not generate a DEHDL symbol from Model Editor, because no Capture license found
% j |3 h+ S& c& y0 x956456 CAPTURE NETLIST_OTHER OrTelesis netlist not transferring user properties defined under combined
! |4 Z& A+ ]& D( f' K9 _$ k956489 ALLEGRO_EDITOR MANUFACT dimensions lost when symbol with diemnsions attached to symbol origin placed on board
3 D$ q, j5 w& }1 Q, L. ~/ Y956603 CONCEPT_HDL OTHER Part Manager "has stopped working" after changing a component
2 L$ p' V0 ^, f5 R956751 ALLEGRO_EDITOR ARTWORK Import Gerber command does not work correctly" t5 u" M/ e3 c! Q" ~
956847 PCB_LIBRARIAN METADATA PDV - Partdeveloper symbol to function linkage broken/changed in 16.5+ U3 A9 U4 S0 t3 b6 |; J- u1 e
956987 CAPTURE OTHER Find from "Search toolbar" doesn't gives complete results0 s% u( F: \ ~! k) Z1 t" Z
956996 CONCEPT_HDL INFRA Correction to ERROR(SPCODD-7): Following Primitive instance causes CM to empty
4 O9 S {4 y u& e957009 CAPTURE NETLIST_OTHER Problem getting database property in mentor pads PCB netlist
" `3 o. v/ Y7 n957137 APD DXF_IF DXF out command dose not work correctly.& p. ~; G" F5 B( q9 l/ L6 R
957167 APD GRAPHICS Highlighting for Static shape with display_nohilitefont environment variable.% X b) f* O, U0 l$ s
957232 SIG_INTEGRITY OTHER Allegro crash during Model Assignment.
; @9 c" I" j1 P! t& q( \' v0 [957267 CONCEPT_HDL INFRA Packager Error after Import Design. J4 }: P, C! D' D
957866 SIP_LAYOUT DATABASE Cavity outline is not getting deleted from symbol file
4 f0 ~% _+ ^% X; y- J* X1 o958010 ALLEGRO_EDITOR REPORTS Wants the ability to extract "Batch" reports from Partition ".dpf" files.( l0 L, K8 @* H
958252 ALLEGRO_EDITOR TESTPREP Resequence testprep with the option - Delete probes too close crashes the design
4 d1 C. J3 ]6 I. L+ i4 }4 i) m958253 ALLEGRO_EDITOR REPORTS Shape did not have thermal relief connected to pin but unrouted nets still shows zero.
) B& k" c/ [# w0 ?8 u0 y958433 ALLEGRO_EDITOR DRC_CONSTR False embedded component DRCs/ g: s; ~# k0 z, r: y
958753 ALLEGRO_EDITOR SHAPE Dynamic shape is getting corrupted in 16.5
. _# @+ }3 h- j3 h/ ]' P959011 ALLEGRO_EDITOR OTHER copy problem of via and cline- F5 b7 |2 Y% Q& i
959101 ALLEGRO_EDITOR EXTRACT Using extracta with excluding Thermal reliefs
* U# F2 G- S, y) ^$ u959253 CONCEPT_HDL INFRA Design will not open
. f7 y5 g0 s+ f959299 APD MODULES Getting ERROR(SPMHDB-279) when trying to update modules placed on the Top side# y! B4 \4 Q3 K$ d$ K/ C
959884 CONCEPT_HDL INFRA Design Uprev/concept2cm crashes with Application Error/Out of Memory Error.
3 `# }6 R! e% o8 S959909 ALLEGRO_EDITOR SCHEM_FTB Site level propflow.txt file is ignored property is transferred
& Q+ C' U% f) L7 V, V9 \) @960067 SIP_LAYOUT PLATING_BAR Creation of plating bar removes "NODRC_ETCH_OUTSIDE_KEEPIN" property from the clines.6 z4 w% y1 c4 I# m5 l9 l
960126 SIG_EXPLORER EXTRACTTOP Allegro PCB SI license is used automatically at Topology Extraction of Allegro Physical Viewer.
" V0 @- G; @: z$ I) j960143 SIG_INTEGRITY GEOMETRY_EXTRACT Running simulation in Bus sim happened crash while enable Coulpled Via model to S parameter0 i2 P- h: B& Z/ w8 i( ^) B
961349 CONCEPT_HDL HDLDIRECT Motorola designs have broken connectivity compared to 16.3% S; m Z# c; o& f. i
961816 ALLEGRO_EDITOR INTERFACES Normal Export > DXF fails and offsets the pins of the BGA symbol# H7 M2 k( T* F6 b/ N! o
962519 SIP_LAYOUT WIREBOND Align option doesn't work for wb_tackpoint fingers |
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