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stupid · 发表于 2011-4-26 14:44

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本帖最后由 stupid 于 2011-4-26 15:25 编辑

Today's testing, tomorrow's engineers
Staff and students combine to form a unique test lab that's widely respected in the data-communications industry.
Martin Rowe, Senior Technical Editor -- Test & Measurement World, 4/1/2006 2:00:00 AM

Durham, NH—You may not think of New Hampshire as a hotbed for data-communications testing, but you should. In this town a few miles from the seacoast resides the University of New Hampshire InterOperability Laboratory (UNH-IOL, www.iol.unh.edu), part of the UNH Research Computing Center. The UNH-IOL is a testing lab that has the respect of just about every maker of data-communications equipment. Since its founding in 1988, the UNH-IOL has become known for its technology expertise and for a spirit of cooperation that helps member companies solve conformance and interoperability problems.

The UNH-IOL currently tests products in 20 technology categories, including Ethernet, DSL, IPv6, Serial Attached SCSI (SAS), Serial ATA (SATA), Fibre Channel, and Wi-Fi. Companies join the UNH-IOL to take advantage of its heavily equipped test beds and extensive technical resources. Test beds contain hardware and software tools developed at the lab for peRForming compliance tests, and they also contain networking equipment from member companies that the lab uses for interoperability testing. For an annual membership fee ranging from $14,000 to $20,000, a member company may reserve week-long blocks of individual testing on a test bed and participate in week-long group tests, called "plugfests." Some companies belong to more than one technology group; the lab refers to each group as a "consortium." (Editor's note, 4/21/06: This section has been amended since the article was published. The original wording implied that members were permitted to use the lab for only one week per year or attend only one plugfest per year. This is not the case.)

Students perform most of the tests, which cover components such as communications ICs, subsystems such as network-interface cards, and network elements such as switches and routers (see "Let the students do the testing"). Member companies often send an engineer to the lab for a week to work with students on standards compliance testing or interoperability testing. "Catch the Rabbit," highlights how Rabbit Semiconductor used the UNH-IOL when the company added Ethernet to its microprocessors.

The test beds are richly equipped, because companies that join a lab consortium must agree to contribute their products. "We have networking and communications equipment that companies won't give to each other," said Gerard Nadeau, manager of the UNH-IOL's Fast Ethernet Consortium. "We act as a buffer between companies, and we can work out problems without giving away proprietary technology."

"Some companies leave every product they bring to the lab," added Bob Noseworthy, manager of the lab's 10 Gigabit Ethernet Consortium. "But 10-Gbps products are expensive, so we may share products with the IPv6 Consortium."

Because companies provide products for the test beds, their products are continually tested against new products. "We've found interoperability problems with equipment that's been on the market for years" said staff engineer Andy Baldman. "When that occurs, we contact the manufacturer and explain how their product interacts with a new device."

UNH-IOL clients appreciate the lab's role as a technology intermediary. "The UNH-IOL gives us a neutral ground," said George Dobrowski, director of technology and product planning at Conexant, a member of the lab's DSL Consortium. "We can bring our DSL chips there for a week of intense testing." Conexant uses the DSL test bed to run interoperability tests on new designs because "the UNH-IOL has equipment combinations that we can't replicate in our own lab."

Beds and tools

Test beds contain networking equipment, test equipment, and test tools. Often, staff and graduate students develop hardware and software test tools before such tools are commercially available. "We have, on occasion, used a company's prototype or evaluation board as the basis for developing a test tool," said Nadeau. "If member companies give us the hooks into their products, we can design a somewhat automated tool for more in-depth analysis than we could achieve with standard test equipment."

The lab has several Ethernet test tools that graduate students and staff have designed in collaboration with member companies. But because the lab lacks the facilities to fabricate test boards, member companies often pitch in to design and build them.

One such test tool is the "Tiger," designed by UNH-IOL and Texas Instruments (Figure 1), for testing Gigabit Ethernet (GigE) and Fibre Channel devices. The Tiger provides students with access to an Ethernet IC's signals. It provides 20 digital outputs that connect to an Agilent Technologies logic analyzer. With the tool, students testing GigE ICs can see a parallel representation of a GigE data stream—while the data is in a 10-bit format. They can view two 10-bit sequences at once on the logic analyzer. (GigE uses 8b/10b encoding that converts 8-bit data into 10-bit data. The extra bits add bit transitions to provide for clock recovery.)

Another test tool used for Ethernet testing lets students view a Fast Ethernet Auto-Negotiation sequence, which is a significant part of conformance testing. This tool consists of a custom interface board (Figure 2) that connects to a digital I/O card from Viewpoint Systems that then connects to a PC. The Auto-Negotiation sequence consists of a series of 100-ns pulses that occur at 100-ms intervals. The interface board contains one-shot flip-flops that elongate the pulses to lengths long enough for the digital I/O board to capture them. A custom software application written in LabView provides a graphical display of the sequence.

When performing tests, the students follow carefully written test procedures that describe how to set up and run tests based on clauses in communications standards. The procedures, available for downloading from the UNH-IOL Web site, clarify ambiguities in standards that require measurements without specifying how to make them.

UNH-IOL engineers play an important role not only in interpreting industry standards but also in helping to develop them. For example, consortium managers Eric Lynskey (Ethernet in the First Mile) and Bob Noseworthy (10 Gbit Ethernet) and others regularly attend committee meetings of IEEE 802.3 Ethernet subcommittees, and they often edit IEEE standards documents.

Physical-layer measurements

The Tiger and Auto-Negotiation test tools let students test Ethernet products at the Ethernet physical (PHY) and data-link layers, but much of the lab's conformance testing for Ethernet and other technologies focuses on the analog signaling in the PHY layer. Jitter is perhaps the most critical PHY-layer measurement, and the UNH-IOL has been a pioneer in the area. Andy Baldman measures jitter in serial data streams by capturing them with high-bandwidth oscilloscopes from Agilent, LeCroy, and Tektronix. Although today's oscilloscopes can perform jitter analysis, the UNH-IOL staff created its own tool using Matlab when the lab started offering jitter conformance testing for Token Ring networks.

"Once upon a time, scope companies just made scope hardware, so we had to develop our own software tool for separating total jitter from deterministic jitter," said Baldman. Because he knows exactly how his algorithm works, he can answer questions about how the measurements were made when a product fails.

Baldman will use a scope maker's internal conformance software if he knows its algorithm. He spent the summer of 2005 working for Agilent Technologies on the company's Ethernet compliance software. He started using it because he knows how it works, but he also knows that engineers in the industry use scopes from other makers. Thus, he compares results obtained from Agilent, LeCroy, and Tektronix scopes. He's working with test-equipment makers to hARMonize the methods of jitter measurement to provide more consistent results.

Baldman's relationship with test-equipment makers is typical of other UNH-IOL staff members. Much of the test equipment in the lab is donated, and staff and graduate students often develop their test procedures that use the donatedequipment.

"We can't get out of the starting gate without test-equipment makers," noted Noseworthy. "The difficulty is that we try to play evenly with all the manufacturers." Test-equipment makers also rely on the UNH-IOL for their own product testing, often bringing new equipment to the lab for evaluation.

Students and staff use test equipment for more than just measurements. The lab's DSL Consortium, managed by Matthew Langlois, uses data generators from Spirent Communications and wire-line simulators from Spirent, Telebyte, and Sparnex to test DSL modems and DSL access multiplexers (DSLAMs), which are used by service providers. Data generators create data streams and wire-line simulators simulate worst-case line conditions for each of the DSL modulations that the lab supports (ADSL1, ADSL2, ADSL2+, and VDSL2).

During a compliance test, a digitizer captures the DSL signals on a phone line and transfers them to a PC through a National Instruments digital I/O card. The PC measures longitudinal balance, transmit power, noise margin, and bit-error rate. The digitizer acts as a digital storage oscilloscope with flexible sampling clocks and an arbitrarily deep capture buffer greater than 512 Mbytes, which far exceeds that of commercially available scopes. With the digitizer card, students running a test can store as many samples as they need in the PC's hard drive and perform signal analysis offline.

The DSL test bed (Figure 3) consists of five DSLAMs and hundreds of DSL modems. DSL modem makers and chipset makers such as Conexant come to the lab because the test bed has DSLAMs from all suppliers. Modem makers can typically use the lab's standard test suite, although some will run customized tests. "The standard test suite takes about 18 hours to run," said Langlois. "It takes a week to run through all five DSLAMS."

Testing the next Internet

While the UNH-IOL focuses heavily on deployed technologies such as Ethernet and DSL, the lab is also involved in the next Internet technology, IPv6. "IPv6 is the next Internet protocol," said technical manager Erica Williamson. "With IPv6, we should never run out of IP addresses."

The UNH-IOL is a leading IPv6 test lab, with a test bed that consists of routers, firewalls, servers, cameras, a network time server from Symmetricom, and router and network testers from Agilent and Ixia. Makers of voice, video, and data-communications products come to the UNH-IOL to test their IPv6 protocol stacks. Test tools include software that lets students and staff manipulate data traffic. "We look at every 'must' and 'should' in the protocol specification to see how an equipment maker implements it," said Williamson. Testing of an IPv6 product takes from one to two weeks.

The lab's IPv6 Consortium's test bed includes a connection to the world's largest IPv6 network. Dubbed the MoonV6 project (www.moonv6.org), the IPv6 network is a joint effort led by the North American IPv6 Task Force that includes the UNH-IOL, the Department of Defense, and network service providers. Its aim is to promote the use of the IPv6 protocol. At a MoonV6 plugfest, makers of video and voice equipment, routers, and firewalls test their products for interoperability.

While IPv6 is an up-and-coming technology, 10BaseT Ethernet is mature and stable. Thus, the UNH-IOL has dropped its 10BaseT Ethernet Consortium, but the lab still tests new 10BaseT products on an individual basis for backward compatibility and conformance.

Serial-bus technologies that are gaining in popularity include SAS and SATA. The UNH-IOL has formed the SAS Consortium, which currently has five full members, but it supports SATA as a testing service only. "We're trying to convince companies to help us start an SATA consortium," said Baldman. He's currently developing test beds for both serial buses. Part of the difficulty stems from these products being so new that manufacturers often don't have many samples to contribute.

Makers of SAS and SATA disk drives and host-bus-adapter cards can use the UNH-IOL to perform interoperability tests under specified worst-case conditions. The test beds that Baldman is developing use a "golden worst case" set of cables built by Molex specifically for the lab. The cables come in three different lengths and gauges although they produce identical amounts of signal loss.

"Some companies want different lengths so they can say their products were tested with different length cables," said Baldman. "While the cables may be equivalent from a signal-loss perspective, the ability to demonstrate that you work across different length cables is still very valuable to our members from a marketing perspective."

Although the UNH-IOL is best known for testing wireline technologies, its staff and students can test IEEE 802.11 wireless devices, too. Jeremy Kent manages the lab's Wireless LAN Consortium, which contains a precompliance test bed (the UNH-IOL is a certified Wi-Fi precompliance lab). The lab has dozens of wireless devices that let students perform interoperability tests. The test bed includes wireless test systems from Azimuth Systems and VeriWave as well as a vector network analyzer and signal generator from Rohde & Schwarz. The test bed can perform measurements such as transmit power and protocol analysis. A graduate student is developing a receiver test tool as part of a master's thesis.

The UNH-IOL has gained the respect of many people in the data-communications industry. Its test tools and procedures are the envy of many engineers. IC manufacturers, card manufacturers, network-equipment manufacturers, and test-equipment makers rely on the UNH-IOL's spirit of cooperation and technical expertise to verify that their products will work in the field.

Catch the Rabbit

During my visit to the UNH-IOL, I met Lynn Wood, an engineer with Rabbit Semiconductor. Rabbit is adding Ethernet to its processor ICs, and Wood spent a week at the lab running compliance tests. Wood tested receivers, transmitters, complete Ethernet subsystems, and software drivers.

This was Wood's second visit to the UNH-IOL for this project. After performing basic function tests in his lab, Wood came to the lab because, "If you look at the Ethernet spec, you can't figure out what to test. UNH-IOL has worked all of that out." On his first visit, Wood worked with his device in FPGA form because he could quickly make design changes based on test results. This time, he was there to test the final FPGA design before the company commits to building it in ASIC form.

Wood performed 10BaseT Ethernet transmitter and receiver PHY-layer tests under worst-case conditions. He tested his devices using long cables and used a UNH-IOL tool to create simulated signals with varying jitter, crosstalk, skin effects, return loss, and rise time. The test tool uses Matlab scripts to generate Ethernet worst-case signal conditions. Wood performed bit-error-rate measurements to verify that the receivers could maintain 10–12 BER or less under worst-case conditions.

Let the students do the testing

Students play a major role at the UNH-IOL. In fact, about 100 of the 120 UNH-IOL employees are students, most of whom are undergraduates majoring in electrical engineering or computer science, although some have nonengineering majors. Students do the lab's testing under guidance from a graduate student or staff member.

Students learn about the UNH-IOL from open houses, through friends, or through faculty members. A professor may recommend a student to the UNH-IOL for a position. Students typically work about 15 hours per week. "We assume no knowledge of computer networks, and we assume that everything a student knows about networks is wrong," said EFM Consortium manager Eric Lynskey. The UNH-IOL usually hires first- or second-year students. After being hired, students must spend 13 weeks at "boot camp" during the summer, where they learn the basics of computer networks and become familiar with the lab's test tools.

Students do most of the testing, using hardware and software test tools developed by staff engineers and graduate students. "Students will learn LabView and Matlab, and once they gain enough experience, they can tweak test code," noted Lynskey. Sometimes, a student will develop a test tool for academic credit such as a senior project or a master's thesis. In addition to gaining practical experience from their UNH-IOL jobs, the students also make industry contacts that often lead to employment after graduation.

stupid · 发表于 2011-4-26 14:50

本帖最后由 stupid 于 2011-4-26 15:39 编辑

The chips almost test themselvesWith the test features they build into their PCIe switches and 10-Gbps PHY devices, the engineers at PLX Technology can see things their bench instruments can't.

Martin Rowe, Senior Technical Editor -- Test & Measurement World, 4/1/2011 12:00:00 AM

Sunnyvale, CA—High-speed serial buses such as PCIe (PCI Express) and 10-Gbps Ethernet present significant challenges to designers of computers and communications systems. PCIe data rates of 8 GT/s (gigatransfers per second) and Ethernet data rates of 10 Gbps produce signal degradations in interconnects and PCB (printed-circuit board) traces (Ref. 1), yet system designers have difficulty measuring the degradation, because test equipment can't see inside a device.

Engineers at PLX Technology address this problem by building self-test features into the company's devices. The self-test features were also essential when the engineers developed their first PCIe switches and 10GBaseT PHYs (physical-layer interfaces), because the necessary test equipment hadn't yet reached the market. Initially, test functions inside the devices were available to PLX engineers only, but engineers learned that making these test functions available to customers helped those customers with their designs and helped applications engineers solve problems.

The PLX devices include self-test features such as traffic generators, signal processors, temperature sensors, and sampling circuits. They can perform loopback tests, BER (bit-error-rate) measurements, channel calibration, eye-width measurements, linearity measurements, and packet analysis.

No device can perform all of its own testing, however, so the PLX engineers also need some external test equipment. For example, to test the devices over a full range of PVT (process, voltage, temperature) parameters and to conduct interoperability and EMI (electromagnetic interference) tests, the engineers employ oscilloscopes, power supplies, BER testers, and thermal heads. Serial-bus products also need evaluation boards for physical-layer measurements, data-link measurements, and compliance tests.

PCIe is now in its third generation, called Gen3, which runs at 8 GT/s per lane. Gen3 data rates are up from 5 GT/s per lane for PCIe Gen2 and 2.5 Gbps for Gen1. In September 2010, PLX added 10GBaseT (10-Gbps Ethernet) PHY devices to its line-up through its acquisition of Teranetics. The devices convert XAUI (10 Gigabit Attachment Unit Interface) or XFI (10-Gigabit serial electrical interface) buses on the system side to 10GBaseT Ethernet on the line side. PLX also manufactures PCIe bridges and storage controllers for the consumer market.

Reginald Conley, PLX director of hardware applications, explained that PCIe switches, used in servers and switch products, can have up to 96 lanes grouped into ports of up to 16 lanes. PLX PCIe Gen3 switches with 48 lanes are in production, and 96-lane devices are in development (96-lane Gen2 is already shipping). Typically, 16-lane ports are used by graphics cards. Each lane uses differential signaling, which uses two PCB traces per lane. That requires a test board to have two SMA connectors per lane.

2 b* \2 }: |, F4 ZFigure 1 shows a test board for a 96-lane PCIe switch. The 192 SMA connectors give engineers access to each lane so they can make measurements such as BER, return loss, and jitter. The switches have I2C ports that give engineers access to the device for setting parameters and reading registers that contain test results.

Figure 1. A test board for a 96-lane PCIe switch has 192 SMA connectors.

Sampling from inside

The PCIe switch has internal sampling circuits that let engineers see the signal inside the device, which they can't do with an oscilloscope. At PCIe Gen2 and Gen3 data rates, the pins and bond wires inside a device package attenuate signals and add noise and jitter. Furthermore, the switch's internal signal processing takes the incoming signal, which has no eye opening, and opens the eye.

External instruments are still necessary for looking at signals at device pins, but probes can alter signals when connected to device pins or connectors. "An oscilloscope probe on a high-speed signal may clean the signal or make it worse," said Vijay Meduri, VP of engineering for PCIe switches. Conley added "A probe could filter out a high-frequency glitch and cause you to miss it."

Conley explained that the sampling circuit samples a signal's phases and adjusts the sampling based on amplitude. It then puts data about the sampled signal onto a register that PLX's visionPAK PC software can read through the I2C bus. The software uses the combination of phase and amplitude to produce an image, which is an on-chip eye diagram that represents bit errors. PLX design engineers, application engineers, and customers can use visionPAK to control the internal test functions and poll registers for test results.

To produce the eye diagram of BER measurements, visionPAK collects 1's and 0's from every lane on a switch, overlays them, and maps the eye image based on BER. Figure 2 shows the eye diagram that represents BER. Engineers can change the sampling point of the eye and use the software to calculate BER at any point in the eye. The blue area in the eye's center indicates sampling points where no errors occur. As the sampling point (colored bars) moves toward the crossing points, BER increases.

Figure 2. The plot indicates the BER across many PCIe Gen3 lanes, with the blue center indicating a sampling point with no errors. Courtesy of PLX Technology.

When PLX began manufacturing PCIe Gen1 switches, test features weren't available through software. Conley noted that engineers had to use jumpers on the test board to activate test features.

A PCIe switch also has loopback capability, which lets engineers use a port to test itself or another port. Figure 3 shows two loopback configurations, which engineers can configure through visionPAK. The blue arrows indicate an internal loop where a lane's transmitted signal loops back to its receiver. In an external loop (red arrows), a signal from another lane—on the same device or another device—passes back to its source. An external loop includes a transmission medium such as PCB traces and connectors. A test of an external loop can reveal problems such as impedance mismatches or CDR (clock-data recovery) errors.

Figure 3. PCIe switches have loopback capabilities for both on-chip and external tests. Courtesy of PLX Technology.

As with most serial buses, engineers use the loopbacks as part of a BER test that generates a PRBS (pseudorandom-bit-sequence) pattern. BER tests let engineers build confidence that a device is working, but the tests do nothing to verify that two devices can establish a data link. For that, engineers need to send PCIe packets between two ends of a lane. Internal packet generators let PLX engineers and customers test that a switch can establish a link and send error-free packets. Packets are user-configurable so engineers can force packet errors and dropped packets to see how a link responds.

PCIe has many possible errors, and a device must handle each in a consistent and specified manner. Through the
visionPAK software, a PCIe switch device can inject specific errors into a data stream at random times. The device has registers that log the errors, and engineers can interrogate the logs to find out how the device responded.

Engineers generate high-density traffic using a switch's internal packet generator, which generates layer-2 packets called TLPs (transaction-layer packets) that establish the data link between two ends of a lane. "With the packets," said Conley, "you can test a link from end point to end point."

The data that travels over a serial link has a direct effect on how much power a switch consumes. Because of that, PLX engineers have developed data patterns that force PCIe switches to consume their maximum power. "Customers want to know a device's maximum power consumption," said Meduri. "They need it for their power budgets." He explained that a PCIe switch's core logic consumes about 70% of the total power, with the PHY circuit consuming about 30%. A device's power consumption is at its highest when the maximum number of transistors is switching on and off.

Power sequencing also plays a vital role in testing. A PCIe switch uses three voltages: 0.9 V for core logic, 1.8 V for SerDes (serializer-deserializer) and I/O buffer circuits, and 2.5 V for some I/O buffers. Meduri noted that the switches must function properly regardless of the order in which power comes up, so testing must include all possible power-up combinations.

Even with all of these tests to verify performance and to let engineers characterize the PCIe Gen3 switches, it's interoperability that counts. After all, a PCIe switch is part of a larger system. For interoperability testing, engineers use test boards and PC mother¬boards that can hold several PCIe peripherals such as switches from other manufacturers, network-interface cards, and graphics cards. The PLX interoperability lab for PCIe devices has more than 100 computers so engineers can test with most PCs on the market. Software developed for interoperability testing can detect any PCIe card in the system just as an operating system does. The software can send packets between the switch under test and any peripheral.

r* I* u/ Q& h, }& I! JThe PHY's the thing

With its acquisition of Teranetics, PLX moved into the 10-Gbps PHY market. The company's 10-Gbps PHY device, often used in routers at data centers, is an interface between 10GBaseT Ethernet on the line side and XAUI or XFI on the system side. Dimitry Taich, director of system engineering, said that although most available products use XAUI, more and more new designs use space-efficient XFI.

The PHY device has features that help PLX engineers decide how to test it. For example, imagine that the log file on a device indicates that packet errors occur on a particular port and that the error intervals are equal to multiples of a power-supply switching frequency. This would point toward insufficient isolation between power planes and signal paths and would tell the engineers where to start their tests.

Performance tests begin, of course, with BER. "If you pass a BER test," said Taich, "then the PHY is working properly. If a device doesn't pass, then we have to study the problem."

To run a BER test, the engineers connect a traffic generator from Ixia or Spirent Communications to the device's XAUI receive channel. They then loop the 10GBaseT output from channel 1 to the input of channel 2. Figure 4 shows the setup for what Taich calls a "snake test" that tests all four of a device's ports.

Figure 4. A "snake test" lets engineers measure the BER on a PHY's four line-side and system-side ports.

A test for a BER of 10-12 takes several minutes. That's what the standards require, but customers require a test for a BER of less than 10-14 or 10-15, which takes several days. The test uses actual Ethernet packets, not just PRBS patterns. "We drive traffic and look for broken packets," said Taich. "If we test for several days and see zero errors, we're done. If, however, a test fails, we have to go deeper and analyze test results, starting with finding which port or ports are causing the problem."

Once engineers know which port is causing the BER problem, they measure signal parameters such as jitter and driver linearity. They also look for problems related to temperature and power-supply voltage. The PHY devices have on-chip temperature sensors and can log their temperature readings. From the log data, engineers can decide if the device has a temperature problem. They can use the PHY device's internal temperature sensor to monitor device temperature. If required, they can adjust internal processing algorithms to mitigate the problem.

Temperature is just one of the variables that can affect a device's performance. PLX engineers run PVT tests that characterize the 10GBaseT PHYs. Engineers who characterize the PCIe switches and other devices also run these tests.

PVT tests involve subjecting a device to extremes, or corners, of the three variables. Varying power-supply voltage and temperature is easy to do. Changing process variables such as speed requires that manufacturing engineers vary processes when making a device. Typically, design and test engineers will ask manufacturing to vary the process for device speed, but other parameters may also need adjustment.

A PHY can't connect directly to a connector. It must go through a transformer first. The transformer provides isolation, blocks DC voltages, and matches line impedance. PLX engineers test interface devices with transformers from several manufacturers so they can recommend a transformer to customers.

PLX engineers also use evaluation boards to characterize their devices and gain extensive knowledge about how their parts work. Customers, though, design those devices into systems such as switch cards. Problems can occur there because of the interaction between components. At 10-Gbps speeds, even short PCB traces can affect signal quality. PHY devices should be placed as close to connectors as possible. A board may, however, have so many communications ports that designers cannot fit every PHY device near its connector. Taich noted that many multiport designs need two rows of PHY devices. Those devices in the second row will have longer PCB traces between them and their connectors, which can result in signal distortion compared to front-row devices.

To help solve this problem, the PLX engineers developed a test routine that lets the PHY send a test pattern to the system upon power up. The device collects reflections from connectors and analyzes the reflections. In a few tens of microseconds, the device measures the quality of each link and places the results in registers that the host system can read. The device can compensate for signal loss through channel adjustments on its internal DSP (digital-signal processor). Such a test also allows a check for missing components in the data path, thus significantly speeding up systems-level manufacturing testing.

The PHY devices also have the ability to measure port-to-port (or "alien") crosstalk. "Crosstalk is an issue because speed and noise considerations are strict," said Taich. "We developed a routine where one port sends test patterns while another is quiet. Because we know the pattern, we can analyze the noise on the quiet port to see how much energy it receives." The port can measure the noise and compare noise levels to predetermined limits based on IEEE standards.

Taich noted that PHY testing also requires engineers to run performance tests on their devices with cables of different lengths (up to 140 m) and from different suppliers. Measurements such as BER, jitter, and crosstalk take several hours, with a complete test suite taking two days to complete. To reduce test time and automate the changing of cables, PLX engineers developed a "robot" that connects a PHY under test to many cables under software control (Figure 5).

Figure 5. A robot automatically connects an assortment of cables to a PHY under test.

! z& `$ [* p- E m
Interoperability is key
( J9 E/ U$ |8 b' M& h! U- v
All communications devices must interoperate with those from other sources, often from competitors, so PLX engineers buy PHYs and SerDes devices from several companies in order to test their devices for interoperability. Based on the test results, the engineers can program internal logic (state machines, timers, signal-processing engines) to match a link partner's expectations and improve interoperability. Unfortunately, a setting that maximizes interoperability with one supplier's part can degrade interoperability with a different supplier's part. "It's a moving target," said Taich.

Because there are many 10GBaseT parts on the market, PLX still sends parts to the University of New Hampshire InterOperability Lab for tests (Ref. 2). "The UNH-IOL has a wide variety of test platforms, and they choose the most difficult products to test against," said Taich. "They also test for interoperability at 1-Gbps and 100-Mbps speeds, which we need to provide backward compatibility with older devices."

A great deal of testing goes into data-communications devices to ensure they comply with industry specifications and satisfy customer demands. By integrating test into the devices themselves, PLX engineers have made it possible to get their devices to market sooner.

REFERENCES

1. Kazmi, Akber, "PCI Express Gen 3 Simplified," EE Times, February, 24, 2009.

2. Rowe, Martin, "Today's testing, tomorrow's engineers," Test & Measurement World, April 2006. p. 28.

51video · 发表于 2011-4-27 10:08

啊。。。都是E文。。
不过很专业的感觉

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