SPI程序问题

jiaohuang2004 · 发表于 2011-3-19 05:12

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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity spi is
port
  (
reset    : in std_logic;  --global reset signal
sysclk    : in std_logic;  -- systerm clock
data_in    : in std_logic_vector(13 downto 0);
spi_o    : out std_logic;
sck_out    : out std_logic;
ss_n       : out std_logic_vector(1 downto 0)
  );
end spi;
architecture b of spi is
  type state_type is (idle,shift,stop);  -- data type define
  signal state          : state_type;
  signal out_reg          : std_logic_vector(13 downto 0):=(others=>'0');
  signal clkdiv_cnt       : std_logic_vector(3 downto 0) :=(others=>'0');
  signal bit_cnt          : std_logic_vector(3 downto 0) :=(others=>'0');
  signal sck_o          : std_logic;
  signal full    : std_logic;

begin
sck_out  <= sck_o;
process(sysclk)
begin
      if (sysclk'event and sysclk = '1') then  --reset
      if (reset = '1') then
            ss_n       <= (others=>'1');  --AD5553 idle CS =1
            out_reg    <= (others=>'0');
            clkdiv_cnt  <= (others=>'0');
            bit_cnt    <= (others=>'0');
            spi_o    <= '1';
            sck_o    <= '0';    -- AD5553 SCK idle is 0
            state    <= idle;
   full    <= '0';
      else
if(full = '0') then
   out_reg <= data_in ;
   full <= '1';
end if;

         case state is
         when idle =>

                  state    <= shift;
                  spi_o    <= out_reg(13);
                  out_reg <= out_reg(12 downto 0) & '0';
                  sck_o    <= '0';
         when shift =>
               clkdiv_cnt <= clkdiv_cnt + '1';
               if (clkdiv_cnt(2 downto 0)="111") then
                  sck_o    <= not sck_o;
               end if;

   if (clkdiv_cnt = "1111") then
                  spi_o    <= out_reg(13);
                  out_reg <= out_reg(12 downto 0) & '0';
                  bit_cnt <= bit_cnt + '1';
               end if;

   if (bit_cnt="1110" and clkdiv_cnt = "1111") then
                  state    <= stop;
                  sck_o    <= '0';
                  spi_o    <= '1';
               end if;

   when stop =>
               state    <= idle;
               sck_o    <= '0';
               spi_o    <= '1';
               clkdiv_cnt  <= (others=>'0');
               bit_cnt    <= (others=>'0');
   full    <= '0';
         when others =>
               state    <= idle;
         end case;
      end if;
      end if;
end process;
end b;

其中out_reg    一直是0，在idle状态赋不上值，大家看是怎么回事

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