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library IEEE;3 W8 v7 p3 d! O/ F F
use IEEE.STD_LOGIC_1164.ALL;
* S+ A/ F" }" R4 f- p6 r' y) |2 duse IEEE.STD_LOGIC_ARITH.ALL;9 M9 R: Z& K9 ]' R( ~
use IEEE.STD_LOGIC_UNSIGNED.ALL;! O2 k3 _% D; v
entity spi is
& ?+ ], k% X# J, sport
8 W7 L+ |" |" R* ? (4 B; r& h1 J4 {+ \
reset : in std_logic; --global reset signal) ~% h( A9 _0 k% Z9 B
sysclk : in std_logic; -- systerm clock
( k9 z" u9 T) w% I; p* {, o data_in : in std_logic_vector(13 downto 0);
/ {+ P# i$ l% L- H6 a, D9 u6 l spi_o : out std_logic;
2 t7 ^) Q3 j7 `6 h4 `; } sck_out : out std_logic;2 g- w0 `# l( ]5 W: [4 [' ~6 q- z, _" p
ss_n : out std_logic_vector(1 downto 0)4 f2 q* @0 N: ^& B$ [
);* B* E1 k6 N' N4 _6 _7 M5 S
end spi;" L! N. m7 Q% O; S( ?* v
architecture b of spi is4 D+ E" T- f9 U2 ?* i2 S* e' v* c
type state_type is (idle,shift,stop); -- data type define
, _! I8 I0 h8 K+ ~4 n signal state : state_type;+ g) ]2 n6 K# I' X2 k; V
signal out_reg : std_logic_vector(13 downto 0):=(others=>'0');
2 B* Q- C9 H4 l# J1 L9 G; z" O: q; @ signal clkdiv_cnt : std_logic_vector(3 downto 0) :=(others=>'0'); I2 y! I+ }0 D- ?3 b
signal bit_cnt : std_logic_vector(3 downto 0) :=(others=>'0');3 J+ e; K+ y+ i1 ^ r% E
signal sck_o : std_logic; z* X; R1 _* X! T
signal full : std_logic;4 ?: g* l. n; c* R
+ N' H/ z+ ~. X" hbegin
$ R$ k! |9 J K sck_out <= sck_o;
0 N4 p( V d a" @. I process(sysclk)7 s; A8 ?+ T! j
begin2 J: m$ a, k# [- r: ?: e
if (sysclk'event and sysclk = '1') then --reset
4 k: ]' r) E+ F if (reset = '1') then/ }1 l, i* `- Z9 w6 A! e- A0 g, `
ss_n <= (others=>'1'); --AD5553 idle CS =1
! a- _& R! |1 r% f& Z out_reg <= (others=>'0');
; ]( g% U0 q6 h6 ^! e clkdiv_cnt <= (others=>'0');
: ~0 _8 n* x, G3 Q bit_cnt <= (others=>'0');# x$ k8 Z- I2 v2 q0 v+ n
spi_o <= '1';
/ `6 q# f. N' r2 _' ~ sck_o <= '0'; -- AD5553 SCK idle is 0
$ g* Y. _; Y- x1 g state <= idle;( }" m5 e9 N% m
full <= '0';
; e( h: x) U8 y% _* s; K7 S* Q7 A else 7 w8 V8 x1 p# D2 h
if(full = '0') then
4 h# w% h) `+ H out_reg <= data_in ;
( p# _3 u0 ]: n% ~; | full <= '1';
4 o r9 c% K6 g- V end if;+ D9 O( p0 J* `4 o9 `
$ [! N! j5 X* ?& [# \1 x case state is 8 W: z+ q) Q/ b8 j v( x
when idle =>
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4 E1 e& V8 d7 j5 e7 b1 ?- | state <= shift;4 Z+ {- k3 g0 F: K9 ^. o
spi_o <= out_reg(13);
( W, `% `5 M1 s' m$ ?# d, q! c O# t out_reg <= out_reg(12 downto 0) & '0';
1 h; p: o* t7 { sck_o <= '0';
& c/ l8 R( n2 y8 G) ` when shift =>
- J' h6 g7 X7 \# F: D$ W clkdiv_cnt <= clkdiv_cnt + '1';
( p0 \- ]2 H# I. y5 K9 n if (clkdiv_cnt(2 downto 0)="111") then5 `7 f5 J! A! q4 u2 S/ |4 x! T
sck_o <= not sck_o;
- L6 D# B/ a* L8 r9 i end if;3 F4 W1 j/ ~$ t. f
' H& n c( w. b% q if (clkdiv_cnt = "1111") then
1 I- Z" ^3 l7 q4 D$ l spi_o <= out_reg(13);7 f' ^7 T4 J. b9 g- y- [
out_reg <= out_reg(12 downto 0) & '0';
* z# @3 U1 |* Z) b- r bit_cnt <= bit_cnt + '1';4 N8 Z, c! y/ v9 M; c, m1 A
end if;
: m! j0 H8 b) x; _: X 8 s Q! @# S+ C3 w
if (bit_cnt="1110" and clkdiv_cnt = "1111") then
, o" b9 t4 t0 k0 {$ f state <= stop;
/ S. u! G/ x6 l+ s sck_o <= '0';
, K; ]; \5 u: h. @# b! Y3 B spi_o <= '1';" E% R/ @$ ?5 D4 _
end if;- v1 B* A" W3 y: T
! E4 j) p4 p+ J) O( l
when stop =>, }+ N3 T8 S. P$ H) w% s$ X
state <= idle;
7 R$ b% x, X' J; C+ Z! O sck_o <= '0';
) E! S3 D5 G* |! J+ X% l4 R spi_o <= '1';
* u, s9 A/ d- F, d) h clkdiv_cnt <= (others=>'0');
; ?! n' f2 e4 t6 |$ T bit_cnt <= (others=>'0');
7 b2 h/ `. C# \$ A( s; U# w full <= '0';* k7 Q5 `. I; n9 Q: {4 }# _- M, H
when others =>2 o0 _) j( M0 r6 u$ B
state <= idle;
7 v" w1 w- |' X) i- X2 _ c) ~ end case;1 d: `1 b8 v9 d7 C
end if;
% u" w# H* R+ H3 y end if;
* B- k9 t ]2 q/ A0 m end process;
; V( V2 r/ }" q. ^end b;9 [1 `+ e0 S9 M
& P ~7 e4 N0 s- ^; o1 e- H
" M6 ^! ^9 @; \1 R+ p) f+ K+ x) }其中out_reg 一直是0,在idle状态赋不上值,大家看是怎么回事$ q* w% h" x8 T6 P6 p1 Q( T
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