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Warning (10631): VHDL Process Statement warning at my_latch.vhd(37): inferring latch(es) for signal or variable "out_0", which holds its previous value in one or more paths through the process;
. e, q, g/ H0 l- `& r5 lWarning: Found combinational loop of 1 nodes
. e$ U: F; k% w9 \ Warning: Node "my_latch:inst14|out_3~16";& _7 v5 J2 ]: R; ^, g7 ]
这两个警告如何消除啊??
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* N6 ^7 o2 b( J: U3 A. J6 d, iWarning (10631): VHDL Process Statement warning at my_latch.vhd(37): inferring latch(es) for signal or variable "out_0", which holds its previous value in one or more paths through the process;
& O- u& K Q( _4 q( m% N7 V这个警告的话,是因为编写VHDL语言时,用了不完整的IF语句,产生了锁存器,为什么很多资料中提到在VHDL语言中尽量避免使用不完整的IF语句,也就是说尽量不要使用锁存器??但在实际使用中确实需要实现输出锁存,该如何解决啊?谢谢啊!!! |
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