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本帖最后由 金志峰 于 2020-11-5 01:02 编辑
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" }$ m+ n* y- X& [Hotfix_SPB17.40.012
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百度云链接: https://pan.baidu.com/s/1udP4SQr7pERhzD2tHlMuCA 提取码: a6q4 3 H8 U: @/ v8 l- y
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Fixed CCRs: SPB 17.4 HF012 - Date: 10-30-2020
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CCRID Product ProductLevel2 Title( ?. g% l8 q* l, R+ J
========================================================================
7 s8 Y* L' L7 N3 p; q* e! r2324284 ADV_PKG_ROUTER OTHER APR fails to route and does not use the BBVias.
$ K; S# K M1 O2346605 ADW ADWSERVER Librarian license incorrectly checked out by data nodes during LiveBOM creation( z# M8 ?7 [! x& m5 B# {6 n% E7 m. @
2317952 allegro_EDITOR 3D_CANVAS Allegro 3D Canvas does not show STEP models placed on paste mask correctly
0 d/ J- B0 t8 q& B5 u4 q. O+ l2192222 ALLEGRO_EDITOR DFM Allegro PCB Editor crashed during check 'Mask' with the setting of 'Via Partially Covered With Mask Opening'+ g% j, y+ p8 G
2197203 ALLEGRO_EDITOR DFM Wrong alert on Soldermask sliver checking0 c7 j; C2 \6 t A2 R
2280806 ALLEGRO_EDITOR DFM Importing netlist results in error related to illegal subclass (SPMHNI-234)
2 o( H3 s3 X* j' r0 ?4 l5 {5 j2262559 ALLEGRO_EDITOR DRC_CONSTR Copper Features: Minimum Acid traps Angle gives false DRC6 n9 O, z0 j( N7 d4 w6 f0 h
2319385 ALLEGRO_EDITOR INTERACTIV Find by Query for Via structures is not working with Symbol field filter
$ F/ g; B' z, P* D+ K2279179 ALLEGRO_EDITOR PLOTTING File> Plot ignores the printer setup properties and always prints in Portrait format. B" E) a4 Z& p) P( e5 z) h" j) }
2306419 ALLEGRO_EDITOR PLOTTING File -> Plot -> Properties only accepts 'Portrait' and not 'Landscape'! W( r, v6 c$ F" u& \
2333930 ALLEGRO_EDITOR PLOTTING The File> Plot always prints PCB in portrait( t) I" C* Y8 ]
2327088 ALLEGRO_EDITOR SHAPE Design Sync gets a SAV file reported but there is no information about the cause of the problem in netrev.lst
+ k0 t- i% i- {2331947 ALLEGRO_EDITOR SHAPE When adding shape, pressing the 'Shift' key ends the process
5 F* c/ ^! E4 P# Q" p2339008 ALLEGRO_EDITOR STREAM_IF Stream import view layers give error
9 f- V" H+ R6 J* n1 C2328322 APD DRC_CONSTRAIN Database getting corrupted during artwork creation even after running DBDoctor.
( l: E f0 V" u; J2280535 APD REPORTS About the missing fillets report result: Ignore fillets not generated inside via regular pad area
1 w$ E6 R5 j/ |! Q/ @" |2323629 CAPTURE OTHER Product unusable with DSN file: Operations have significant delays and application stops responding
+ J+ S" I7 ?/ L" h2 o B9 `/ w9 }9 X2261147 CONSTRAINT_MGR ANALYSIS Setting "Mechanical drill hole to conductor spacing" does not flag DRC! [/ b, b! K/ }( F
2330712 CONSTRAINT_MGR DATABASE Physical Constraints Set value cannot be modified6 i4 ^6 M6 p. x( }, W' i
2333755 CONSTRAINT_MGR SCHEM_FTB CM simplified out-of-sync pop-up form has clipped text. ]3 Q, w$ g _, u7 V
2235714 CONSTRAINT_MGR UI_FORMS Using the 'Change all design unit attributes…' pop-up menu option changes only the Min BB Via Gap value/ X ?6 R: f/ V9 D, f
2288109 CONSTRAINT_MGR UI_FORMS Column sort is not working for match group$ O6 a5 O$ l7 l" \: T- R7 M( t( ?1 w
2306092 CONSTRAINT_MGR UI_FORMS Display Constraints shows empty constraints in Constraint Manager" J8 ?. \% x$ l h" z; e
2332795 CONSTRAINT_MGR UI_FORMS CMGR Worksheet colums are not sorted as per the columns definitions. _4 k& S; @( s. _5 l
2326995 PCB_LIBRARIAN SYMBOL_EDITOR Graphics and pin number locations are incorrect
7 [0 ~$ Q+ b$ u. `2 ?" [2280766 Pspice MODELEDITOR Error while converting Verilog-A model: p$ |+ d& G. E! f
2285008 PSPICE MODELEDITOR Model Editor crashes if file name does not match with IBIS model file name. ~0 ^+ c4 w3 J3 R
2346048 PULSE ADHOC Importing or File New Block as a designer working on a design that has been shared does not work3 e# Q) V+ W7 e) A* O2 `
2346643 PULSE ADHOC System Capture crashes when adding a part
2 L% z2 `% l) ]2214054 PULSE UNIFIED_SEARC Unified Search does not honor operating system HTTP proxy settings
( H" }2 ]: n- J1 B2325635 PULSE UNIFIED_SEARC Errors in Unified Search (vista) using customer database
0 u, s6 R/ `2 ?: q2326089 PULSE UNIFIED_SEARC Unified search does not show EDM parts and gives error (SPPSUN-1)* N+ O; |& p8 ^1 u
2329750 PULSE VERSION_ON_SA Live BOM data disappearing from migrated DE-HDL design with variants
* I& L: ~6 [6 }$ j2319690 SIP_LAYOUT EDIT_ETCH Allegro SiP Layout XL - Auto-I Breakout Closest End excessive run time: Takes long time to complete2 ` F% `! Z* g; W
2320336 SIP_LAYOUT EDIT_ETCH Auto-Interactive Pin Swapping /Auto Breakout cannot route in design- s' a- k+ g4 X$ H3 a0 I7 f& h
2333679 SIP_LAYOUT INTERACTIVE Add Offset Via Angle Field. c% G/ q) r5 X G: j' ~ b* N& l8 ~
2344732 SYSTEM_CAPTURE DESIGN_CORRUP Page cannot be loaded because the design database is corrupt$ I) X4 a4 |+ ]- B/ k6 Q
2342258 SYSTEM_CAPTURE MISCELLANEOUS System Capture is impacting PCB Editor GUI Readability by Setting QT_SCALE_FACTOR* v* W* F8 J# Z
2337610 SYSTEM_CAPTURE PART_MANAGER System Capture crashes when updating a part with changed PACK_TYPE and Symbol
# P) m7 j) V# O( }0 e! a9 S2341550 SYSTEM_CAPTURE VERSION_ON_SA Projects migrated from HotFix 002 to HotFix 010 have slow peRFormance2 S5 y+ w& {5 [' j+ @
2341591 SYSTEM_CAPTURE WIRING Moving wire segments still leaves odd pieces of wires7 [ p! O" \4 o+ s3 u# u
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发表于 2020-11-5 00:58
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