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本帖最后由 金志峰 于 2020-11-5 01:02 编辑
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Hotfix_SPB17.40.012. K2 J& d W1 b' ]/ a0 r8 h
0 x% L/ C1 T( h6 t8 ^) x百度云链接: https://pan.baidu.com/s/1udP4SQr7pERhzD2tHlMuCA 提取码: a6q4 / e% G6 k: s; K K) J& S2 `
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% i, n$ s1 @9 [/ dFixed CCRs: SPB 17.4 HF012 - Date: 10-30-2020
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" T; @" f* K6 a& k=============================================================. |* d4 Q: o$ ?* S$ w
CCRID Product ProductLevel2 Title
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2324284 ADV_PKG_ROUTER OTHER APR fails to route and does not use the BBVias./ X) R) S; G0 ]6 \' d$ W
2346605 ADW ADWSERVER Librarian license incorrectly checked out by data nodes during LiveBOM creation
$ U, {4 ~1 x: Y8 M- g5 Q* {2317952 allegro_EDITOR 3D_CANVAS Allegro 3D Canvas does not show STEP models placed on paste mask correctly
% u+ p3 Z7 Q$ N4 `- s' i# l2192222 ALLEGRO_EDITOR DFM Allegro PCB Editor crashed during check 'Mask' with the setting of 'Via Partially Covered With Mask Opening' ^' F& f7 H: X5 T
2197203 ALLEGRO_EDITOR DFM Wrong alert on Soldermask sliver checking# Q! t2 k X. ?! d/ H- h
2280806 ALLEGRO_EDITOR DFM Importing netlist results in error related to illegal subclass (SPMHNI-234): V9 @! u' C0 L$ @
2262559 ALLEGRO_EDITOR DRC_CONSTR Copper Features: Minimum Acid traps Angle gives false DRC9 X% y/ |1 n! S& D2 z* M% V. o9 F
2319385 ALLEGRO_EDITOR INTERACTIV Find by Query for Via structures is not working with Symbol field filter* W( ^ U8 \' V9 A- a+ O+ R3 ^4 b: T" _
2279179 ALLEGRO_EDITOR PLOTTING File> Plot ignores the printer setup properties and always prints in Portrait format.+ d" N9 B% U" H( I- `( o- M. L
2306419 ALLEGRO_EDITOR PLOTTING File -> Plot -> Properties only accepts 'Portrait' and not 'Landscape'
% m2 q- d: @# m" X2333930 ALLEGRO_EDITOR PLOTTING The File> Plot always prints PCB in portrait
H7 E4 N0 a7 e! ~6 }; l Q5 Y2327088 ALLEGRO_EDITOR SHAPE Design Sync gets a SAV file reported but there is no information about the cause of the problem in netrev.lst
! L8 s, n+ R; G# h `+ y2331947 ALLEGRO_EDITOR SHAPE When adding shape, pressing the 'Shift' key ends the process! S, K2 t! Z# d( U" ~7 h5 w
2339008 ALLEGRO_EDITOR STREAM_IF Stream import view layers give error
' g z. D6 ~! V1 J2328322 APD DRC_CONSTRAIN Database getting corrupted during artwork creation even after running DBDoctor.
: g: v) d9 S/ J8 ^2280535 APD REPORTS About the missing fillets report result: Ignore fillets not generated inside via regular pad area
4 d2 a" q4 t$ h0 }, ^$ y8 P, }2323629 CAPTURE OTHER Product unusable with DSN file: Operations have significant delays and application stops responding
' S. h) k" T% a2 c( P& f! m* K' ]2261147 CONSTRAINT_MGR ANALYSIS Setting "Mechanical drill hole to conductor spacing" does not flag DRC+ r( ]( ? T) {, Z% t* r \
2330712 CONSTRAINT_MGR DATABASE Physical Constraints Set value cannot be modified0 j4 G8 ] O8 m5 }
2333755 CONSTRAINT_MGR SCHEM_FTB CM simplified out-of-sync pop-up form has clipped text6 W( E- q6 Y! z7 ]
2235714 CONSTRAINT_MGR UI_FORMS Using the 'Change all design unit attributes…' pop-up menu option changes only the Min BB Via Gap value+ Y) U2 W R! T
2288109 CONSTRAINT_MGR UI_FORMS Column sort is not working for match group
! k" `8 y: {$ s! y C2306092 CONSTRAINT_MGR UI_FORMS Display Constraints shows empty constraints in Constraint Manager! _% y3 J+ c3 A! C1 x
2332795 CONSTRAINT_MGR UI_FORMS CMGR Worksheet colums are not sorted as per the columns definitions: I5 }' I0 U9 u# z; H; {
2326995 PCB_LIBRARIAN SYMBOL_EDITOR Graphics and pin number locations are incorrect
: g6 I3 n' A( v( U7 J* p2280766 Pspice MODELEDITOR Error while converting Verilog-A model% B7 s& \, L4 {. i, o
2285008 PSPICE MODELEDITOR Model Editor crashes if file name does not match with IBIS model file name" s# q5 E0 i1 K* ~; G P
2346048 PULSE ADHOC Importing or File New Block as a designer working on a design that has been shared does not work
9 [/ d: V/ T+ ?8 X* n, O$ U8 w2346643 PULSE ADHOC System Capture crashes when adding a part8 [* \: X' R/ I6 q& _7 f5 g& n
2214054 PULSE UNIFIED_SEARC Unified Search does not honor operating system HTTP proxy settings
) }# M& F {0 S2325635 PULSE UNIFIED_SEARC Errors in Unified Search (vista) using customer database9 g- l7 v1 u* Q+ g. a D
2326089 PULSE UNIFIED_SEARC Unified search does not show EDM parts and gives error (SPPSUN-1); y1 `/ V8 d' |% \9 L
2329750 PULSE VERSION_ON_SA Live BOM data disappearing from migrated DE-HDL design with variants n) R! ~3 d' C# G6 Z! i
2319690 SIP_LAYOUT EDIT_ETCH Allegro SiP Layout XL - Auto-I Breakout Closest End excessive run time: Takes long time to complete: L+ S5 r* l; I
2320336 SIP_LAYOUT EDIT_ETCH Auto-Interactive Pin Swapping /Auto Breakout cannot route in design' e; {1 w* c% Z( I) S) K* p8 ?& ~6 z
2333679 SIP_LAYOUT INTERACTIVE Add Offset Via Angle Field
4 D4 Y" e/ q5 Q/ g; r' [# K5 E; }4 e2344732 SYSTEM_CAPTURE DESIGN_CORRUP Page cannot be loaded because the design database is corrupt, P( C3 |) w4 `
2342258 SYSTEM_CAPTURE MISCELLANEOUS System Capture is impacting PCB Editor GUI Readability by Setting QT_SCALE_FACTOR8 k2 h! B& X% H. u2 [/ s; \! p, {* a
2337610 SYSTEM_CAPTURE PART_MANAGER System Capture crashes when updating a part with changed PACK_TYPE and Symbol
6 b- G3 R5 c8 g- @2341550 SYSTEM_CAPTURE VERSION_ON_SA Projects migrated from HotFix 002 to HotFix 010 have slow peRFormance" S! k) m; E/ G) t* P2 {3 p
2341591 SYSTEM_CAPTURE WIRING Moving wire segments still leaves odd pieces of wires
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发表于 2020-11-5 00:58
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