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本帖最后由 金志峰 于 2020-11-5 01:02 编辑 3 K5 c4 H; G1 d. y7 e) i' E) s! z2 t1 f% l
6 a' C- h9 a. dHotfix_SPB17.40.012
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7 u A& J9 Z6 Q3 c% ^百度云链接: https://pan.baidu.com/s/1udP4SQr7pERhzD2tHlMuCA 提取码: a6q4 $ I1 T, H" C6 V. k! d% |' t
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Fixed CCRs: SPB 17.4 HF012 - Date: 10-30-2020
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- `+ a" X4 N: q6 Q3 LCCRID Product ProductLevel2 Title
3 W7 o6 j) R: ]6 q. n========================================================================
% {1 f0 u, Q( Z. Q2324284 ADV_PKG_ROUTER OTHER APR fails to route and does not use the BBVias.
2 ^3 _* z1 j# _" B5 x9 X9 d! ^2346605 ADW ADWSERVER Librarian license incorrectly checked out by data nodes during LiveBOM creation
; f# {! Y# n- T2317952 allegro_EDITOR 3D_CANVAS Allegro 3D Canvas does not show STEP models placed on paste mask correctly
* j& R2 h* I1 t4 l$ e- ?2192222 ALLEGRO_EDITOR DFM Allegro PCB Editor crashed during check 'Mask' with the setting of 'Via Partially Covered With Mask Opening'
# j- d; C6 ^ y3 W$ j3 R. m" r2197203 ALLEGRO_EDITOR DFM Wrong alert on Soldermask sliver checking
- s% h) y7 n8 h2280806 ALLEGRO_EDITOR DFM Importing netlist results in error related to illegal subclass (SPMHNI-234)1 j& B& j6 K( E- ?2 l" Z: z0 \$ s
2262559 ALLEGRO_EDITOR DRC_CONSTR Copper Features: Minimum Acid traps Angle gives false DRC, ^3 e# b4 M; A$ W: o
2319385 ALLEGRO_EDITOR INTERACTIV Find by Query for Via structures is not working with Symbol field filter
7 j+ C' n5 U3 U8 }; M2279179 ALLEGRO_EDITOR PLOTTING File> Plot ignores the printer setup properties and always prints in Portrait format.
6 K$ H9 {8 w# P1 k1 _2306419 ALLEGRO_EDITOR PLOTTING File -> Plot -> Properties only accepts 'Portrait' and not 'Landscape'( C6 i( V+ B) [) d# e
2333930 ALLEGRO_EDITOR PLOTTING The File> Plot always prints PCB in portrait
# s3 r; n& p9 `4 y2327088 ALLEGRO_EDITOR SHAPE Design Sync gets a SAV file reported but there is no information about the cause of the problem in netrev.lst
: m3 e" I- ^+ G4 q2 L2331947 ALLEGRO_EDITOR SHAPE When adding shape, pressing the 'Shift' key ends the process
+ @! |/ C5 b0 I2339008 ALLEGRO_EDITOR STREAM_IF Stream import view layers give error ^( f" h' m- s; W J# K
2328322 APD DRC_CONSTRAIN Database getting corrupted during artwork creation even after running DBDoctor.# f* w; @0 Z0 @. h7 j: n
2280535 APD REPORTS About the missing fillets report result: Ignore fillets not generated inside via regular pad area
; g! r5 q* Y3 V1 S3 C1 b2323629 CAPTURE OTHER Product unusable with DSN file: Operations have significant delays and application stops responding Z1 K% V5 n- b9 q5 w- P
2261147 CONSTRAINT_MGR ANALYSIS Setting "Mechanical drill hole to conductor spacing" does not flag DRC8 O/ k- S5 Q! J3 k+ Q* L( P0 P
2330712 CONSTRAINT_MGR DATABASE Physical Constraints Set value cannot be modified Q% Y% ? c( D- L3 Q
2333755 CONSTRAINT_MGR SCHEM_FTB CM simplified out-of-sync pop-up form has clipped text* F3 {: Z1 u1 o# H1 z/ w
2235714 CONSTRAINT_MGR UI_FORMS Using the 'Change all design unit attributes…' pop-up menu option changes only the Min BB Via Gap value- r, q) X( }* g' D4 r
2288109 CONSTRAINT_MGR UI_FORMS Column sort is not working for match group: K' F$ } w. q( f
2306092 CONSTRAINT_MGR UI_FORMS Display Constraints shows empty constraints in Constraint Manager) w5 b5 I3 K5 {$ w9 t
2332795 CONSTRAINT_MGR UI_FORMS CMGR Worksheet colums are not sorted as per the columns definitions
( A/ H+ u! d$ z! Z! |2326995 PCB_LIBRARIAN SYMBOL_EDITOR Graphics and pin number locations are incorrect
/ E% O6 \. U9 }. G3 W7 p5 Y2280766 Pspice MODELEDITOR Error while converting Verilog-A model
! q, v- |& i7 {2285008 PSPICE MODELEDITOR Model Editor crashes if file name does not match with IBIS model file name
) D6 f! g, {% J2346048 PULSE ADHOC Importing or File New Block as a designer working on a design that has been shared does not work
) b9 S7 |, N4 y7 v% m: C$ V2346643 PULSE ADHOC System Capture crashes when adding a part9 T+ g: [! q2 M; a" z
2214054 PULSE UNIFIED_SEARC Unified Search does not honor operating system HTTP proxy settings
- _7 U4 u( M0 b' ~& n2325635 PULSE UNIFIED_SEARC Errors in Unified Search (vista) using customer database4 i+ G# N. G) ?& q% }* U3 {$ S B
2326089 PULSE UNIFIED_SEARC Unified search does not show EDM parts and gives error (SPPSUN-1)
0 Z- P& b# D+ W+ `2 y; O4 x2329750 PULSE VERSION_ON_SA Live BOM data disappearing from migrated DE-HDL design with variants
9 y6 h5 b* v6 D% {- W' m; P+ i2319690 SIP_LAYOUT EDIT_ETCH Allegro SiP Layout XL - Auto-I Breakout Closest End excessive run time: Takes long time to complete+ ~: Z- z% q$ Y/ U" p
2320336 SIP_LAYOUT EDIT_ETCH Auto-Interactive Pin Swapping /Auto Breakout cannot route in design
- g8 w3 g: P; Z) _% _- R2333679 SIP_LAYOUT INTERACTIVE Add Offset Via Angle Field
3 r. o0 u, s6 d7 _6 q! M" k! x2344732 SYSTEM_CAPTURE DESIGN_CORRUP Page cannot be loaded because the design database is corrupt
1 C8 l: X$ @: Y2342258 SYSTEM_CAPTURE MISCELLANEOUS System Capture is impacting PCB Editor GUI Readability by Setting QT_SCALE_FACTOR% _7 q9 W5 u- @% q+ l
2337610 SYSTEM_CAPTURE PART_MANAGER System Capture crashes when updating a part with changed PACK_TYPE and Symbol
; |" i2 P) H) L& y$ V! ]2 D7 l2341550 SYSTEM_CAPTURE VERSION_ON_SA Projects migrated from HotFix 002 to HotFix 010 have slow peRFormance9 z- p; f" e2 q/ j- o
2341591 SYSTEM_CAPTURE WIRING Moving wire segments still leaves odd pieces of wires
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发表于 2020-11-5 00:58
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