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本帖最后由 金志峰 于 2020-11-5 01:02 编辑 3 Q5 V Y+ `% m' D& X1 J
# e! q! o9 s6 w' G+ X0 V! zHotfix_SPB17.40.012- B4 x$ M0 c4 U
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百度云链接: https://pan.baidu.com/s/1udP4SQr7pERhzD2tHlMuCA 提取码: a6q4
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& W3 i+ h+ c) y# w3 ^Fixed CCRs: SPB 17.4 HF012 - Date: 10-30-2020
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4 b' f% e4 B" g1 ]# n7 wCCRID Product ProductLevel2 Title' D8 Y& y) a. B9 ]2 P
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2324284 ADV_PKG_ROUTER OTHER APR fails to route and does not use the BBVias.
4 B# u( k$ P7 Z+ Y2346605 ADW ADWSERVER Librarian license incorrectly checked out by data nodes during LiveBOM creation% |' i4 F* E; |: }
2317952 allegro_EDITOR 3D_CANVAS Allegro 3D Canvas does not show STEP models placed on paste mask correctly
4 b' o0 p3 k5 M; C2192222 ALLEGRO_EDITOR DFM Allegro PCB Editor crashed during check 'Mask' with the setting of 'Via Partially Covered With Mask Opening'
( c# I2 j! `- B4 }4 L2 j% I2197203 ALLEGRO_EDITOR DFM Wrong alert on Soldermask sliver checking
8 y; [) |5 G* ?6 F/ l$ ]2280806 ALLEGRO_EDITOR DFM Importing netlist results in error related to illegal subclass (SPMHNI-234)
; S8 r$ [! J5 m7 q% ^* \) n2262559 ALLEGRO_EDITOR DRC_CONSTR Copper Features: Minimum Acid traps Angle gives false DRC% Y+ z$ _1 l X, ?
2319385 ALLEGRO_EDITOR INTERACTIV Find by Query for Via structures is not working with Symbol field filter+ c2 R$ v$ |+ Q
2279179 ALLEGRO_EDITOR PLOTTING File> Plot ignores the printer setup properties and always prints in Portrait format.: l( n/ G3 }0 e5 m* }$ @5 k
2306419 ALLEGRO_EDITOR PLOTTING File -> Plot -> Properties only accepts 'Portrait' and not 'Landscape'! h- c7 U& @9 {( g1 `
2333930 ALLEGRO_EDITOR PLOTTING The File> Plot always prints PCB in portrait
* |0 g+ z' a% S8 G' y2327088 ALLEGRO_EDITOR SHAPE Design Sync gets a SAV file reported but there is no information about the cause of the problem in netrev.lst
c, O6 m3 K6 J' d2 a+ A2331947 ALLEGRO_EDITOR SHAPE When adding shape, pressing the 'Shift' key ends the process
" k$ v5 H, I+ K5 i0 F* |' ]2339008 ALLEGRO_EDITOR STREAM_IF Stream import view layers give error
2 l& G5 R& z1 ]' s- ?2328322 APD DRC_CONSTRAIN Database getting corrupted during artwork creation even after running DBDoctor.
7 ^& z9 y# p+ m& g, C8 m& f6 ^( I2280535 APD REPORTS About the missing fillets report result: Ignore fillets not generated inside via regular pad area
. Q S: e4 @) B* f7 `; C5 j. h2323629 CAPTURE OTHER Product unusable with DSN file: Operations have significant delays and application stops responding
' F- i# u4 V" ^) P5 R7 \/ I2261147 CONSTRAINT_MGR ANALYSIS Setting "Mechanical drill hole to conductor spacing" does not flag DRC
$ M; i" y. M. h0 @$ R3 S& H2330712 CONSTRAINT_MGR DATABASE Physical Constraints Set value cannot be modified7 F& s5 q9 E9 j1 B- f/ H7 z( [ G
2333755 CONSTRAINT_MGR SCHEM_FTB CM simplified out-of-sync pop-up form has clipped text
+ x# V$ o- }' ?2235714 CONSTRAINT_MGR UI_FORMS Using the 'Change all design unit attributes…' pop-up menu option changes only the Min BB Via Gap value
+ p$ A& t* k7 S( `" ~3 l2288109 CONSTRAINT_MGR UI_FORMS Column sort is not working for match group9 _. K8 n- p* j
2306092 CONSTRAINT_MGR UI_FORMS Display Constraints shows empty constraints in Constraint Manager" g, s* o' E5 g3 ^! |/ _! Y* r
2332795 CONSTRAINT_MGR UI_FORMS CMGR Worksheet colums are not sorted as per the columns definitions
$ j F/ F% | e' I8 _2 O% c2326995 PCB_LIBRARIAN SYMBOL_EDITOR Graphics and pin number locations are incorrect% Q) Y" W, z0 \8 x
2280766 Pspice MODELEDITOR Error while converting Verilog-A model$ i" N* D0 Z+ ?+ r4 N
2285008 PSPICE MODELEDITOR Model Editor crashes if file name does not match with IBIS model file name- N! x3 a% G$ d& M
2346048 PULSE ADHOC Importing or File New Block as a designer working on a design that has been shared does not work7 W! J1 f# u* W" [/ `
2346643 PULSE ADHOC System Capture crashes when adding a part5 H) P) y. { b2 N% h
2214054 PULSE UNIFIED_SEARC Unified Search does not honor operating system HTTP proxy settings
3 u4 r4 m; `7 T) B, N, d. C4 j( K2325635 PULSE UNIFIED_SEARC Errors in Unified Search (vista) using customer database
* s+ {: V( D. q* g: e1 e4 N& E2326089 PULSE UNIFIED_SEARC Unified search does not show EDM parts and gives error (SPPSUN-1)
2 x" X" @& O4 ^% o- E8 e2329750 PULSE VERSION_ON_SA Live BOM data disappearing from migrated DE-HDL design with variants
/ h. Y; {. e& `* u- t; v2319690 SIP_LAYOUT EDIT_ETCH Allegro SiP Layout XL - Auto-I Breakout Closest End excessive run time: Takes long time to complete; @. v: \4 Y8 ~# _8 m& A
2320336 SIP_LAYOUT EDIT_ETCH Auto-Interactive Pin Swapping /Auto Breakout cannot route in design
1 p# d" S7 E0 ], T5 H' C9 W2333679 SIP_LAYOUT INTERACTIVE Add Offset Via Angle Field
/ W6 }! i9 [: n [! J/ `: w/ b2344732 SYSTEM_CAPTURE DESIGN_CORRUP Page cannot be loaded because the design database is corrupt
1 S' w6 R6 ]' H$ P* ^2342258 SYSTEM_CAPTURE MISCELLANEOUS System Capture is impacting PCB Editor GUI Readability by Setting QT_SCALE_FACTOR4 H7 l* t$ u( R% v! G% l
2337610 SYSTEM_CAPTURE PART_MANAGER System Capture crashes when updating a part with changed PACK_TYPE and Symbol
5 D7 {$ l/ T4 \: Y, P1 Y1 I9 {3 Z2341550 SYSTEM_CAPTURE VERSION_ON_SA Projects migrated from HotFix 002 to HotFix 010 have slow peRFormance' \/ K9 c) y! ]! W! x) C5 \
2341591 SYSTEM_CAPTURE WIRING Moving wire segments still leaves odd pieces of wires
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发表于 2020-11-5 00:58
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