|
|
EDA365欢迎您登录！
您需要 登录 才可以下载或查看，没有帐号？注册
x
本帖最后由 auto1860 于 2020-11-4 13:30 编辑
, Y2 D' t2 r; o* J9 S
W( e) q& I* J+ g- f2 m链接：https://pan.baidu.com/s/1f4DTDBhhjcKz4On13yCxSg : d! }/ s# M3 Q! W
4 I, y; o# Q" S q, z. p
Fixed CCRs: SPB 17.4 HF0120 V+ q4 K3 \* C# U+ V
10-30-2020: y: T& @/ s- D p% l( P. l
========================================================================================================================================================
, a* {9 ?; v8 M5 dCCRID Product ProductLevel2 Title: E5 | H1 m- u6 I
========================================================================================================================================================
- y. C5 y% N- ]3 F2 s. @6 x' X2 y2324284 ADV_PKG_ROUTER OTHER APR fails to route and does not use the BBVias.0 L7 M4 u B1 m4 y- {
2346605 ADW ADWSERVER Librarian license incorrectly checked out by data nodes during LiveBOM creation
+ Z6 |, A( w" \2317952 allegro_EDITOR 3D_CANVAS Allegro 3D Canvas does not show STEP models placed on paste mask correctly+ L+ u7 b' [4 ^; K2 B$ n% w
2192222 ALLEGRO_EDITOR DFM Allegro PCB Editor crashed during check 'Mask' with the setting of 'Via Partially Covered With Mask Opening'
9 q H, y @: t% R* Q: k# x, B R2197203 ALLEGRO_EDITOR DFM Wrong alert on Soldermask sliver checking
0 v. W& A! Y' t+ t2280806 ALLEGRO_EDITOR DFM Importing netlist results in error related to illegal subclass (SPMHNI-234)
! o9 h2 o8 ]4 e8 t- x) L/ @2262559 ALLEGRO_EDITOR DRC_CONSTR Copper Features: Minimum Acid traps Angle gives false DRC
' X. Y# A# x2 o& e9 F( f2319385 ALLEGRO_EDITOR INTERACTIV Find by Query for Via structures is not working with Symbol field filter3 U, x. V# r2 Z/ x" H6 j2 Y4 a
2279179 ALLEGRO_EDITOR PLOTTING File> Plot ignores the printer setup properties and always prints in Portrait format./ S1 d! _1 M7 |
2306419 ALLEGRO_EDITOR PLOTTING File -> Plot -> Properties only accepts 'Portrait' and not 'Landscape'5 l4 o3 }: L A+ }: X* ~3 ]
2333930 ALLEGRO_EDITOR PLOTTING The File> Plot always prints PCB in portrait
9 u. a$ ?# f3 S/ w, U% s4 ^2327088 ALLEGRO_EDITOR SHAPE Design Sync gets a SAV file reported but there is no information about the cause of the problem in netrev.lst' |7 y9 @1 Y( I$ M& E; M
2331947 ALLEGRO_EDITOR SHAPE When adding shape, pressing the 'Shift' key ends the process: S0 Z/ k. K2 h6 @. A& g8 n
2339008 ALLEGRO_EDITOR STREAM_IF Stream import view layers give error
: b3 V' e6 z2 t4 D3 k2328322 APD DRC_CONSTRAIN Database getting corrupted during artwork creation even after running DBDoctor.
9 n( I: t' a/ K0 W9 p2280535 APD REPORTS About the missing fillets report result: Ignore fillets not generated inside via regular pad area
7 N7 H; n: o" X! N Z2323629 CAPTURE OTHER Product unusable with DSN file: Operations have significant delays and application stops responding
+ ^0 _4 `0 d1 V. H1 }5 M2261147 CONSTRAINT_MGR ANALYSIS Setting "Mechanical drill hole to conductor spacing" does not flag DRC) v4 e2 }: z+ g
2330712 CONSTRAINT_MGR DATABASE Physical Constraints Set value cannot be modified
: f, X4 y4 S' O r! K n2333755 CONSTRAINT_MGR SCHEM_FTB CM simplified out-of-sync pop-up form has clipped text
, l. s# e D+ T2235714 CONSTRAINT_MGR UI_FORMS Using the 'Change all design unit attributes...' pop-up menu option changes only the Min BB Via Gap value
1 M4 H4 B- N0 s2 n# ]2288109 CONSTRAINT_MGR UI_FORMS Column sort is not working for match group0 y- K3 @$ u: y- Z
2306092 CONSTRAINT_MGR UI_FORMS Display Constraints shows empty constraints in Constraint Manager+ e5 s5 i2 |9 Q6 H0 O; T" _
2332795 CONSTRAINT_MGR UI_FORMS CMGR Worksheet colums are not sorted as per the columns definitions4 s: j+ E' \+ f# ?/ ~5 m7 {8 [% I3 |
2326995 PCB_LIBRARIAN SYMBOL_EDITOR Graphics and pin number locations are incorrect- I }+ _7 C8 _ ~
2280766 Pspice MODELEDITOR Error while converting Verilog-A model
3 C1 D# |9 b, q r' r0 G2285008 PSPICE MODELEDITOR Model Editor crashes if file name does not match with IBIS model file name
" T! I! d2 c: a* q4 s6 _4 h2346048 PULSE ADHOC Importing or File New Block as a designer working on a design that has been shared does not work0 H% y' @: p) }8 n: I3 X& A& I
2346643 PULSE ADHOC System Capture crashes when adding a part
) z) S8 }# o4 ?% ?- Z1 f2214054 PULSE UNIFIED_SEARC Unified Search does not honor operating system HTTP proxy settings
% S8 X7 `- v v6 f Q: @2325635 PULSE UNIFIED_SEARC Errors in Unified Search (vista) using customer database0 C, D7 ~5 i1 }" K
2326089 PULSE UNIFIED_SEARC Unified search does not show EDM parts and gives error (SPPSUN-1)
- K% m/ G! [5 A! U1 `2 H* A* T6 p' ~2329750 PULSE VERSION_ON_SA Live BOM data disappearing from migrated DE-HDL design with variants# ] y' E, h: q/ M ^1 C% D% S
2319690 SIP_LAYOUT EDIT_ETCH Allegro SiP Layout XL - Auto-I Breakout Closest End excessive run time: Takes long time to complete6 X( {8 Z6 U5 n+ h
2320336 SIP_LAYOUT EDIT_ETCH Auto-Interactive Pin Swapping /Auto Breakout cannot route in design: A7 t' H* C. N6 A3 G: ]
2333679 SIP_LAYOUT INTERACTIVE Add Offset Via Angle Field
0 S: V# |3 o$ b: h; `/ h- d+ o' M: b2344732 SYSTEM_CAPTURE DESIGN_CORRUP Page cannot be loaded because the design database is corrupt& \( N5 W6 Z7 `9 I
2342258 SYSTEM_CAPTURE MISCELLANEOUS System Capture is impacting PCB Editor GUI Readability by Setting QT_SCALE_FACTOR
- _2 H: M) J2 [3 y& z( X2337610 SYSTEM_CAPTURE PART_MANAGER System Capture crashes when updating a part with changed PACK_TYPE and Symbol
6 o$ x) D0 e8 b2341550 SYSTEM_CAPTURE VERSION_ON_SA Projects migrated from HotFix 002 to HotFix 010 have slow peRFormance3 M' d- q* b! M# [% L4 E2 k1 H' l
2341591 SYSTEM_CAPTURE WIRING Moving wire segments still leaves odd pieces of wires3 V5 `* T, ~$ ]) Q# B P+ \
% U1 Q1 d( f% @( Y$ p6 `
|
|
/1 
发表于 2020-11-4 12:16
收藏
淘帖
支持！
反对！
发表于 2020-11-4 14:16
