|
EDA365欢迎您登录!
您需要 登录 才可以下载或查看,没有帐号?注册
x
本帖最后由 auto1860 于 2020-11-4 13:30 编辑
7 X2 ~$ D. ]) B; R3 k& j: s% {/ [% Q1 ~ G; e, F4 Y. h
链接:https://pan.baidu.com/s/1f4DTDBhhjcKz4On13yCxSg
. ~! o2 C6 ^- }% r+ D" z2 o" d, L
Fixed CCRs: SPB 17.4 HF012# b( X& e4 ^0 ?- c5 n2 v& r# O
10-30-2020. W3 k# _+ l$ A6 }* w, m6 o1 r( p8 \
========================================================================================================================================================) Z4 O+ m. J: Q
CCRID Product ProductLevel2 Title1 J6 e& }7 B2 e- J8 \- y' y/ Y
========================================================================================================================================================& e' C% n$ n+ X4 U
2324284 ADV_PKG_ROUTER OTHER APR fails to route and does not use the BBVias.
9 V2 L* v e2 q: U: q. f2346605 ADW ADWSERVER Librarian license incorrectly checked out by data nodes during LiveBOM creation
& G2 w# z7 a+ y8 n" K2317952 allegro_EDITOR 3D_CANVAS Allegro 3D Canvas does not show STEP models placed on paste mask correctly$ }8 R+ t1 I: j4 e, ^) A
2192222 ALLEGRO_EDITOR DFM Allegro PCB Editor crashed during check 'Mask' with the setting of 'Via Partially Covered With Mask Opening'
, q6 \; i: m& o" x7 T" K2197203 ALLEGRO_EDITOR DFM Wrong alert on Soldermask sliver checking+ R0 R& ?$ `' [$ j0 R
2280806 ALLEGRO_EDITOR DFM Importing netlist results in error related to illegal subclass (SPMHNI-234)
/ v9 \) B% s$ W# y& ~/ O2262559 ALLEGRO_EDITOR DRC_CONSTR Copper Features: Minimum Acid traps Angle gives false DRC
2 s& l- L7 t& i, R) o# ]; v% U2319385 ALLEGRO_EDITOR INTERACTIV Find by Query for Via structures is not working with Symbol field filter
% {$ Z: S+ x0 N2279179 ALLEGRO_EDITOR PLOTTING File> Plot ignores the printer setup properties and always prints in Portrait format.+ p9 S- ~, Q$ Z* Y" D
2306419 ALLEGRO_EDITOR PLOTTING File -> Plot -> Properties only accepts 'Portrait' and not 'Landscape'$ Y" I4 @2 p: [) E4 R& F. r, f
2333930 ALLEGRO_EDITOR PLOTTING The File> Plot always prints PCB in portrait4 P" C% D9 h- m& A; h
2327088 ALLEGRO_EDITOR SHAPE Design Sync gets a SAV file reported but there is no information about the cause of the problem in netrev.lst
m( j* \1 `% k* m$ g2331947 ALLEGRO_EDITOR SHAPE When adding shape, pressing the 'Shift' key ends the process
* l4 F( s. ~. M) ]/ e2339008 ALLEGRO_EDITOR STREAM_IF Stream import view layers give error# w- p6 u! Q, V0 m* ?4 Y( Z
2328322 APD DRC_CONSTRAIN Database getting corrupted during artwork creation even after running DBDoctor.- K4 M6 @% ]/ A$ B5 N6 W% X
2280535 APD REPORTS About the missing fillets report result: Ignore fillets not generated inside via regular pad area
5 ]& `4 q, q% t9 j9 ?2323629 CAPTURE OTHER Product unusable with DSN file: Operations have significant delays and application stops responding
* W4 ~6 d4 y! i8 t r& ]2261147 CONSTRAINT_MGR ANALYSIS Setting "Mechanical drill hole to conductor spacing" does not flag DRC7 }, c3 T8 g2 d6 F, M0 J
2330712 CONSTRAINT_MGR DATABASE Physical Constraints Set value cannot be modified
; [: p% G7 `4 N; W4 J/ u/ c9 @2333755 CONSTRAINT_MGR SCHEM_FTB CM simplified out-of-sync pop-up form has clipped text" |" {) _1 I. i1 b2 q/ \
2235714 CONSTRAINT_MGR UI_FORMS Using the 'Change all design unit attributes...' pop-up menu option changes only the Min BB Via Gap value
: {! k2 l, K, V* e2288109 CONSTRAINT_MGR UI_FORMS Column sort is not working for match group
' K& m- v$ a4 J$ `2306092 CONSTRAINT_MGR UI_FORMS Display Constraints shows empty constraints in Constraint Manager
7 p% H6 l+ Q. F( j; c4 [2 a2332795 CONSTRAINT_MGR UI_FORMS CMGR Worksheet colums are not sorted as per the columns definitions0 n% K5 y2 @! h& H8 |5 _2 A! o
2326995 PCB_LIBRARIAN SYMBOL_EDITOR Graphics and pin number locations are incorrect
9 d) O1 c( y; i7 H2280766 Pspice MODELEDITOR Error while converting Verilog-A model
; S' e& n! g$ @2285008 PSPICE MODELEDITOR Model Editor crashes if file name does not match with IBIS model file name) o- T2 f* {6 g% P7 G- D) g
2346048 PULSE ADHOC Importing or File New Block as a designer working on a design that has been shared does not work
/ u' [) M( h% s# F% c% B! I2346643 PULSE ADHOC System Capture crashes when adding a part
- i/ W- h) Z4 J7 m! K$ u2214054 PULSE UNIFIED_SEARC Unified Search does not honor operating system HTTP proxy settings
/ Q* g8 @( s1 ^: ^/ v+ k2325635 PULSE UNIFIED_SEARC Errors in Unified Search (vista) using customer database
- @0 A- S$ S) m2326089 PULSE UNIFIED_SEARC Unified search does not show EDM parts and gives error (SPPSUN-1)
h! B- i N/ u7 P2329750 PULSE VERSION_ON_SA Live BOM data disappearing from migrated DE-HDL design with variants
% d5 p: T7 m0 h5 W$ @, `; i) ?2319690 SIP_LAYOUT EDIT_ETCH Allegro SiP Layout XL - Auto-I Breakout Closest End excessive run time: Takes long time to complete$ N! ~$ M* J5 Y# h
2320336 SIP_LAYOUT EDIT_ETCH Auto-Interactive Pin Swapping /Auto Breakout cannot route in design' I9 {8 Q6 L) g# h7 K' N: `
2333679 SIP_LAYOUT INTERACTIVE Add Offset Via Angle Field
3 ~: o9 s* f) Y4 e2344732 SYSTEM_CAPTURE DESIGN_CORRUP Page cannot be loaded because the design database is corrupt
: q" Y3 A1 l) k' T" }; }1 X2342258 SYSTEM_CAPTURE MISCELLANEOUS System Capture is impacting PCB Editor GUI Readability by Setting QT_SCALE_FACTOR2 N) s5 L1 R3 a5 M$ L8 p
2337610 SYSTEM_CAPTURE PART_MANAGER System Capture crashes when updating a part with changed PACK_TYPE and Symbol) A9 ~! h1 x# x! l9 c
2341550 SYSTEM_CAPTURE VERSION_ON_SA Projects migrated from HotFix 002 to HotFix 010 have slow peRFormance. M% G/ {# l, B- H
2341591 SYSTEM_CAPTURE WIRING Moving wire segments still leaves odd pieces of wires) `+ K+ a1 M1 k& h# k
1 N4 Q6 d/ t# X% q( P
|
|