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本帖最后由 auto1860 于 2020-11-4 13:30 编辑 6 s" Q, p8 N; c: t
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链接：https://pan.baidu.com/s/1f4DTDBhhjcKz4On13yCxSg ( V0 o! M* X* H
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Fixed CCRs: SPB 17.4 HF012
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2324284 ADV_PKG_ROUTER OTHER APR fails to route and does not use the BBVias.
6 u* K7 k" [* l- t2346605 ADW ADWSERVER Librarian license incorrectly checked out by data nodes during LiveBOM creation1 a* ]* l) u/ E5 X
2317952 allegro_EDITOR 3D_CANVAS Allegro 3D Canvas does not show STEP models placed on paste mask correctly
* H! `' `1 M- w. p( {8 b6 S2192222 ALLEGRO_EDITOR DFM Allegro PCB Editor crashed during check 'Mask' with the setting of 'Via Partially Covered With Mask Opening': N& |9 R- z' T+ U9 f2 ]' F3 g! X
2197203 ALLEGRO_EDITOR DFM Wrong alert on Soldermask sliver checking. a9 X3 g/ K) h7 c8 f9 |
2280806 ALLEGRO_EDITOR DFM Importing netlist results in error related to illegal subclass (SPMHNI-234)1 C6 Z5 X7 }! W" A8 b
2262559 ALLEGRO_EDITOR DRC_CONSTR Copper Features: Minimum Acid traps Angle gives false DRC
- W4 B; v+ [8 d, T, Y2319385 ALLEGRO_EDITOR INTERACTIV Find by Query for Via structures is not working with Symbol field filter+ o" p& X+ ~6 D' w+ f
2279179 ALLEGRO_EDITOR PLOTTING File> Plot ignores the printer setup properties and always prints in Portrait format.* D+ }$ \& t# e2 o' r/ ?1 [% c
2306419 ALLEGRO_EDITOR PLOTTING File -> Plot -> Properties only accepts 'Portrait' and not 'Landscape'& I* Z$ g0 H' l) B) U( ]+ y1 y
2333930 ALLEGRO_EDITOR PLOTTING The File> Plot always prints PCB in portrait) g' o- S7 Y6 Z8 [$ S, m3 l
2327088 ALLEGRO_EDITOR SHAPE Design Sync gets a SAV file reported but there is no information about the cause of the problem in netrev.lst P# K! y0 H E0 {4 ~3 e" }
2331947 ALLEGRO_EDITOR SHAPE When adding shape, pressing the 'Shift' key ends the process9 |) _9 j5 ~+ H7 [1 D8 m7 l/ m
2339008 ALLEGRO_EDITOR STREAM_IF Stream import view layers give error4 Q7 _) E2 d; u9 a
2328322 APD DRC_CONSTRAIN Database getting corrupted during artwork creation even after running DBDoctor.
8 G2 r. X' a Y: l5 I4 ?5 ^$ s5 u2280535 APD REPORTS About the missing fillets report result: Ignore fillets not generated inside via regular pad area
$ ^6 Q" c+ F) s1 c# j& f/ r: Z0 c2323629 CAPTURE OTHER Product unusable with DSN file: Operations have significant delays and application stops responding
; v4 Z5 |4 V/ |; d& \8 u( R2261147 CONSTRAINT_MGR ANALYSIS Setting "Mechanical drill hole to conductor spacing" does not flag DRC. R- {# @: B8 D% j
2330712 CONSTRAINT_MGR DATABASE Physical Constraints Set value cannot be modified2 Y0 j# x8 {2 L5 K) ^& v
2333755 CONSTRAINT_MGR SCHEM_FTB CM simplified out-of-sync pop-up form has clipped text
2 v. t+ X3 \3 o! @% v0 r% t2235714 CONSTRAINT_MGR UI_FORMS Using the 'Change all design unit attributes...' pop-up menu option changes only the Min BB Via Gap value, C2 }+ {4 u) \4 T/ `% l; Z1 k2 S: z
2288109 CONSTRAINT_MGR UI_FORMS Column sort is not working for match group
. Z% v2 U' L" m7 R2306092 CONSTRAINT_MGR UI_FORMS Display Constraints shows empty constraints in Constraint Manager
6 C: j- A* A( K2332795 CONSTRAINT_MGR UI_FORMS CMGR Worksheet colums are not sorted as per the columns definitions
* Q* H0 b1 O5 y% h! r$ t: G2326995 PCB_LIBRARIAN SYMBOL_EDITOR Graphics and pin number locations are incorrect
4 L' T% J7 O, ]' y, _2280766 Pspice MODELEDITOR Error while converting Verilog-A model
" y" t: N# k2 a. l2285008 PSPICE MODELEDITOR Model Editor crashes if file name does not match with IBIS model file name: }) J! N8 O5 |# A3 p
2346048 PULSE ADHOC Importing or File New Block as a designer working on a design that has been shared does not work* s/ V. D1 R. {; W6 Z7 v3 I) g
2346643 PULSE ADHOC System Capture crashes when adding a part/ d0 f) K& R. F: C
2214054 PULSE UNIFIED_SEARC Unified Search does not honor operating system HTTP proxy settings! z7 z( ^5 U) u! f4 f, N( d' f
2325635 PULSE UNIFIED_SEARC Errors in Unified Search (vista) using customer database
: c* C$ b# |8 Y+ y" g1 S1 }2 X: J2326089 PULSE UNIFIED_SEARC Unified search does not show EDM parts and gives error (SPPSUN-1)) @& P# \% r5 r+ N1 H! H
2329750 PULSE VERSION_ON_SA Live BOM data disappearing from migrated DE-HDL design with variants
9 U6 Y e' A* M' J( o2319690 SIP_LAYOUT EDIT_ETCH Allegro SiP Layout XL - Auto-I Breakout Closest End excessive run time: Takes long time to complete0 ~! G' R% P- Q! L1 U
2320336 SIP_LAYOUT EDIT_ETCH Auto-Interactive Pin Swapping /Auto Breakout cannot route in design$ X; `2 Z* Y: T- }
2333679 SIP_LAYOUT INTERACTIVE Add Offset Via Angle Field
8 M2 Y a3 ?8 I- ` `5 s2344732 SYSTEM_CAPTURE DESIGN_CORRUP Page cannot be loaded because the design database is corrupt
6 _# H- I9 j/ P1 A8 u2342258 SYSTEM_CAPTURE MISCELLANEOUS System Capture is impacting PCB Editor GUI Readability by Setting QT_SCALE_FACTOR. [( i, e: u: X& y) F* r
2337610 SYSTEM_CAPTURE PART_MANAGER System Capture crashes when updating a part with changed PACK_TYPE and Symbol
" @% u, C7 R1 B& J+ E7 B. U( S2341550 SYSTEM_CAPTURE VERSION_ON_SA Projects migrated from HotFix 002 to HotFix 010 have slow peRFormance* Y& f) v) v0 G
2341591 SYSTEM_CAPTURE WIRING Moving wire segments still leaves odd pieces of wires$ B: U' m7 l6 y- c5 `& y9 Z
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发表于 2020-11-4 12:16
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发表于 2020-11-4 14:16
