EEPROM读写数据 25lc640 附程序

wangxia6112 · 发表于 2010-6-10 10:14

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本帖最后由 wangxia6112 于 2010-6-10 16:00 编辑

FPGA:XC3S100E
EEPROM:25LC640
PROM:XCF02S

我有个问题，想问有了这三块芯片，如何对EEPROM进行读写操作？

另外，采用的总线是PCI总线。

请高手指点指点。

以下是我自己的程序，读到的数据和写入的数据不一致，不知道是哪儿出问题了，麻烦各位帮忙看一下。

2 `: P* a8 q: h U: ?# k
7 U: A/ n; j3 @7 Q3 U# c

复制代码

module cpld(clk10m,rstn,sclk,mosi,miso,ecs,led,mosio,eecs,esclk);
input clk10m,rstn;
//input iow,ior;
input miso;
output sclk,mosi,ecs;
output [7:0]led;
output mosio,eecs,esclk;
reg [7:0]led;

wire clk4m;
reg [20:0]cnt;
always @(posedge clk10m or negedge rstn)
cnt<=(rstn==0)?0:cnt+1;

assign clk4m=cnt[20];
reg cs,sck;
reg [4:0]next_state;

parameter idle='d0,
ewen0='d1,ewen1='d2,ewen2='d3,ewen3='d4,ewen4='d5,ewen5='d6,//ewen6='d7,

write0='d11,write1='d12,write2='d13,write3='d14,//write4='d15,//write5='d16,

read0='d21,read1='d22,read2='d23,read3='d24,read4='d25,read5='d26,read6='d27,read7='d28;//,read8='d29,read9='d30;

//reg [4:0]cnt0;//write enable counter
//wire [7:0]wren;//write enable
//assign wren=8'b00000110;
reg [47:0]sq;
//wire [7:0]adr;
//wire [7:0]data;
reg [3:0]tmp0;
reg [4:0]tmp1;
reg [4:0]tmp2;
reg [4:0]tmp3;
//reg [1:0]tmp4;
always @(posedge clk4m or negedge rstn)
if(!rstn)
begin
  cs<=1;
  sck<=0;
  sq<='hz;
  led<=8'b0;
end
else
case(next_state)
idle:
  begin
cs<=1;
sck<=0;
//if((iow==0) && (ior==1))//
next_state<=ewen0;
//else if((ior==0) && (iow==1))//
//next_state<=read0;
  end

ewen0:
  begin
cs<=1;
sck<=0;
next_state<=ewen1;
  end
ewen1:
  begin
cs<=0;
sck<=0;
tmp0<='d8;
//tmp1<='d41;
sq[47:40]<=8'b00000110;//write enable
sq[39:32]<=8'b00000010;//write
sq[31:24]<=8'b00001111;//eeprom write address
sq[23:16]<=8'b01011100;//eeprom data
sq[15:8]<=8'b00000011;//read
sq[7:0]<=8'b00001111;//eeprom read address

next_state<=ewen2;
  end
ewen2://sck posedge ,wren signal=00000110
  begin
sck<=1;
tmp0<=tmp0-1;
next_state<=ewen3;
  end
ewen3:
  begin
sck<=0;
next_state<=(tmp0==0)?ewen5:ewen4;
  end
ewen4:
  begin
sck<=1;
sq<=sq<<1;
tmp0<=tmp0-1;
next_state<=ewen3;
  end
ewen5:
  begin
cs<=1;
sck<=0;
next_state<=write0;
  end
/*ewen6:
  begin
cs<=1;
sck<=0;
next_state<=write0;
  end*/

//write
write0:
  begin
cs<=1;
sck<=0;
tmp1<='d28;
next_state<=write1;
  end
write1:
  begin
cs<=0;
sck<=0;
tmp1<=tmp1-1;
next_state<=(tmp1==0)?write3:write2;
//next_state<=write2;
  end
write2:
  begin
sck<=1;
sq<=sq<<1;
//tmp1<=tmp1-1;
next_state<=write1;
  end
write3:
  begin
cs<=1;
sck<=0;
next_state<=read0;
  end
//end write

read0:
  begin
cs<=1;
sck<=0;
tmp2<='d20;
next_state<=read1;
  end
read1:
  begin
cs<=0;
sck<=0;
tmp2<=tmp2-1;
//sq<=sq<<1;
next_state<=(tmp2==0)?read3:read2;
  end
read2:
  begin
sck<=1;
//tmp2<=tmp2-1;
sq<=sq<<1;
next_state<=read1;
  end
/*read3:
  begin
sck<=0;
sq<=0;
tmp3<=14'd7;
next_state<=read4;
  end
read4:
  begin
sck<=1;
led<={led,miso};
tmp3<=tmp3-1;
next_state<=(tmp3==0)?read6:read5;
  end
read5:
  begin
sck<=0;
next_state<=read4;
  end
read6:
  begin
sck<=0;
tmp4<=2'b10;
next_state<=read7;
  end
read7:
  begin
sck<=1;
tmp4<=tmp4-1;
next_state<=(tmp4==0)?idle:read6;
  end*/
  read3:
begin
sck<=0;
tmp3<='d8;
next_state<=read4;
end
  read4:
begin
sck<=1;
//tmp3<=tmp3-1;
led<={led,miso};
next_state<=(tmp3==0)?read6:read5;
end
  read5:
begin
sck<=0;
tmp3<=tmp3-1;
next_state<=read4;
end
  read6:
begin
cs<=1;
sck<=0;
next_state<=idle;
end
default
  next_state<=idle;
endcase

assign mosi=sq[47];
assign sclk=sck;
//assign mosi=si;
assign ecs=cs;
assign mosio=sq[47];
assign eecs=cs;
assign esclk=sck;
endmodule