|
|
EDA365欢迎您登录！
您需要 登录 才可以下载或查看，没有帐号？注册
x
本帖最后由 T45524093 于 2010-4-29 09:17 编辑
- l# d- \1 m' J' g+ x& o d
9 v9 r' l1 K# ?http://downloads.nordcad.dk/Hotfix_SPB16.30.007_wint_1of1.exe
. `2 _ N5 n/ \
z/ y) P$ M& N. I0 i3 e+ S4 _6 B8 g
5 g# ]. O- u. F+ N, ^; ^" P# g/ q3 J$ `$ N! m) w% X: d* V' [' i
" R C) I) Q7 ]% @/ v
% w& [; d( ^& ^- f- d0 F7 ?7 @( V- x4 X
- {& j. @" ^, X3 CDATE: 04-23-2010 HOTFIX VERSION: 007
$ b% a4 ~" I% L8 b, j* e' u===================================================================================================================================7 C5 g2 m4 x. S; G( t
CCRID PRODUCT PRODUCTLEVEL2 TITLE: v, x9 v r9 \: v
===================================================================================================================================
+ |- B" N/ n1 `# u1 Y w7 z721859 allegro_EDITOR OTHER update shape to smooth creates tmp file on remote file server working dir why?3 t# O- ?& P' H Y" q, r/ ~" Y
740201 SPECCTRA_MENT_ IMPORT Wrong stackup order after translating from mbs2sp
: D' A# I1 X" g; o3 I# ~# e744797 SIP_LAYOUT OTHER Cannot Copy a connector (IO) symbol in APD and SiP tools
. M% D4 g5 q* @ B$ f747831 CIS CONFIGURATION There is a delay of 5 to 10 mins in opening SQL database in V16.2 and V16.3. It is fine in V16.0.% ?6 c, t8 l- [5 j
747848 CIS CONFIGURATION Unable to configure CIS with Oracle database due to Capture crash.
5 E5 z, F n9 a6 z& h5 G751372 CAPTURE OTHER Copy / Paste Issue in capture 16.3
" D2 f4 q8 @( w5 @! i; g( D757434 ALLEGRO_EDITOR MODULES Allegro hangs the board file after creating Placement Replicate circuit.1 v. a# J) g1 ]% l& x
759906 CIS PART_MANAGER Property copy from one to several parts doesn't work
# B9 a/ j- S9 q760154 Pspice NETLISTER Model parameter (Tj) is not affecting Smoke Analysis result/ G: \& S3 K2 S! o; ^) r' `/ g: R R1 m
761177 CIS OTHER Error Message - Memory exhausted3 z1 j+ k. S& r6 W, |: y
762602 CIS EXPLORE_DATABASE CIS doesn't open datasheet for parts if it is not stored at default Capture location.
I' i8 Y- H5 h% }7 A; [763677 APD EDIT_ETCH The "Via to Via Line Fattening" tool is inconsistent in which clines are changed.+ W6 }+ h. Y. J, F* ^; o+ B
763715 CAPTURE NETLIST_OTHER A long pin name gets truncated upto 31 characters when the wirelist is created.
# `7 o U4 e* }6 t) B/ o- C763878 CONSTRAINT_MGR DATABASE Why Pinpairs disappear after closing Constraint Manager?" z: P: k! f/ E2 T+ ^" s6 e! E0 y
764020 CAPTURE NETLISTS Usernetl.dll has changed between 16.2 and 16.3
7 s+ e' b, w5 ]764101 APD EDIT_ETCH Perpendicular routing through a Region does not work when the region segment is drawn at an angle.: K* z1 @, h# x. t$ y& K) Q
764200 ALLEGRO_EDITOR DRC_CONSTR Via at smd fit drc on a via that is placed fully inside the padstack having custom pad
6 O( Q; Z3 p4 a/ \2 u& Z764903 PSPICE ENVIRONMENT 'Run in Resume Mode' does not work in SPB 16.3
& Z' h! Q$ `& d" r! j765206 F2B PACKAGERXL Unable to feedback subsequent pin swaps from Allegro
! _' e2 i8 I+ E5 X8 e765319 APD DRC_CONSTRAINTS Identical Constraints in PeRFormance Advisor question
) L$ @6 `" n% d1 `" ^5 E765541 SIP_LAYOUT SHAPE Set via oversize value to 3 in dynamic shape instance parameters will make overlap shape.6 C5 e, M1 Y% U$ }6 X! @! x. V
766147 APD EDIT_ETCH Resize/Respace Diff Pairs does not work on 45 and off angle, D+ M2 x5 h8 D/ a
766337 SIG_INTEGRITY GEOMETRY_EXTRACT Geometry of Via model Extracted from board file is not identical to Original Via geometry design B! l7 ], B/ ]) a' T, d: I
766443 ALLEGRO_EDITOR PADS_IN unable to translate PADS ascii to brd in 16.3
* e3 [- R; N" L' W766581 CIS CONFIGURATION In 16.3 capture.exe remains memory-resident after exit" M* O; p% ?6 q$ E7 V
767161 ALLEGRO_EDITOR SHAPE The behavior of Add Fillet command is different by Hotfix version.
& k+ ~1 T3 B1 I) p! E767217 SIP_LAYOUT IMPORT_DATA The Die-Text In wizard and it is crashing on the "Finish" step.: I; \1 @& P4 q1 ], w; a/ m- [
767598 SIP_LAYOUT WIREBOND Can't wirebond SIP designs as it just hangs.
% Q! a8 i1 L0 a7 T# N* Q, \9 {8 R767832 ALLEGRO_EDITOR DRC_CONSTR Reducing Design Accuracy updates Physical Diffpair constraints wrongly
+ R i$ o% B5 ]1 }$ _; r/ N768822 ALLEGRO_EDITOR skill axlSetParam return value is divided by 10 to the power of the design accuracy.# O! _- [4 C' }( H/ j& B7 h/ X2 E
769150 CIS PART_MANAGER Update All part Status on a group changes 揇o Not Stuff? status to 揝tuffed? in V61.3_ISR_5. |
|
[复制链接]
/1 
发表于 2010-4-29 09:15
收藏
淘帖
支持！
反对！