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我做的是出租车计费系统,VHDL语言做的,也就是从网上下载的。请问一下下面的程序中SE模块和DI模块是干什么用的啊?拜托帮忙,快答辩了!3.3.1 p8 p; P( H: Z& `; s# k
模块3 b/ W" ?/ L5 E* M, ~6 c5 e g
JIFEI( Q, A( o; `" _+ J% W
的实现! l8 D5 a- i9 }) x7 ~
该模块是模拟汽车启动,停止,暂停加速。模块如图4: CLKSTART
/ h. z4 ?2 P' V/ Q5 }CHEFEI[12...0]STOP
/ v, Y' F9 F y7 b; R5 o& eLUC[12...0]PAUSEJS1 q3 {& U9 f7 d6 a% }3 S; z( q% K
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! O, v6 b2 Z) V( |/ @% o$ T" L图 4
; ], O9 M/ e, b4 zJIFEI模 块 输入端口/ x# L6 _8 g3 k2 |1 f8 E. u
START、STOP、PAUSE、JS
. X& x: C6 k, U* I, N! |分别为汽车起动、停止、暂停、加速按键。程序如下: library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; entity jifei is port (clk,start,stop,pause,js:in std_logic; chefei,luc ut integer range 0 to 8000); end jifei; architecture rtl of jifei is begin process(clk,start,stop,pause,js) variable a,b:std_logic; variable aa:integer range 0 to 100; variable chf,lc:integer range 0 to 8000; variable num:integer range 0 to 9; begin if(clk'event and clk='1')then if(stop='0')then chf:=0; num:=0; b:='1'; aa:=0; lc:=0; elsif(start='0')then b:='0'; chf:=700; lc:=0; elsif(start='1' and js='1'and pause='1')then if(b='0')then num:=num+1; end if; if(num=9)then lc:=lc+5; num:=0; aa:=aa+5; end if; elsif(start='1'and js='0'and pause='1')then lc:=lc+1; aa:=aa+1; end if; if(aa>=100)then a:='1'; aa:=0; else a:='0'; end if; if(lc<300)then null; elsif(chf<2000 and a='1')then chf:=chf+220; elsif(chf>=2000 and a='1')then chf:=chf+330; end if; end if; chefei<=chf; luc<=lc; end process; end rtl; 3.3.27 p& ^0 Q% ^. E/ A: |- j
模块2 B& t5 G1 V* x4 N1 [
X
6 } G6 _7 R+ o* T3 K: h3 Q: o的实现* h; d& d7 f+ m$ e' w$ B2 T: ~
模块X见图5。该模块把车费和路程转化为4位十进制数,daclk的频率要比 clk快得多。 AGE[3...0] ASH[3...0]DACLK( m8 g; K7 W- }" v: K) Y$ @
ABAI[3...0]ASCORE. h' w8 Q( t9 B) A
AQIAN[3...0]BSCORE
2 t# @% ]) }( {+ i; p2 PBGE[3...0BSHI[3...0]BBAI[3...0]BQIAN[3...0], f9 J z# r+ u* ~
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% F' z- m1 i7 J l* y图5 X模块 该模块的程序如下: library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; entity x is port(daclk:in std_logic; ascore,bscore:in integer range 0 to 8000; age,ashi,abai,aqian,bge,bshi,bbai,bqian ut std_logic_vector(3 downto 0)); end x ; architecture rtl of x is begin process(daclk,ascore) variable comb1:integer range 0 to 8000; variable comb1a,comb1b,comb1c,comb1d:std_logic_vector(3 downto 0); begin if(daclk'event and daclk='1')then if(comb1<ascore)then if(comb1a=9 and comb1b=9 and comb1c=9)then comb1a:="0000"; comb1b:="0000"; comb1c:="0000"; comb1d:=comb1d+1; comb1:=comb1+1; elsif(comb1a=9 and comb1b=9)then comb1a:="0000"; comb1b:="0000"; comb1:=comb1+1; comb1c:=comb1c+1; elsif(comb1a=9)then comb1a:="0000"; comb1b:= comb1b+1; comb1:= comb1+1; else comb1a:= comb1a+1; comb1:= comb1+1; end if; else ashi<= comb1b; age<= comb1a; abai<= comb1c; aqian<= comb1d; comb1:=0; comb1a:="0000"; comb1b:="0000"; comb1c:="0000"; comb1d:="0000"; end if; end if; end process; process(daclk,bscore) variable comb2:integer range 0 to 8000; variable comb2a,comb2b, comb2c,comb2d:std_logic_vector(3 downto 0); begin if(daclk'event and daclk='1')then if(comb2<bscore)then if(comb2a=9 and comb2b=9 and comb2c=9)then comb2a:="0000"; comb2b:="0000"; comb2c:="0000"; comb2d:=comb2d+1; comb2:=comb2+1; elsif(comb2a=9 and comb2b=9)then comb2a:="0000"; comb2b:="0000"; comb2:= comb2+1; comb2c:= comb2c+1; elsif(comb2a=9)then comb2a:="0000"; comb2b:=comb2b+1; comb2:=comb2+1; else comb2a:= comb2a+1; comb2:= comb2+1; end if; else bshi<=comb2b; bge<=comb2a; bbai<=comb2c; bqian<=comb2d; comb2:=0; comb2a:="0000"; comb2b:="0000"; comb2c:="0000"; comb2d:="0000"; end if; end if; end process; end rtl; 3.3.3
* F5 ~( w8 y' I5 m l+ H$ G模块% f j7 S0 W( N" o6 W: Q
XXX1% F* w5 F6 e# q* ]$ ^
实现+ B k+ m1 c+ D* N4 |
模块XXX1见图6。经过该八进制模块将车费和路程显示出来。该设计采用的是共阴极七段数码管,根据16进制和七段显示段码表对应关系,用VHDL的CASE语句可方便的实现他们的译码。 动态扫描时利用人眼的视觉暂留原理,只要扫描频率不小于34HZ,人眼就感觉不到显示器的闪烁。本系统24HZ的扫描脉冲由相对应的外围电路提供。动态扫描电路设计的关键在于位选信号要与显示的数据在时序上一一对应,因此电路中必须提供同步脉冲信号。 C[2...0]A1[3...0]A2[3...0] A3[3...0]! K* A8 T, F1 b( u
! s0 B/ j1 v% a8 h% G7 e9 o/ n- EDPA4[3...0]B1[3...0]
# i8 ]/ E5 Z" y2 g7 V x
! b) @! w/ j, q6 ?, k. L* m' SD[3...0]B2[3...0]B3[3...0]B4[3...0]$ h* }9 k& B: @6 T8 Q/ N4 J
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图 6 模块XXX1 这里采用八位计数器提供同步脉冲,VHDL语言如下: library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; entity XXX1 is port(c:in std_logic_vector(2 downto 0); dp ut std_logic; a1,a2,a3,a4,b1,b2,b3,b4:in std_logic_vector(3 downto 0); d:out std_logic_vector(3 downto 0)); end XXX1; architecture rtl of xxx1 is begin process(c,a1,a2,a3,a4,b1,b2,b3,b4) variable comb:std_logic_vector(2 downto 0); begin comb:=c; case comb is when”000”=>d<=a1; dp<=’0’; when”001”=>d<=a2; dp<=’0’; when”010”=>d<=a3; dp<=’1’; when”011”=>d<=a4; dp<=’0’ ;, U9 P$ A, H) b" S( i3 m
when”100”=>d<=b1; dp<=’0’; when”101”=>d<=b2; dp<=’0’;
. m/ C5 T- y6 \2 L8 o7 Zwhen”110”=>d<=b3;
dp<=’1’; when”111”=>d<=b4; dp<=’0’; when
" U% e5 [* d0 t) o+ J: q. B! Tothers=>null; end z4 t0 | q9 q# ~, @
case; end3 a. z5 x/ h* I. @, _# Y* K+ v8 P& x1 m
process; end; [) ^1 j' O& s+ r, T6 t
rtl; 3.3.4
, g7 H& y, ?5 M& I! {! `( j( J模块& R" S- `& P3 \
SE# ]: p6 w X0 h9 c
的实现: {7 Q2 L( P7 P4 W$ b, u6 y' N
模块3 t- c: T7 B( J, T
SE
$ {$ p1 o9 |; T0 O" e见图" Z- Z/ s# P- Z- a
7:该模块是系统检测模块。 CLK1 ]9 I# u, H4 X$ z/ e
( P2 Q% ~6 _* a+ k/ ^4 k5 \A[2...0]5 {) }0 {# p- ^: o' a! c7 z* a
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7 J9 o& E) w: _: \- i图' t- J; H6 p# D! A
7 * r2 y3 u7 p4 q: l, N
SE模
* z1 u1 S" z( H1 t2 ?块 模块SE程序如下: library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; entity se is port(clk:in std_logic; a:out std_logic_vector(2 downto 0)); end se; architecture rtl of se is begin process(clk) variable b:std_logic_vector(2 downto 0); begin if(clk’event and clk=’1’)then if(b=”111”)then b:=”000”; else b:=b+1; end if; end if; a<=b; end process; end rtl; 3.3.5- k0 u4 q. x5 ?" |* V6 k
模块$ M( s6 L& O, Y4 K" a9 ]/ O9 O
DI
5 L8 y- ]$ X6 F的实现' y, }' N6 V" w; {; M8 c7 G# i
模块DI见图 8 D[3..0]
) t k8 Y5 p- N! E7 e5 ?
: z3 W3 }! C9 T4 [3 [Q[6..0]
" t' |) N1 s# {: h/ Y |
) X) \, @/ D. H
; k. ^: i, k; a# C) f& f$ k$ N; U$ [
5 [" n/ _% w% K$ o/ x) g
# h1 }/ V1 V' s, T图8 DI模块
模块DI的程序如下3 q* l1 U3 n, @0 ], C
library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; entity di is port(d:in std_logic_vector(3 downto 0); q:out std_logic_vector(6 downto 0)); end di; architecture
& u u$ {2 _+ h: q- K7 D q& krtl of di is begin process(d) begin case d is when”0000”=>q<=”0111111”; when”0001”=>q<=”0000110”; when”0010”=>q<=”1011011”; when”0011”=>q<=”1001111”; when”0100”=>q<=”1100110”; when”0101”=>q<=”1101101”; when”0110”=>q<=”1111101”; when”0111”=>q<=”0100111”; when”1000”=>q<=”1101111”; when others=>q<=”1101111”; end case; end process; end rtl; |