POWERSI仿真的时候报错 XX is outside of the plane XX

w8832095

POWER SI仿真的时候报错，大佬帮忙看看，哪里出了问题

"Via1302::VREG_S1A_0P8" on layer "Signal$Inner_Layer7" is outside of the plane "Polygon324774::GND".
"Via1313::VREG_S1A_0P8" on layer "Signal$Inner_Layer7" is outside of the plane "Polygon324774::GND".
"Via1316::VREG_S1A_0P8" on layer "Signal$Inner_Layer7" is outside of the plane "Polygon324774::GND".
3 ]1 w+ r2 M1 z! Y5 e8 J5 M4 K
"Via1317::VREG_S1A_0P8" on layer "Signal$Inner_Layer7" is outside of the plane "Polygon324774::GND".
"Via1320::VREG_S1A_0P8" on layer "Signal$Inner_Layer7" is outside of the plane "Polygon324774::GND".
8 N( p6 A* N$ q1 Q: k( n "Via1321::VREG_S1A_0P8" on layer "Signal$Inner_Layer7" is outside of the plane "Polygon324774::GND".
"Via1347::VREG_S1A_0P8" on layer "Signal$Inner_Layer7" is outside of the plane "Polygon324774::GND".
"Via1348::VREG_S1A_0P8" on layer "Signal$Inner_Layer7" is outside of the plane "Polygon324774::GND".
"Via1354::VREG_S1A_0P8" on layer "Signal$Inner_Layer7" is outside of the plane "Polygon324774::GND".
% a3 ]+ O; l* M- o* e' Q2 ~' h7 I "Via1355::VREG_S1A_0P8" on layer "Signal$Inner_Layer7" is outside of the plane "Polygon324774::GND".
"Via1421::VDD_EBI_IO" on layer "Signal$Inner_Layer7" is outside of the plane "Polygon324774::GND".
"Via1479::VDD_EBI_IO" on layer "Signal$Inner_Layer7" is outside of the plane "Polygon324774::GND".
"Via1481::VDD_EBI_IO" on layer "Signal$Inner_Layer7" is outside of the plane "Polygon324774::GND".

道法自然

帮你顶一下

w8832095

不同层，貌似孔的大小不一致，导致短路啊，这个孔径怎么去设置呢

xieda2005

不是告诉你那个过孔了嘛，用里面的查找功能，查找孔，比如报错里面的，Via1302，看看啥问题，