CADENCE SPB RELEASE 16.3 README -- UNIX Version 已经RELEASE,期待windows 版本

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$ R* i& M$ M6 N' t6 \4 gcadence SPB RELEASE 16.3 README -- UNIX Version

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INSTALLATION GUIDE
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; j. h: ~0 b; u' OYou can find the UNIX installation guide on Cadence Online Support or the
Cadence downloads site.


MIGRATION INFORMATION
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Important migration information is contained in the "Migration
& ]% ^% Y. I2 i' y" z; `" k8 \Guide for allegro Platform Products Release 16.3", which is
3 g$ r" v' B: bavailable when you install this software or on Cadence Online Support.


3 x1 y  q7 d' u# \1 g) v- x# P; m1 USYSTEM REQUIREMENTS
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# [+ W! Y/ l8 \----------------------

Information about minimum and recommended system requirements can be
4 S2 _0 w# U$ B- {* |; K, Cfound in the "Allegro Platform System Requirements" document in the
+ {$ g7 d  B: Z, \Cadence product documentation or on Cadence Online Support.
% ~3 D! v! g7 `/ [/ B! {* S
, N( d* g+ m3 `* T) h- Q
; q6 G* c! j1 s8 S3 x' w  ]WHAT'S NEW
----------
7 x. S& D" r3 ]4 l# A$ |Product release notes are available at:
[url=http://support.cadence.com/wps/mypoc/cos?uri=deeplinkminocumentViewer]http://support.cadence.com/wps/mypoc/cos?uri=deeplinkminocumentViewer[/url];
src=pubs;q=landing/spb163/prodList.html

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+ j) Y8 {( @$ F6 SKPNS
----
The Known Problems and Solutions (KPNS) document is located at:
& e( y3 T6 N: B& s/ ~[url=http://support.cadence.com/wps/mypoc/cos?uri=deeplinkminocumentViewer]http://support.cadence.com/wps/mypoc/cos?uri=deeplinkmin:DocumentViewer[/url];
src=pubs;q=landing/spb163/kpnsList.html
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Allegro /SigXplorer ABIML LIBRARIES FOR DEFAULT TRACE MODELS
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, b( e  D1 O  W% J--------------------------------------------------------------
2 I$ f  I) f" u5 |6 u. WThe Allegro /SigXplorer ABIML Library is a free library that includes ABIML
libraries for SigXplorer default trace models with suRFace roughness effect.
3 C* R! Q5 g, i( K) x2 `6 U. aIt is designed to provide accurate trace models in Allegro /SigXplorer without
: l: M: @0 ]4 r! Xtime consuming EMS2D solver runs. The libraries can be found at:
% u" r- C) F7 \1 y" y% Qhttp://www.cadence.com/products/pcb/pages/Downloads.aspx

* M1 W! a$ S2 H* T3 m& NThis ABIML library is provided free of charge for use with Allegro and SigXplorer.
The library is provided as a zipped archive, with installation instructions included.

CUSTOM ENVIRONMENTS
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Customers using custom batch files or scripts to set up their environments must add
the following to their path. There is the potential that some Allegro products may not
! V( Q. p; W8 h+ Ulaunch without this setting.
6 `2 X& l# z0 ^& a1 y  K. S%CDSROOT%\OpenAccess\bin\win32\opt
3 o2 S) C- O  |4 H. j
% R3 z9 I; |4 a5 Z& q  @/ ]
' C/ n6 L: l- l- f! t1 e
" X5 K8 T* G- g* y2 ^8 R9 e' y
List of Fixed CCRs
-------------------
-------------------
8 W5 F. }* S% U, D* `, }! Y

1 h! [% @$ e; p3 l4 [* Y* nENHANCEMENT CCRs
8 B. V' z# |9 Y0 T2 w  e----------------

# `1 F. G/ s. z" x  \CCR Description
6 F( o3 Y0 A8 a( k6 ]4 N----- -----------
, h, [# C% V" I- Y( B----- -----------

7419 Customer menu options added to Allegro menus
+ Z9 s! k; T- v- h1 }9 D+ D8230 Use via in area constraint does not work
+ Z) l/ Z% ^# J6 }10658 Modify default formatting for Label texts and linewidths
12216 Cannot set color or line width for wires on net-by net basis
! J# G3 W9 x  o& O, V, ?13083 flip/mirror design to back side
) ]; \, C7 s) E4 y' E# x4 d7 J13373 Select length of pin graphics
0 r1 h  p. D$ W! X- }: z# [18072 Add docking option for probe cursor box.
# x( h& }$ N; {% Z# a6 ~! r5 k; t21451 Change Probe print trace color yellow to alternate.
9 L  \  O2 {7 H+ a32798 pxllite complex hierarchy netname enhancement
39600 Option to see time spent on allegro database
, G6 _0 z& }2 g: u60427 Add different subclasses for pin_number top and bottom
132769 Footprint viewer in CIS should also show pad spacing info
) [8 d0 Y/ D6 r5 R* R( @6 _% N158838 Need easy way to delete marker
0 ]% U8 o8 E+ S8 i) Q; j159977 need attribute mapping capability in mbs2lib and mbs2brd
" @" m8 m1 d; ^8 _% `164790 Improve autorouting quality on diff pair w/match length rule
205909 Constraint Manager displays in Allegro no graphic mode
: }& D+ M; v: @210027 Delete dynamic shape removes net name from copied vias
222127 pads_IN: Constraints are not imported with the design.
( \3 i: V& E: d236698 Report Unused parts in multiple parts package should be DRC
245193 export dxf height information when blocks are unchecked
8 Q# C% v9 {" i254183 Multithreading for DRC and CM analysis in Allegro
" H# B7 j# K7 i% G282027 Problem with Split Part and part graphics
282507 request to import IBIS file directly
283698 place by schematic page number window need enhancement
7 Z" F, E; ]. l: x. ?% e. B288540 Schematic page# display order request for Quick place
1 }% ^2 s! ?- v9 v290641 Option to copy paste cursor value
298081 Models from Funtion.olb need more explanation
323813 Need negation and exclusion function in ADE reports
' q* V  \# N2 I! f; o, h6 M5 A341484 Wirebond: Tools to generate wirebond manufacturing outputs
6 f: q$ Q$ u2 [9 e- L* ?2 j5 g353212 Variant Name is not coming in Standard BOM
1 Q4 ^* ~) L% v3 }  H9 `# D360602 Enhancement to Show element on a via
362934 Enhancement for Allegro to utilize Dual Processors.
364850 change the font properties of Label Text
367468 Need a real DML_PATH environment variable
% g$ G+ E7 W; q6 S380714 Ability to have Power pin set to Not Connect
2 N. ]. N8 f, G$ N  L* l" N8 c) q382860 Display parts and nets in different colors
384488 Add DEVICE and REFDES filter to Signal Model Browser
391487 Ability to have user defined directory for storing distribution files for MC analysis
420008 The renamed differential pair names are different in CM of conceptHDL and CM of Allegro.
420023 It should be possible to Delete a differential pair defined by SIGNAL_MODEL (.dml) on CM.
6 S% [& I: F9 W, y& a; ?420648 Need to get RF Elements to retain previously entered values
429280 ARC is unable to load/save rules - submitted for tracking with Medtronic SiP benchmark
430549 GUI for ADRC XML Rule files
430558 Store last used ADRC rule check ini and check values in .sip database
452606 Can we have last plot as a default
( D' l! e0 K- w+ I; k; ^  \6 w3 l; s( v454452 Allow neighboring/overlapping die pads on same net to go to same finger during wirebond add.
464056 Setup option to always prompt to baseline a new part
  s/ k' p/ M5 C/ ~* B3 Z, _$ r469378 Enhancement : Hide/Unhide feature for trace
475077 Schematic Generation Setup form is missing the Port symbol selection.  It was there in the 15.7 release.
475714 User Guide should mention that Temp Sweep is not honored in AA Flow?
4 ~) K: |8 C' v6 a$ q480843 Requesting ability to View > Zoom Mirror current view.
484632 Request for Bond finger to snap to Guide in Free placement of Bond pads
1 Z9 V. ?6 E! Q& s2 r+ V490948 Provide a sketch line and text property form
  c' U- m8 I( O3 f, Q/ T) x# S1 \0 |- }500550 CRef's should be preserved with the next run of the schgen in the preserve mode.
* ]8 U7 Q- c( M. a- c505284 Enhance The ConceptHDL can set the color for $XR0 property.
512748 improving arc routing
513967 staggered C-line via arrays
515333 Option to specify spacing between Components in the Generated Schematic
525748 Why is MC Analysis Sigma value 1/3rd of 15.7 version value?
526818 Retain Hard Packaging Information option does not work for SECs.
528391 SigXplorer measurement is wrong
# }+ N5 t* A+ D- i" O533844 Allegro password not encrypted in the .brd file.
6 k; B9 m, M$ P* q3 ]+ {" @( F536681 In the ADRC tool requesting a "Layer" option for Conductor to Package Substrate Edge Spacing
536948 Allow  sorting of power symbols
539407 In ADRC Minimum Shape Check requesting individual "Layer" option
541145 slide command does not support to keeping the existing arc
541214 about supporting OpenDrain Model in Quad2signoise
542414 A function to force diff pair spacing to primary gap.
8 \/ D# h" V4 h+ T6 l! b/ d: r2 n- J542803 A "Minimum Shape Check Soldermask" entry is needed in ADRC
543470 Provide rectangle and line width thickness for Drill legend in NC drill Param
543766 Crefer fails to annotate occurrence properties to offpage symbols in replicated blocks
, K) H3 v: }+ m( v) l) f545408 Cursors are toggled off when deleting a plot
5 i; f. W- T% e546891 Enhancement: message improvement when expand design action in Concept
& B: V7 q( S* `5 Y  O7 H546985 XOR function to allow to compare layers within different or same designs
548920 Add a document of which properties can be synced and which cannot be and the files required
5 g  s: f$ q4 _+ e/ F) U553669 Add a 3D viewer to Allegro
& l( w! \$ S& `+ ]$ h+ I) b1 V555183 Wire Bond Report --- Report field should have save function for reuse
556200 Need listing of DE HDL command names and switches.
3 i7 c9 G( I  v2 {556883 Grid point for Origin to be highlighted
559638 Enhancement for importing height from PADS in allegro
! |$ s0 |+ Z( ^! N/ T( z559724 Request cline via arrays to be applied to diffpair nets
, ^9 o, i# D4 P' B9 F560134 Show Element Customized Display
, a& C' \4 s: S$ V/ Z; B6 |563957 Enhance Color Dialog form Class/Subclass section to expand vertically when the form size increases.
568058 Request to have component information available through the context menus
569615 Enhancement to import constraints from mentor Board Station to Allegro PCB
569680 BOMHDL defaults to the wrong file type when html report type is selected
9 ?5 \& Z- `6 g0 L; l6 R569784 Request ability to assign netname to via during copy
: W, H& g# A* u- E: y9 W6 ~" O7 c569863 User would like to set a larger default trace width
570128 Enhancement : Packager setup for subdesign drop down
6 L+ U& |0 m& q; T/ b570195 SiP - Provide option to create/combine BF labeling with additional text required for Bond diagrams
: ]% `! W  J+ F' R# }' N570861 Unconnected mark does not be removed even after wire is connected to the pin.
/ Z, f9 e) T8 o; c; r+ j. N575211 Web links in CIS explorer are not working when Firefox 3 as a default Browser
4 S. I7 U& ^: J4 \! c577944 Enhancement request to have the drill legend for thru holes and slots to be separated without being on top of each other
583630 Can Multiple Section pop up box be disabled?
! k* ]% s! a0 {583712 Ability to have string values for SCHEMATIC_GROUP property
585904 Find a schematic page with help of nets
589512 RF component snap is 'too clever'
590246 CIS to Allegro flow to include or ignore constraints same as HDL to Allegro
591306 Suppress RF edit window when changing RF Element properties
591318 Use RF setup values or retain changed values in RF Element forms
591443 Temporary highlighting is lost when using the Copy command
591450 Provide a dynamic tapering option to RF PCB Route
& |3 V: j8 l4 r/ ~2 L/ ]3 t6 [: M591489 Would like to suppress RF Snap windowing around the user pick automatically
! e3 M+ l( [$ a, X1 c3 L# @591812 Provide move options for the RF Snap command
- s5 K/ ~8 |/ ]. T591817 Provide easy group and element ID in repackage form
591825 Quickplace for RF Elements
! b8 t; ]4 m2 m591865 Request for more information on 'Other' Netlist formats
596392 Publish PDF needs improved error messages for missing installation.
3 ^  h! s0 D& [+ E: z& G* v, J. q+ g596555 Request alias symbols documentation to include and clarify when necessary to rotate 180 degrees
3 d8 V& A& U. k7 b. G. R596843 Cannot do global search after importing read-only schematic block
597808 Option to increase the default thickness of all traces in Probe
599499 Plotting from within Allegro does not find path to stipple file
7 W2 c" Y. _; C- Y: T$ _) M604125 Manufacture>Create Bond finger Soldermask.
) b7 {# B  m5 P+ O$ _605023 Need rats by layer function for Free Viewer
$ @2 i1 D+ J( R) K' N$ S, T, U605112 Dies should not be counted as conductor layers in Design Summary Report of SiP
8 k& a( _, }" S; q/ ^* A605373 importing and Exporting BondWires
9 v" g# k! X; ^2 b' P609035 Voltage_bus part - Make pin number invisible
7 Q8 @* j3 T6 `2 |. ~2 `609561 Enhance Circuit Replicate to support coppers shapes connect lines and vias
610934 Retain user input values in RF PCB forms
2 Y1 q- ?! x6 T1 ~) @612008 Mirror Rules need to be documented for axlTransformObject.
613639 Update Documentation for "split_inst_name" property.
614345 Email facility for Design partition on Solaris does not work
615139 option DMFACTOR  documentation missing in pspcref.pdf
- S# E, N- [% C615374 Retain Soldermask Thickness value in 3D Viewer Options
9 a0 l2 T' F4 {615850 Auto Setup should honor device setup parameters if component value is null
615988 PDV WHen importing from Mentor does the browser not remember the last location of import
616529 15.7 Design Entry HDL fails with Out of Memory message
616873 Uppercase characters in design name error should be improved
617976 Enhancement for a way to sort user subclass in define subclass form
620289 Server 2003 support information in pcbsystemreqs.pdf
7 Z# e6 x# y; Y% y620303 Enhancement: Shortcut key for "Select Entire Net"
( C) x7 ~% M5 K+ w- q. c3 F621054 Renamed net in netlist isolates components from the rest of the net.
" X; ~' Z0 T9 w1 e1 ?+ B621955 Offset Via Generator utility should show a warning message if vias are already present.
: F# u/ Y0 Y# M8 P622203 Requesting that "DFA Constraint Spreadsheet" icon be added in Customization >Toolbar commands
623218 display pin names associated with a net in net Properties
+ \7 x+ M: n# o1 ]; k623908 Mirror Symbols while dynamically moving enhancement
624817 Display padstack name in data tips when hovering over Pad-stack
* y1 C7 v' w' I) g+ Q625733 In Netlist Report they are requesting square bracket vs angle bracket
626605 Extract topology with routed interconnect to include via's in Allegro DesignPlanner, PCB XL and PCB GXL
626673 16.2 Die Stack Editor - Add option for DIE x y cords within DIE STACK form - shows rotation and allows move but
629008 enhancements for find command
: l( h2 b; |5 O. \8 u5 z8 G8 g, w5 \629548 Request an Option in Create Plating Bar where it may be directed to a different Subclass
. d2 w5 Q! I  E, W. W$ L' x630949 DRC for bond wire to bond wire requires additional parameter "wire profile" to "wire profile"
0 p/ y; F: L' S  O630955 SCM does not see design difference after update of fixed die/BGA in cdnsip
4 w# H8 J, x- `3 Q( P630973 SCM should see the net assignment made in CDNSIP for Power and Ground pins
631609 Clarify how to generate a cref.dat file in Cadence Help
631697 Want to degass many shapes in succession with custom parameters
+ x0 ]) Q) c, g6 d( C632754 pspPN and lib_list should reflect location of new models in 16.2
6 n' s$ R6 |# e633440 Sensitivity not varying components correctly
7 s( \3 n2 o7 `& R2 {633842 Add note to docs regarding padstack quickview
' w  r; @' i; V! N) \634350 Enhancement suggestions for pop up info boxes.
634877 Export netlist with properties changes scope from global to local
8 u: [; g3 @- X9 I1 I; _5 o635118 skill variable to obtain list of Classes and user defined subclasses in a database
# S7 b- k" {/ k6 ?2 G* x7 C635233 Place hierarchical pin tool tip
635543 Any command to get the current line/lock type information?
635579 Enhancement for Structured format in parameter file
7 C( ~4 B1 Y3 p3 q% @. |' w' s636930 Die Export option to create symbol either from schematic or layout
637195 Allow for SKill access to backdrill info on padstacks
6 q/ [- O- Z% i8 r637768 Enhancement to assign different colors to different net based on a unique property
( E' q( O/ N" B, U0 I+ A4 u! G638455 Enhancement: Add some details regarding nomd.lib
1 y$ q2 A, D, u* m" }638581 ENH - Press ESC button Spreadsheet window disappear
# L3 P5 x' }4 ]! N. H638622 Add note to CM Spacing Domain Region worksheets regarding shape2element clearance
638910 Enhancement to sort the list of available vias alphabetically in the via list ?
639630 Does the Net_Short property work with Modules?
640262 Request object membership count in the status line and forms of CM.
640280 Provide resizable windows in CM and other apps
640668 File>Change Editor needs ability to go from GXL to Performance L or Design L.
642095 Ability to disable the Pop-Up description of elements
642298 ENH: For license checkout detailed message
642422 After Copy parameters from one part to other in partmanager forgets previously highlighted line
642865 Allow format of hyperlinks in ptf files
642894 ERROR(SPCOCN-1993) is not documented anywhere in Cadence Help
2 X* v# _- k) G% ]643381 Add an option to ts2dml to allow user specified port ordering.
643390 Request for a switch or button that would allow Properties to be maintained during a shape merge
( I) M* P9 P6 q  ~  e1 F% P! y643625 Bond Wire export to DXF does not support WYSWYG
643790 Include Associated Components in the Verilog netlist
644216 Store Filter Row Data and Units Of Measurement in site-specific file.
) z1 i( v1 b! y; \9 g$ R! h644248 Need a better solution to identify and handle unstuffed components
644350 Incorrect upper/lower case for axlPadstackToDisk in Allegro SKILL reference manual
646662 Enhancement to add feature to toggle on/off inter communication tool from within PCB Editor when using DE CIS.
: X! Q+ e9 W2 w1 p, ?646981 about the treatment of NO_GLOSS property in Missing Fillets Report
647480 global setting for adrc settings in sip via techfile
647617 Degassing not suppressing shapes less than size specified
648210 Request for Working Layer (WL) model in all tier Allegro tools..
* O0 t% Q0 j, v# }, B648218 must delete keyword "multiwire" from Doc
648533 The cross probe highlighting between DEHDL and Allegro PCB Editor is not documented
648801 Stream Out issue for SPACER
648930 If two PPT option set names match a given component which one will be used?
649603 about spara import
9 Q& {6 ~  x- Q1 k( k- q0 n$ H649607 Management of SiP Technology File and Project Information
1 e7 K& B$ p% u% m7 k6 j649610 Management of Part Table (PTF) Files
649613 Management of Library Lists
2 d9 q5 T  W" Q652335 Tooltips clutter Place Part dialog.Option to switch it OF and ON
+ ]. v; p7 Q3 `; _9 {0 T  J652511 Unplace Component command
$ f7 n2 t! h/ P& a; p652554 Enhancement request for Allegro to check the vias used to the allowable vias defined in constraint manager
652939 Is there a way to predefine the values for Sample Start Height and Sample Start Length in Wire Profile Editor?
1 N8 Q( y: A9 C3 }& C653027 Explicit RMB "Done" option is required in Part Developer symbol editor when editing text
) m: z9 O; D  e& h653359 Setting the $PN to # does not set the pin numbers to invisible when part is sectioned using the section command
5 N$ u' b( N) G0 t+ N3 q/ I1 h% F653420 Enhance ADRC rule for Acute Angle Merged Metal Check to work on a user defined minimum constraint value
! H$ ?7 _9 g- m2 l" U653471 Request for Die Text In Wizard option to Flip the DIE coordinates
! t8 {9 {( H! k+ R- l' `! t+ D653825 sigxp_tier was not reset when installing a new product suite
657180 Enhancement: Tooltip for DRC markers
657187 SI model delete enhancement
! \/ f$ x9 ^4 z: N/ k% u657189 SI Model assign enhancement #2
: I, ^+ d1 A* R/ }657501 Negative planes doesn't match with Film View
0 P% K+ H, m0 K$ O659543 Need a Report to show which Die Pins have no bond wire attached
659661 Function needs for setting the rotation angle in finger by group.
( X: w8 f! L: J* b661477 Color192 window sections to be resizable
1 I8 Y* P5 Z6 Z+ d) b) r662215 Please add the function of renaming net by batch command.
% d" u! h# t; c2 ~/ e% v662325 Skill code example axlDBGetProperties.txt not correct
662982 When you edit shape, ministat should always enable shape
. E' A& {2 l0 A7 L. y663260 Enhancement: ALG0051 message should be more specific
' H! j* w6 ?6 C$ g# v" z9 I. ]# I663754 Enhancement to create Device file when saving dra file on opening another design
! s6 R: p! U/ F6 u  C! |664240 Add CNVPATH in User Preferences to place default CNV files
  _: Y2 {/ ?) E. F2 e5 Y665798 163BETA - provide graphical examples to show result of Flexible Shape Editor actions
" o( o% W& L- d9 ?& ?/ i7 G666186 Enhancement FishEye functionality in Variant View Mode
666768 Temporary graphics for modules / groups do not reflect true size
, I# b) F' F2 a: _" @& \3 F4 a666775 Update microvia to microvia DRC markings to avoid upper and lower case confusion
# ]' a6 m: d( h1 L$ X" X& c667773 Request for ability to set grid definition by entering simple formula
668110 Customer wants to enter the value of radius when editing routes.
669373 Xnets are not formed correctly in CM. Up to 14 'extra' in a copy of the same design.
669380 Add options for ts2dml in MI
669798 Add all 5  Dyn_Thermal_Con_Type property options to Via_Array.
/ P- A; ]% W  s  c) e. R/ \+ B( z670775 Request to make the SKILL _axlSetDynamicsRotation and Mirror functions public
671194 Allegro not to crash when opening unsupported files
671337 Request performance improvement to access DML libraries from SigXplorer or PCB SI.
7 [# I7 _! a* x$ L9 |671757 Handling of double quotes in HSPICE subckt.
: M, P) I+ C/ s' W  p- B  u672930 ERROR [DRC0039] Tap may not be connected with the bus Check Entire net
7 @* ]& ]3 `: b674666 Report the wirebonds XY coordinates
675118 Cline change width command enhancement
675151 Insert comment option for database elements
; k0 z8 u1 \5 X/ Q/ b: B+ m675398 RF PCB setup should automatically point at the project file if Allegro is launched form a project manager
675551 schematic to sip layout fail
676814 Signal Library command with Allegro performance license.
$ a# @4 e7 m$ p# V( c* A676906 Add switch -regenerate_xnets to the dbdoctor dUI
  W- ]/ N6 y% d& j1 a2 g9 ^677983 about setting of ibis2signoise option "-d" as default
9 e; W2 N& N3 W* O3 B678036 Request for a Physical design compare.
678798 Identify DC nets command doesn't remove the RATSNEST_SCHEDULE
679926 Testprep fails with no route keepin. Message in testprep.log ambigious at best
680586 Explanation of functions and macros in online help
; R) n  q) B. h1 S$ Q682695 Offset is outside or on pad edge. DEFAULT INTERNAL: REGULAR-PAD message needs rephrased
682865 When using PTC format IDF files don't use forward slashes.
9 Q" y0 F+ Q8 Y2 V$ x3 z684713 pin_count view needed for packages
$ L! B# D% ]$ P7 W( d8 j684796 do not delete all vias with DRC for via array
5 k& `% S6 z$ Q. j) J5 L686103 Replace vias evenly spaced apart
3 X8 C& u+ V# A9 |686112 Add Connect and Slide keeps cline length
: t4 T) H3 u# P5 T) f7 B686122 Select objects by polygon
$ E0 g. q% y5 R# }% n4 p, `687155 License for batch signoise command
0 a, h, I0 [& D  C687187 BGA Full stagger matrix wizard generation
687201 Improvement in Find feature
& w4 R' Q/ z9 k687685 Documentation of new properties in Variables block
688047 Include blank space in pin name as the illegal character in PDV user guide
" D/ V5 ]: X$ V688830 renaming feature discrete library translator
& ?) o2 K4 V# P: I; m# G/ h; }3 r689720 Need the ability to re-center Vis's in center of Pins when a Die is changed.
695957 master.tag generated from the table design needs to contain the verilog representation of the sch.
696661 Add ability in Offset Via Generator to add vias per a given Net
" L; `& a) e* `6 y7 y, ?696812 provide description for axlCnsPurgeAll() skill function in doc
697824 Components not installed of variant design should not be extracted into SigXplorer.
4 U* e; s# t% J, u698097 Color Dialog form (color192) does not resize correctly
700262 Unable to add Signal Library Model paths in the Allegro Physical Viewer (part of the Allegro PCB SI -L tool)
700712 Defined pin locations are not used when using Die Text-in Wizard with default option Center pins on symbol origin
701514 axlCNSGetSpacing online documentation enhancement request regarding "bbvia_gap"
702190 Request support of Windows 2008 Server Editions.
702613 Request SaveRefdesModelAssignments support the include original model path option.
! [/ j) e: G* q+ r, D, L% \+ j6 D$ N703905 Need Hot Fix number Info on Help >> About
704594 Update symbol removes the text present on Package_Geometry/Silkscreen
704899 Split Bundle Methodology Should Include a Next Function
, n7 Y' f. I0 Y% Q3 j: c* U  T& Y0 U705601 Please make listnindex a public Skill command
705615 During Updating Symbol the text location and size are changed so Reset Text location is confusing
706165 idf import fails to expand drawing enough to accept text.
706457 Change type of the fourth optional argument for Mirror in axlGeoRotatePt to boolean
706463 Add optional Character in the starting of each line of the file created by axlLogHeader
706787 Fillet should remain when user slide the segment far from pin/via.
1 g: x6 Q& {4 t  {. C  p) G709119 Requesting a pull down menu with "Comp" and "Net" to be added in the Offset Via Generator
3 _- L" T( g  o! N/ G/ E: A# `; _711837 remove the comma from the image of grid value separator
714840 Enhancement: Anti-etch can be recognized as Void element.
! K2 n: E, y" G1 Z' k& b6 v8 N/ v: B715454 Option to configure Design Entry HDL for Cadence Help
715713 Enhancement for Wire Short Check during move feature
716671 About the log file of the na2 interface.
) y# _( V1 t+ u717722 Pad designer  File > save as should have recent file name in file field
718431 Enhancement request to have DRC checks on negative layers.
- g. i+ E* f6 a  H; f' z7 p3 g719050 Log file should contain username date and time while creating or saving .DRA file
719514 Request length column be added to the Dangling Line Report
720297 about "rip up thermal-relief clines"
+ d% \5 Y& L+ \722346 DRC checks for mismatches in labeling Net
9 e  u+ g6 ~8 s1 K7 O% y) V723661 Add *.pad in the File of type drop down menu when executing QVUpdate
724832 Tackpoint move on a non standard wire bond -> *Error* difference: can't handle (2043.0 - nil)
726057 Request incremental DRC update when enabling DFA constraints.
728908 Add Color View Save and Load in Symbol Editor
729947 User would like a metal usage report

9 K6 w- T" {+ l  y# f+ Y
! h; E9 n; j" u% J* x) `, NBUG CCRs
' }0 U# ?- n0 A& C- h: T--------


. _# J2 D+ m4 d3 K- V: ?CCR Description
----- -----------
----- -----------

10116 Add Intersheet references does not work in Complex Hierarchy
11833 Junction not automatically placed when it should be.
6 A8 n9 J! Y; m" S, S; |3 U* _: C8 |1 q16310 Simple hierarchy, intersheet refs not refering to H-block
9 U5 p% ~- a3 d1 H/ o$ P: F2 @19343 Request for intersheet reference to show grid reference zone
22424 Intersheet refs wont work on imported off-page connectors
34275 Ibis2signoise fails with legal characters in file
85735 Cref annotations of the P_ID+00 Bus were missing
/ f3 X. b: e4 b. U0 g! n134692 DDB_WARN: POWER_GROUP prop. not allowed wrongly coming
199343 Stackup-Aware SigXplorer
: {1 b" z- S( s' r' s207620 Part in MISC2.OLB has incorrect pin out
2 N7 |# D! h; d- s7 V' Y* c/ x2 B% _270347 Changes to AXL SKILL must be Documented.
283839 lm117 dropout voltage is too large
2 T7 `9 ~1 i% ~, \! k5 r8 r296826 Variant view displays library property
299384 Part rotation resets the text to default position
328647 Replace Cache takes time for network libraries
340323 Dynamic shapes need same tweaks in 15.7 as in 15.5.1 to fill
: @6 C$ Z" b7 k* |6 p8 ?1 ^* q341035 Dynamic shape fails to fill in design that has cline arcs
: A; ^! {. B1 q" S. D" `390692 Via not getting transferred through the Area Constraint from Allegro to Specctra
; Z9 }, L6 p* v. t405611 Environment variable for SIGNAL_INSTALL_DIR is resolved.
428261 spaces at end of pin name Could not create new pin inst library correction utility
436908 The color dialog window will loose the vertical scroll bar after being minimized.
, u  {; |. a; s( T0 Q437369 Menu selection of Export > Libraries fails to issue the dlib command.
& P0 I& s0 {1 [( Q462783 Busname is too long
495671 Unable to add the signal stubs due to the overlap between SIG_NAME & VALUE Props.
509393 NC drill legend copies null nc_param.txt to current dir.
. w' h$ ^. `; J$ s6 p+ R: \: J: u512809 Window Prt.part.ptf shrinks by 30% and I have to maximize it.
7 a8 g  `5 C5 T9 f- E5 Y" ]- b520802 Global Navigate Zoom to Object needs to remember last setting
' k1 [- U, R' C& h; k6 ?  V! |528686 During text edit the cursor overlaps a letter rather than in between
531555 The diode BAV99 from library works inverted in compare with the graphical representation.
532603 Specifying TC1 and TC2 properties does not seem to have effect
547339 CM-SigXplorer extraction shows different topology in DE HDL vs PCB Editor
548143 Dynamic shape on Etch TOP will not void properly.
550657 Importing registries do not setup printers from MWcontrol
, V1 Z  L" C0 E) L  h9 K552227 about die export padstack  layer mapping
1 B  s& Y% p1 h, c; Y: Q  W6 ]553035 Cref Synonym and Netsbypage reports do not match netlist
558164 All variants are affected by function regardless of being called for
4 Z7 `7 M! U, |& ?! n. @0 H" o. H558692 Memory leak problem in loading marker files
565681 Filling in values in CM by using ctrl+c,ctrl+v and arrow keys is not working as it should.
* j+ Z5 G3 {( G2 b3 K& E" z567606 PDV selecting pins in symbol editor shows pins off grid during move
568049 Genview crashes
$ ?7 I$ p  C0 I' Y8 T: Y5 o. d1 I" x575353 Large box displayed with place manual-h and no RefDes variable set
581848 not able to edit Padstack Boundary
591847 Add Intersheet References does not work on simple H design.
592381 Physical Min/Max line width values not check on internal rows or forms.
" v, c) b# _4 Y" k7 l: g8 C, y593076 Cannot redisplay an invisible OFFPAGE connector's name
598038 Detail button of Markers window with 16.01
601415 Allegro Design Entry Tutorial corrections.
4 ^8 ~# D% g* D4 a0 p( d601531 When using the place manual command and rotating part a ghost image is left behind
603181 Formula to calculate the Actual Temperature for Smoke is incorrect.
6 Q: K+ d, |9 y/ H- ]604965 need to document how tcl cmd addComponent handles property values with spaces
1 E9 l+ S1 r- B7 `8 T1 r9 Q9 `605843 Aliased nets do not fully dehighlight when next net is highlighted
4 B3 ~2 `5 K8 O& t5 D+ Y( Y: T606493 Targeted nets are not remaining targets
608150 TestPrep generation is creating DRC errors
608787 Missing Constraints Report
9 h# P" ~0 W/ a6 c, d. \608942 PDF Publisher output misaligns text in tables
612511 Error in Flow Tutorial regarding checking default user units
  `) N$ V/ N7 h- p612982 VLIM model giving error that line is too long
613194 Adding wire bonds with current selection does not yield DRC's, mismatching Allow DRC violations option.
3 H7 L8 `/ ?+ N; _613738 Variant BOM report lists identical parts in separate lines due to POWER_GROUP
$ K; w" ?# w: ]- r617146 Symbol fails to place through Component Browser
617327 Change root operation results in SCM crash
1 B# x! `' b" T  y  ^: E. A+ ~+ y618150 Property Editor Functionality
618617 Enabling strokes requires checking/unchecking options boxes
9 F' k& N4 Q4 `( [$ _618771 PDV error SPLBPD-382 when importing from APD.
619053 Diff Pair problem with creating them in DEHDL.
$ ~- v/ @# k: Y4 m( g. \619849 Hierarchical Blocks Loosing reference
1 w8 N+ o; _7 P9 r620001 Measurement's Maximum range calculation is not correct
% A; a0 i8 x' H' p3 u* H# H620343 Bogus error during schematic write
620826 Changing the units of dimensions does not work
621163 Ambiguity about the how is the ?start of the wire" defined in CDNSIP for ADRC Wire to bondfinger optical short
3 k+ h7 X. @! K# J" k7 G/ B622263 Drill Customization sort order for oval oblong slots should account for Size Y
0 m: I+ x, i* |* x' T/ E8 n622583 Allegro produces erroneous error msg - symbol not found when the placebound is too large for the board.
' C( b& z/ O: ~* p. F1 w; @  l622692 Why is VGSR negative for N-channel MOSFETs
624378 Device file content conflict
& D3 Q7 g2 c+ h) y  [+ Z% W% R624492 Model Editor finds the wrong model definition for BAV99
6 N: e* g' n0 U4 n* g625462 Symbol pins Property are lost when once stretched
625519 hspice_mt is not used in Channel Analysis simulation
626674 Allegro CDS_SITE setting don't appear to match documentation
) S: r) J4 q" `& A9 Q4 j627018 Find Net in instance mode displays twice
: @! K3 U# u  ^# F) U: F' C% O" q627864 EDIF c2esch crashes
628077 Degas not voiding correctly
628265 no "Unused Blind/Buried Via"Report in APD products
% I* P  `% P$ z5 {) E) n+ Z628845 Markers> Packager menu is unselectable even after pxl.mkr is created.
( `! ]6 G8 p# P2 x3 {+ {- C631344 Mouse Wheel Scroll misses the "along with the Control Button"
633130 The Verilog netlis is wrong
633223 Running skill from a HDL script causes segmentation fault.
633473 INPUT_SCRIPT inconsistency when removed from .cpm file
/ j; D% Z7 H: N  d' p/ A634075 draw_etch_outline doesn't work for circular shape/arcs
635779 Allegro OpenGL distorting text at certain zoom levels
% Y7 P; a4 T" x$ a% ^* Q' c% f; X6 Q636215 Allegro documentation for Export Parameters is incorrect
636688 Signal Model Assignment UI and Find filter association is broken
636819 Documentation wrongly indicates that DFA Analysis in unavailable in XL
; |0 l$ K* ~. R" Y637379 No column for ROOM shown in Constraint Manager
& R1 j- M+ [7 i# ~2 W( F$ Y638140 Intersheet References not offsetting relative to Port
638670 Testprep parameters - padstack selections - Bottom Side replacement text not entirely visible.
638987 Change command hangs on customer?s database
639052 Database Objects Preventing Layer From Being Deleted report fails to run
, `2 j, A( h* `639698 HOME variable defined with %USERNAME% doesn't use value of variable.
3 Q) V2 h# Z: {639829 After setting Zoom key(F10) to a new alias Tool Tip is missing the key number
640127 Correct IDF documentation regarding UNOWNED objects
' I: U. h9 j0 y: M* }4 [# J5 ?# ]640293 performance issues with scm and large pin count devices
0 n3 p0 ^" d5 k640314 The number of menus written in DE-HDL UserGuide is untrue for Unix/Linux users.
5 W+ C  P/ I/ {641503 Stop running the VAN check on a PLUMBING body symbol in PDV
# g9 D( z( r- u! z641676 Incorrect link to assign refdes help
1 G7 Q& Y+ I. e: i5 L* f642053 Drag Connected Objects icon is always display as on
- r& w. ]6 x2 E7 X642299 Switch the windows mode by set command
) D/ Q! o$ f, M8 B' o6 g642436 Save As symbol in part editor is not working fine
642713 Materials are not refreshed when material name have only numbers.
. q4 J& ~/ g9 o: g2 `8 L2 K' U642873 Dynamic shapes out of date message refers to Setup Drawing Options
643721 Attributes with Null values in symbol.css files are removed when saved in PDV
; Q) ^8 x: j: J; J; a4 e+ a2 @643949 Can not create Region-Class-Class for same net class.
644016 APD crashes when creating a tile from LEF file
644733 Import reference text file gives incorrect results
644879 Change forms to enforce naming of lib.defs file
* K* \8 x; z2 q4 I( r& j4 G4 }645046 SG1525A PWM model is reporting unmodel pins and producing incorrect results
. s% `" Q: J: P  {0 j645427 The save button is not enabled on changing the line width
645996 con2con fails to parse ppt file correctly
646175 Please modify the limit length of "Allegro PCB Editor Limits" correctly.
647555 Drill Customization text Non-standard Drill is not readable.
647628 Annotate Type should be removed from PPT Option set files and documentation
# Y7 j+ q( N5 \: \, _648443 Launching SCM without a license is not reported in debug.log
5 K: ~5 C- ~  f+ x649222 Silent install adds extra License Server to CDS_LIC_FILE on the client
/ D# l: }3 ?/ l& U  @$ s" ^' ?% f650558 Die Pad layer changed after refresh padstack
0 W9 Z% j7 |: K650997 Incorrect Pin Shape in CIS Explorer Footprint window
651000 "Wire length over parent die" violation is incorrect.
* {* G. Q2 r* Q  C6 ]5 ?651153 Results for imported CSV inconsistent in PDV
651521 Resizing the display color visibility dialog box corrupts the display
651526 Parts are missing in a advance analysis library list document and font size issue
& `+ z4 A+ x( s1 C  i& X; u! r1 u651532 Scroll bars disappear after minimizing the color visibility form
! u) T; f$ y$ M, }( h: Z, k652050 Append waveform does not work in 16.2 for .dat files created in previous release with import text format
% _& [5 o, @) m2 W652904 significantly low performance issues when using edit interface to delete ports of block
9 I* ~" Q9 z, O! f( \8 {653067 Incorrect warning SPMHNI-198 - Pin name is not legal and will be replaced by `$#?
653784 Off-page connector name change to internal starting like "I12345555"
654580 Save As should update lib.defs without executing the edit die operation
656282 BGA Generator adds outline and RefDes to wrong subclass
656723 visibility of clines in 3d viewer needs ALL instead of just CON field in layers
! Q8 j2 d2 a! i- |) L, ?: T657836 Text crop on User Preferences Editor form
658347 Rule Continuous Soldermask Coverage Check should not work on Cline Segments
659437 Move group fails to display anything with Open GL enabled.
660937 Import techfile fails with etch on layer yet layer has no etch
661369 Importing design fails with the SPCOCN-1158 error when DBL_STR_LEN 'ON'
& y2 h; [2 t* ~: ]# T/ l9 `$ w661754 Hyperlink publish pdf to correct page but wrong grid location
662622 Export Physical reports error Output Layout Filename contains space
+ T+ b6 [' H2 N662918 Skill code example for axlReportRegister does not work
662971 Moving Bondwires disconnect bondfingers.
663088 Cannot add connect to a C-line in Etch Edit Mode
663220 IMPORT_HFS_HARDSEC_ON_SWAP_PINS directive causes error on save in DEHDL
663726 ?Each? menu under RefDes is missing in BOM HDL user guide
2 \6 X* G4 N% U3 c" k" o664764 Material changes when layer type is changed
664900 Project manager User Preferences Editor form has text crop.
665236 Unable to import a Quartus-II version 9.0 pin file.
; C# n: ~- I8 M# @# N) U+ |665389 Spread between voids not working for customer design
665413 In File> "Import and Export"> "Import-ECO pin table" the NEXT button does nothing.
; e3 r+ p, u# N7 d8 K% @665451 Import - Part logic - information popup window has incorrect user preferences Editor Category
665661 Wirebond Die Escape Generator failed to generate Clines
666099 Mandating at least one symbol with sizable pins for using size..1(not for size-1..0) SPLBPD-310/SPLBPD-309 on reload
3 t7 v& V1 l8 g- e666667 Relational Table View Browsing Issue
667286 import IFF No Component Shape Line Via found in IFF file.
7 b, _2 U& h; s1 `( U, f667751 db(v(out)) and vdb(out) gives different results for FFT
4 Z( b9 z0 _/ v: a9 A7 K  F668080 Improve handling of curved routes
668393 Dielectric constant or loss tangent values do not update when changing conductor
668876 Text on the Add button is crop on the Edit via list form.
5 \& t1 B& s/ N8 j8 z2 J) s; `668892 Incorrect Parallel Length data in parallelism report
669206 Parallelism rule causing significant performance issues during DRC update
669238 Unable to use permanent highlighting for groups in version 16.x
669323 Allegro PCB SI User Guide Doc page 229 ignoring vias needs to be updated
669336 Error in documentation of DE HDL Reference Guide
670874 getVersion() function not reporting tool version
671811 Allegro extracta fails with more than 10 output files
672420 User defined property added to component instance is a function property in Allegro
672614 translator converts the symbol "\"  in the original Spice model to "[url=]\\\\[/url]"
% B+ J2 G. h7 X* U1 |( O672615 Translator generates 6 external nodes should only have up to 5 nodes
672618 Translator generates statement in the dml file: Language=hspice causing Spectre run errors
: I$ c* f1 ]3 e+ C672715 Steam_out takes a long time and then fails but the .log file reports a successful export
3 m8 A4 f1 U; H0 h- d. a  v673279 Same characters are listed as both valid and invalid in naming rules.
673410 search by net name is finding electrical
6 o8 n3 ~' Z/ |5 K( D674058 Incorrect Variant Report
674291 Library Explorer fails to start and I receive a 'Runtime Error!' pop-up
674555 If the DSN filename contains spaces, autobackup will not write any DBK files to
4 O  M) a0 m1 x3 s5 Y- D675192 Adding a second BGA caused dsa_api.c to crash
- s1 w$ x3 x) [4 }: y675231 SiP Layout doesn't handle ! characters in port names from Verilog and OpenAccess.
675562 axlWindowFit() documentation needs to be changed.
- n) u0 U! ?( Q675783 SiP Wirebond moving a BF sometimes results in the BF placement on the guideline to become unplaced from alignment option
676201 Cross section impedance not calculating with single license
; O8 D/ f/ Y8 ~/ p9 D/ i  X# c676601 behavior of launch product from library manager
677582 mirror of die component on sip designs
: U, H$ g9 _9 R. t& v678013 Error: Symbol not found, though symbol is mapped in psmpath
678427 repeatedly placed symbols has strange instance name
678538 Why derive database does not transfer the Schematic Part property to CIS
/ ^" P9 b; ^: J6 G' y678814 Spin a temp group will not rotate the symbol
678851 Difference in lengths in 16.01 and 16.2
7 Y1 E' y+ i- z, c678884 dbdoctor fixes corruption and then it's reintroduced
679224 dbdoctor states it fixes an error but the error returns
681197 Report generator Hangs Up Allegro PCB Editor
682135 Justification of $PN placeholders not working in 16.2 release
682204 Cdsserv.exe and cdsqmgr.exe crashes using 16.2 release on Windows
682331 Incorrect reference to the middle mouse button.
. S# L4 h: v/ @/ @- t8 h& o8 k! Q3 n683146 export variant path appears wrong in output folder while two DSN are open simultaneously
683182 DRC0037 shows incorrect Alternate Net Alias.
683379 ERROR in Measurement ConversionGain_XRange
684180 Sizable pins and vector pins cannot reside together in a component.
7 M: i, ?) f4 G) s' e$ i' c684661 via array created wrong results
684700 via array can not be placed on both sides of the cline
684912 16.2 documentation is incorrect for axlDeleteFillet
684915 Incorrect mention of creating graphics template in the PDV user guide
* K$ X* h/ o/ ~- ^685685 When the customer tried to merge shapes, they disappeared and  do not merge.
1 }) e) t; u% b, S2 E( c686338 ERROR #8012 Database Operation Failed with MS SQL database
686560 Changing pin group property after pin swap resets pin numbers
686736 Load property does not propagate to the associated MECH part
  \* H0 Q; }5 {2 Q687008 ERROR 8020 after removing Place Icon
* z0 l6 y; c2 O9 M, D) P687074 Part disappears when you open it
& l; \. P2 n- |6 S- h1 o5 ]* v687354 Not able to create allegro netlist 228 ERROR(SPCODD-228): Cannot package
. r  t8 P+ @$ o- Z+ G687385 Publish PDF outputs the net name (with underscore) overlaps with wire.
687708 Smoke deration calculations for Capacitor
687715 Getting Warning TJL will not be smoke checked
8 T) V6 `& \# {# k! Q/ b* Q688606 Inconsistency in synchronization between bias display and icon
689542 Comma in ESpice model name causes simulation failure
690112 Ignored nets are displayed in simulated crosstalk worksheet in CM
$ M: P: U5 T; E1 R) l( W- H691668 Stimulus editor hangs on doing change type
691740 crash when setting coincident uvias in CM beta testing 16.3
694139 Case difference of net and bus while generating FPGA netlist
694716 Waveforms are flat when using IO b-element in HSpice
695109 Incorrect Diff-pair topology extracted by Paksi-E field solver
695431 csv2ptf fails without providing any error message
696273 Shape disappears when updated in CDNSIP 16.01 and not following the constraints
. ?4 O8 T/ I, p7 m. l; h9 C696534 Pin Visibility check box doesn't work while creating part from spreadsheet editor
698494 Shape not getting filled correctly
700160 Error: TVCurve must start at time zero .
700644 Allegro Crashes on doing Zoom In
700725 Create Fanout with Via structure add structure from Top to Int. for bottom pins
9 c0 l5 Q; k: e/ L2 V- `5 A701128 Inconsistent warning message : TBreak (Tknee)is less than Simulation Temperature
702557 Incorrect Behavior with FSP 2 FPGA Option License
703324 Cross probing board DRC objects to CM DRC spreadsheet fails to zoom in
704268 remove ARC and TOGGLE rmb options when in add rectangle or add circle command
704475 Allegro SI change editor to Allegro PCB XL causes menu problems
705902 ERROR(SPMHUT-144): Illegal arc specification error when Run DBDoctor
. r; P2 O, c3 H705903 Cannot remove a matrix view after modifying the connections
( O2 w7 q: L' k& M, c706169 IDF in error has spelling mistake
706613 Diff pair is not extracting properly through design link.
706729 Import properties fails with ERROR [IMP0020]
708134 Place > Manually command menus not refreshing the Placement list
708145 Creating a netlist with Rev. 57AQ is not formatting correctly
6 G  b2 o* e6 |' u" ^4 E708634 Shapes getting incorrectly displayed in 16.2
710279 ERROR 8020# Place component operation failed.
* g+ ?& T4 J5 f, y+ n& `$ s4 p710859 Unable to create Diff Pair from Autosetup
& i0 i3 r5 K- r& I2 F3 k! J5 H; y2 g711739 selecting one component/symbol of class IC can move unrelated component due to incorrect group membership.
& d5 D1 `& j/ T! c712299 Internal application error while creating new design
712898 Netrev should not read PARENT_PPT_PART property value while importing the logic, due to which import logic fails
713465 Problems with dynamic shape creation over routed full-arcs diffpairs
! Q$ Z; u  T; H! r- K2 M! c& v9 G: S713480 Display issue when adding a custom property to the first bit of the bus.
714072 Error while linking database part
716097 Specctra is crash during route.
' {, [: V% x) y7 I3 o716212 PACK_SHORT property gives package error for visible POWER pins
, J1 W# O  J4 @  {* X' _717484 Dynamic shape creating voids when moving a symbol
718151 Geometry not selected when we click tab for selection filter in pad designer
720092 Difference of behavior for slide for segments in options tab & RMB options
720191 Delay tune cannot keep the Gap if the diffpair segment is diagonal.
' K8 D- K& K' E721415 Two buses are connected without a warning when moved on top of each other
721938 Cross-Section open error
722997 Hyperlink function does not work if zone info. includes hyphen
( O7 |7 W' o) H* K8 ?8 f723146 Pb during compilation using predicate getFileStrings
723159 Typographical Error under "Synchronizing PTF Information" section
723235 client install results in incorrect, redundant, and problematic cds_lic_file variable
724414 State Wins Over Design does not reset the subdesign_suffix block values
7 j9 j# S$ c5 r! S% Y724969 Allegro crashes when using place replicate function
! ~4 b- e5 I, `( ]# @1 \725852 Impedance has little difference - BEM2D
726731 SiP - Wirebond -> Edit -> select bond finger -> RMB Change characteristics results in bf not following snap
726763 crash during logic import in Allegro CM enabled flow
727663 Remove Subclass in My Favorites (Color Dialog) doesn't refresh properly
. _- C' X3 x' W* C+ f729496 Build error in 16.3 and 16.4 cdnsip.exe

osakau

updates so quickly !

partime

有啥好期待的。allegro越来越像protel了，庞大，低效。

黑月

如何下载？？

pcbdesigner

allegro16.3在HDI设计上确实改进不小，不过自从进入到16.0以后，操作习惯与设计效率方面个人认为还是有所下降，总的来说个人还是比较看好Cadence。