讨论下CPCI问题

yuzengshu

0 U% y2 \0 ^2 T; \CPCI 分为系统板，背板，外围板，对于外围板有死规范，但是对于，系统板，和背板的规范
，见的不多，就是对于系统板，时钟线和数据线的长度有没有限定，还有背板，时钟和数据长度的限定怎么
' h; i" f" z* W+ x计算，希望做过的朋友，给点经验，我的是PCI TO PCI桥出来，在到CPCI接口的，谢谢
大家看看这段怎么理解
1 The System Slot clock distribution circuitry shall be designed to accommodate
3 N+ r9 \$ F5 Jup to 200 ps of backplane and peripheral board skew. The following design rules
$ i& t' i) ^4 C' z( Tapply to clock distribution to backplane peripherals and local (onboard) PCI
peripherals
2 Any onboard PCI peripherals connected to the CompactPCI bus, including
! O6 @3 o% B* @/ m7 p3 j8 g- WPCI to PCI bridges, shall be provided a clock that is delayed to
) D0 M1 \1 u) H" S2 g1 L' \* B+ a, saccommodate the maximum propagation delay of the backplane clocks and
still meet the 1 ns overall skew requirement. Up to 800 ps of skew is
allowed for onboard clock distribution (including the clock buffer internal
+ X3 v. y+ p! P+ _skew). The onboard clock signals shall be delayed beyond the clocks routed
5 B) s( R' o' H' q; ^' D+ v* x* mto the backplane (Section 3.5.5.1) to accommodate best and worst case
8 ]$ D! j: z, z$ G, l0 kbackplane delays and the 63.5mm wire delay on the peripheral board.