讨论下CPCI问题

yuzengshu

0 x7 M  ^# h2 M) h
CPCI 分为系统板，背板，外围板，对于外围板有死规范，但是对于，系统板，和背板的规范
" C6 ?1 p) y$ T) y" x2 e2 l. o，见的不多，就是对于系统板，时钟线和数据线的长度有没有限定，还有背板，时钟和数据长度的限定怎么
) j/ g- J3 y3 ~0 o% ]& u计算，希望做过的朋友，给点经验，我的是PCI TO PCI桥出来，在到CPCI接口的，谢谢
: g# t5 _' r3 y9 K( ~3 V, e3 U大家看看这段怎么理解
: @. R, e+ W- h+ E4 B2 J1 The System Slot clock distribution circuitry shall be designed to accommodate
up to 200 ps of backplane and peripheral board skew. The following design rules
5 I! e6 {& V1 n% R* qapply to clock distribution to backplane peripherals and local (onboard) PCI
peripherals
& p# q5 {  N6 @" F# T2 Any onboard PCI peripherals connected to the CompactPCI bus, including
* s( ~& K8 A6 HPCI to PCI bridges, shall be provided a clock that is delayed to
accommodate the maximum propagation delay of the backplane clocks and
still meet the 1 ns overall skew requirement. Up to 800 ps of skew is
1 o- Z' F/ D6 k# M; v" Gallowed for onboard clock distribution (including the clock buffer internal
2 _+ t3 Z- f* F  \" P' ]skew). The onboard clock signals shall be delayed beyond the clocks routed
; ~: A: D. P# B# Xto the backplane (Section 3.5.5.1) to accommodate best and worst case
backplane delays and the 63.5mm wire delay on the peripheral board.