讨论下CPCI问题

yuzengshu

CPCI 分为系统板，背板，外围板，对于外围板有死规范，但是对于，系统板，和背板的规范
，见的不多，就是对于系统板，时钟线和数据线的长度有没有限定，还有背板，时钟和数据长度的限定怎么
, }: F* R3 p# S# r; Y  ~% W6 Y! C计算，希望做过的朋友，给点经验，我的是PCI TO PCI桥出来，在到CPCI接口的，谢谢
- W: G# o2 W, I. _大家看看这段怎么理解
1 The System Slot clock distribution circuitry shall be designed to accommodate
! u& m7 {/ r" c/ U& _up to 200 ps of backplane and peripheral board skew. The following design rules
apply to clock distribution to backplane peripherals and local (onboard) PCI
peripherals
2 \$ q4 T4 |9 o( A& b/ q# v2 i2 Any onboard PCI peripherals connected to the CompactPCI bus, including
) _2 c/ v" B' m1 D' Y& N' @- E/ UPCI to PCI bridges, shall be provided a clock that is delayed to
& f0 x. n6 m1 Maccommodate the maximum propagation delay of the backplane clocks and
6 S1 [) L: M& D3 J8 O: @still meet the 1 ns overall skew requirement. Up to 800 ps of skew is
. i1 c2 |7 B' u! iallowed for onboard clock distribution (including the clock buffer internal
skew). The onboard clock signals shall be delayed beyond the clocks routed
; b; X" K$ a( H$ V3 p# N9 Bto the backplane (Section 3.5.5.1) to accommodate best and worst case
backplane delays and the 63.5mm wire delay on the peripheral board.