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General$ p5 h) t: f5 d$ d
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6 E/ B# R! r! h+ ]. O Tablet, two mcu subsystems architecture6 t6 V1 f6 [$ D1 I$ p- U/ S& F0 H
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% v! W( R5 e o @ Supports eMMC/uFS boot3 |: Q3 w' t& @! N
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Supports LPDDR3
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0 w6 \2 ?1 v0 Y Supports LPDDR4X" }9 U9 O& l7 F4 A& G
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; m; d* u; F/ s9 m8 [2 O# n! l$ kAP MCU subsystem
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Quad-core ARM® 2.0GHz Cortex-A73 MPCoreTM with 64KB L1 I-cache, 64KB L1 D-cache and 1MB unified L2 cache
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Quad-core ARM® 2.0GHz Cortex-A53 MPCoreTM with 32KB L1 I-cache, 32KB L1 D-cache and 1MB unified L2 cache
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NEON multimedia processing engine with SIMDv2/VFPv4 ISA support
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5 e) O3 t0 h7 c! t8 Z" {% Z9 u DVFS technology with adaptive operating voltage from 0.6V to 1.12V
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MD MCU subsystem
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Imagination MIPS32® InterAptive processor with max. 864MHz operation frequency
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3 w& f0 J9 }0 x6 |& r( U High-peRFormance multi-core and multithread processor architecture (two cores and two threads)
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) f3 k& E& y7 k9 d! m8 g' l r9 \ 32KB L1 I-cache and 32KB L1 D-cache per core8 U8 R( L- Q( J- F4 J% o7 e" x
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384KB SPRAM (Scratchpad memory, Two-Core’s ISPRAM and DSPRAM)
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4 F9 t: R v% ? 256KB L2 Cache (share L2 cache for two cores)
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8 ~/ H( o! w( ?( v. q High-performance AXI bus Interfaces
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+ f' I; D x1 h9 [: w: G1 A Power management for clock gating control: Z C, n& o! a' n* G. ?
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p i/ t, U6 G/ W3 ~' Z FD216 DSP for running GSM modem with max. 312MHz operation frequency+ w; x' l2 b: m1 {4 _0 |2 ?
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( {& U9 g1 F4 t/ i/ X, C, ZMD external interfaces8 S1 }/ b9 f: ^- o
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~' Z* h9 C( P- r Dual SIM/USIM interface, f+ F1 g8 z+ M7 ?8 E& F5 Z
Interface pins with RF and radio-related peripherals (antenna tuner, PA, etc.)
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0 I# Q: I( t! I% W# l$ l, BSecurity
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* F2 _9 v( }& @" m6 _7 _ ARM® TrustZone® Security
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External memory interface ?. [2 H( o0 |. V
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LPDDR3 up to 4GB (single channel with 32-bit data bus width)0 _, Z6 ?& M8 C/ F- \3 D0 I6 i: a
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LPDDR4X up to 8GB (dual channels with 16-bit data bus width)
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Memory clock up to LPDDR3-1866 or LPDDR4X-3600
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Self-refresh/partial self-refresh mode
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2 K* S- h) o* P' v) v+ s& y; y Low-power operation; w( x; q7 w8 Q- ]0 T) x/ y, v
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Programmable slew rate for memory controller’s IO pads
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0 n. Y+ O. I5 Z6 N Dual rank memory device
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Advanced bandwidth arbitration control6 s9 h: H8 r0 b% |2 P
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( D8 O' N! Y0 l+ m) k! w$ xPeripherals! R7 }+ ?2 V' z) k4 T0 ?- J/ @, g, ? d
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0 K; T' S- }' P2 h' }! n% O USB one port with USB3.0 device mode or USB2.0 OTG mode" q" h$ f$ v X- E ?7 d0 R( Q
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eMMC5.1
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uFS 2.1
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8 Q, k3 X( n. U 3 UART for debugging and applications
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' ?5 Z M3 N* n; \+ v 6 SPI masters for external devices0 N- [# K; o, a
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$ N5 b3 K1 k, T 6 I2C/3 I3C to control peripheral devices, e.g. CMOS image sensor, LCM or FM receiver module# x: y" C# v/ o W' \5 U3 J) i
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2 D% c1 U8 W& |3 R3 E4 j6 z Max. 3 PWM channels (depending on system configuration/IO usage)
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7 {4 K1 j k8 [- |1 i8 O1 N I2S for connection with optional external hi-end audio codec) l6 n& C. r# t" A0 ]: I/ E
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GPIOs
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2 sets of memory card controllers supporting SD/SDHC/MS/MSPRO/MMC and SDIO2.0/3.0 protocols
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6 ]- U( \: f* f+ e) O% {# hOperating conditions8 c E: n: }$ Y* l
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" e* ^+ w+ { Y Core voltage: 0.7V/0.8V9 ]5 z7 m3 w* f V
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S8 ^: {1 ^/ R8 d+ T5 F I/O voltage: 1.8V/2.8V/3.3V ( G, T* _: N9 r. i P5 k/ T; a
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; u0 c) N. h* B5 ]- [1 L: z4 }4 c; d Memory: 1.1V/0.6V D4 ]# M1 Y7 S9 r5 R
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# Z) k9 S, a6 b- x& `+ Q4 }% V2 {. W LCM interface: 1.8V7 \1 w6 U+ y8 {( n9 H1 O- B
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Clock source: 26MHz, 32.768kHz# I) N/ G/ w4 u& h1 M; X$ E- T/ B
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Type: VFBGA
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7 Y; O2 {- J; h& q 11.8mm*11.0mm( P; w1 X4 U. a- m) m; c/ i) u
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# j5 K0 K! v1 j7 d Height: Max. 0.9mm
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' Z; }, f9 a/ M: A Ball count: 599 balls# ]" P# j# j! @- ?2 B
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Ball pitch: 0.4mm
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; {4 v% A0 I& n0 c+ I FDD/TDD Up to 300Mbps downlink, 150Mbps uplink
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Downlink carrier aggregation (CA) ability; 1.4 to 20MHz RF bandwidth per component carrier (CC) and up to 2 CCs
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6 I" E$ m# S5 [. v2 F 8*2 downlink SU-MIMO per component carrier
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9 P4 Z ?1 Y5 C7 e- |7 n Downlink MU-MIMO per component carrier
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Supports feICIC3 m0 s7 H3 V) W/ A0 c
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Supports MBMS
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6 |# j, j$ g, V$ E/ K Uplink CoMP ability2 Z0 n( p6 ]. x. @/ n! J Q
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Advanced Interference Cancellation5 m$ N0 K6 r! g( D8 @
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Transmit Atenna Selection0 e) M1 h( Z2 u& g
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3G UMTS FDD supported features" R; I# }3 x3 q$ W; B3 q( G: p# k
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" t/ x# F' O2 V$ @2 t 3G modem supports most main features in 3GPP Release 7 and Release 8' q0 m1 {( U, L+ P: h, U1 r
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CPC (DTX in CELL_DCH, UL DRX DL DRX), HS-SCCH-less, HS-DSCH
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8 J4 o X! l" v1 B Dual cell operation6 x0 ?# h! C. @* U
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MAC-ehs
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4 ]. l: p4 N" Q9 ?& o' B9 p2 o 2 DRX (receiver diversity) schemes in URA_PCH and CELL_PCH( R; o6 R! Q* }. D% T. g0 t" \* |- Z
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8 G; A6 {( c1 H: M- Q- Z Uplink Cat. 7 (16QAM), throughput up to 11.5Mbps6 b2 d* P# R5 \* _* c' Z
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6 y; P4 d0 ? y" |2 J$ m Downlink Cat. 24 (64QAM, dual-cell HSDPA), throughput up to 42.2Mbps. }/ S4 ]4 L1 o' {8 t0 y
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8 r" Y$ l. k5 D( J# a, I& B Fast dormancy- B9 ^1 {: a8 D! E
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ETWS' l1 L/ m+ Y9 p+ {. o9 N
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% q5 M4 J+ g3 V! M4 A5 h Network selection enhancements6 p) M. q& \# u3 c
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' q5 m1 \5 r, }4 m3 ]: E Transmit Atenna Selection# U, |( w1 D* G3 B5 o6 x
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TD-SCDMA
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CDMA/HSDPA/HSUPA baseband
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TD-SCDMA Bands 34, 39 & 40 and Quad band GSM/EDGE
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% ?1 f7 N. B0 m8 r6 O( K Circuit-switched voice and data; packet switched data + X; \$ g- A. P# Y; R- G
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8 C. D- Y& |( K$ d4 ^2 v 384/384Kbps class in UL/DL for TD SCDMA! _; A. g. C1 v6 O
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( g2 t4 K6 f* j: y6 A) c* s TD-HSDPA: 2.8Mbps DL (Cat.14)* Z" g4 y( J' x; O. W
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TD-HSUPA: 2.2Mbps UL (Cat.6)
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( f0 K/ H# \' X/ Z F8/F9 ciphering/integrity protection6 O- B. a# Z" E: ], D
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. r/ p8 }. \( z$ E Transmit Atenna Selection; H) b' A1 U* P. f( X
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Radio interface and baseband front end
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8 M3 t1 }/ L' m s High dynamic range delta-sigma ADC converts the downlink analog I and Q signals to digital baseband.
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10-bit D/A converter for Automatic Power Control (APC)
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, M6 ?$ _, p+ X Programmable radio Rx filter with adaptive gain control
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Dedicated Rx filter for FB acquisition) @$ S' ? m, R. P, k
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8 Y" I7 J7 r1 w, k1 u) _ Baseband Parallel Interface (BPI) with programmable driving strength
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Supports multi-band
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& v( b( X, x' z1 D% h7 p( IGSM modem and voice CODEC" s& U, _9 D/ q+ f# i! t7 W5 \4 }
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Dial tone generation
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Noise reduction
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. h m8 L3 J, v2 I. o5 Y( Q1 P Echo suppression3 X# ?& g% \, G/ V
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b3 b) F H3 ^: }7 Q2 F9 W. O Advanced side-tone oscillation reduction' a: a/ z& l) @" O
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Digital side-tone generator with programmable gain7 ~) u. Z) O5 k$ K* n. R
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Z# W) T7 r" z$ N! @ 2 programmable acoustic compensation filters
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y: L& b) p& r8 t ^ GSM quad vocoders for adaptive multi rate (AMR), enhanced full rate (EFR), full rate (FR) and half rate (HR)2 J. S5 w& f: H; }4 K) L
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1 d3 @6 m9 r2 f GSM channel coding, equalization and A5/1, A5/2 and A5/3 ciphering; n3 ~6 i( Q# W! w' ~1 T
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GPRS GEA1, GEA2 and GEA3 ciphering
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# z4 c- M0 ?. o6 K Programmable GSM/GPRS/EDGE modem A+ A9 O4 l. k; U2 h+ y. z
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+ q7 H1 x: H& U3 Q. ^% t) \ Packet switched data with CS1/CS2/CS3/CS4 coding schemes
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* w1 U: e' ~/ s4 H2 ]+ x$ f! N4 V2 T GSM circuit switch data% E! T. g8 e. ]3 @, B# X; V$ E% m1 d
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' S. r2 B8 P! y8 d, u H$ @- s GPRS/EDGE Class 12! b# L- A5 }8 C ?9 P0 Z
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" H0 b5 |+ Q- G6 A0 s( F% e! ECDMA2000 modem interfaces
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Supports CDMA2000 1xRTT (releases 0) and CDMA2000 HRPD/1xEV-DO Revision 0 and A5 s5 z- I% ?( `& D6 t7 n! Q& c
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4 ]1 F) e, n: Z Supports maximum 1x data rates of 153.6kbps for forward and reverse links and DO data rates of 3.1Mbps for forward link and 1.8Mbps for reverse link8 c7 Q- o. E2 d5 v+ f: u0 v: B p
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/ U1 N' r% Y6 d Hybrid operation between 1x and HRPD
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Simultaneous Hybrid Dual Receiver (SHDR) support
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Supports 1x Diversity9 H" D5 t- k+ H7 v4 s/ F
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Supports SRLTE
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Transmit Atenna Selection
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5 d2 B9 v: D- P- W4 b更多芯片参数特点，可参考MT8788规格书资料
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发表于 2019-11-27 15:28
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