再给大家分享一下全志R11芯片处理器相关

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R11代表了Allwinner在智能硬件处理器上的最新成就，它集成了一个以1.2GHz的速度工作的单ARM CortexTM-A7 CPU，并支持多个外围设备。


CPU

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ARM CortexTM-A7 MP1 Processor
Thumb-2 Technology
1 Z" G3 s. p( m$ T! r" ESupports NEON Advanced SIMD(Single Instruction Multiple Data) instruction for acceleration of media and signal processing functions
Supports Large Physical Address Extensions(LPAE)
VFPv4 Floating Point Unit
32KB L1 Instruction cache and 32KB L1 Data cache
  W& w. t7 ~  H6 ~/ {" F128KB L2 cache
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Memory Subsystem
Boot ROM
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) l! s: C6 y8 V% ?6 b, NInternal on-chip memory
9 D& L, f1 T3 g8 M9 zSupports system boot from the following devices:
- SPI Nor flash
- SPI Nand flash
5 R5 V8 B! w. y- SD/TF card
- eMMC
Supports system code download through USB OTG


SDRAM
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Internal on-chip memory
Built-in DDR2 in the R11
Clock frequency up to 400MHz
Supports Memory Dynamic Frequency Scale(MDFS)
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' Z- R% ^' X) N9 H; i8 X% e( ASD/MMC

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$ r+ h* Z) Q" l+ n/ y9 I4 rExternal off-chip memory and storage device
4 @, ]  q: f) E* M3 _1 x6 U! YTwo SD/MMC controllers
1/4-bit data bus
Complies with eMMC standard specification V4.41, SD physical layer specification V2.0, SDIO card specification
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' h. O# _; F: t5 ^$ `( V& X! Y+ |Supports hardware CRC generation and error detection
Block size from 1 to 65535 bytes

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/ T% U5 j) ^! e  q% OSystem Peripheral
Timer

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Three on-chip timers with interrupt-based operation
0 T8 u, i) w  t5 {, a1 \8 b( J( uOne watchdog to generate reset signal or interrupt
33 bits Audio/Video Sync(AVS) Counter
6 u- m# ?8 k0 x" b24MHz or internal OSC clock input

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) Q5 z8 E) J1 mHigh Speed Timer
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' U$ E3 y! n6 e* AUp to two high speed timers
Counters up to 56 bits
! D3 Y3 h& [; B! c# TClock source is synchronized with AHB1 clock, much more accurate than other timers

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5 _0 B- f0 E6 o+ aGIC
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Supports 16 Software Generated Interrupts(SGIs), 16 Private Peripheral Interrupts(PPIs) and 125 Shared Peripheral
7 c- H0 M% R, |4 Y* t4 s# gInterrupts(SPIs)

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DMA


Up to 8-channel DMA
" u4 H1 [/ D5 T! [6 aFlexible data width of 8/16/32 bits
Supports linear and IO address modes
Supports data transfer types with memory-to-memory, memory-to-peripheral, peripheral-to-memory
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# J+ P# G1 s+ Q! OCCU


2 J; n8 ~! ^% S2 A9 V; Q3 ]9 PLLs
One on-chip RC oscillator
One 24MHz external oscillator
0 [% {+ J& M. w# _( d9 e5 zOne 32.768kHz external oscillator
& [& d9 g; a. |& ~Clock management: clock gating ,clock enabling to the device modules, clock reset, clock generation, clock division

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PWM

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  E* Z" P: L. |, jTwo PWM channels
Supports outputting two kinds of waveform: continuous waveform and pulse waveform
0% to 100% adjustable duty cycle
- o7 |* K. I5 s' r$ y$ c  cUp to 24MHz output frequency
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RTC
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  h4 q8 y; D) {8 ]+ OTime,calendar
Counters second,minutes,hours,day,week,month and year with leap year generator
Alarm:general alarm and weekly alarm
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LRADC
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* K; \8 g  s* t! W% E6 q( D' C6-bit resolution
Supports hold key and continuous key
Supports single key, normal key and continuous key
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. U: [- b2 N7 a5 yCrypto Engine


Supports AES 128/192/256-bit with ECB,CBC,CTS,CTR mode
Supports DES/TDES with ECB,CBC,CTR mode
Supports SHA1 and MD5
160-bit hardware PRNG with 175-bit seed


! @. `/ `; b7 e4 U6 PDisplay Subsystem
3 C0 n5 Z8 w' |% i$ O1 YDE2.0


Output size up to 1024x1024
) n/ M( E: R. i! ^+ H: ], j9 cSupports three alpha blending channel for main display
Supports four overlay layers in each channel, and has a independent scale
* U/ p0 [7 K) _) D, @2 v6 [+ F' PSupports potter-duff compatible blending operation
& l  R) b. W' U0 U! S7 I1 zSupports input format YUV422/YUV420/YUV411/ARGB8888/XRGB8888/RGB888/ARGB4444/ARGB1555/RGB565

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Display Output


Supports LVDS inteRFace with single link, up to 1024x768@60fps
/ G9 r2 J$ I/ X% }( h: }Supports RGB interface with DE/SYNC mode, up to 1024x768@60fps
8 ]1 k  a* ?2 r/ g8 O. f6 |Supports serial RGB/dummy RGB/CCIR656 interface, up to 800x480@60fps
Supports i80 interface with 18/16/9/8 bit, support TE, up to 800x480@60fps
Supports pixel format: RGB888, RGB666 and RGB565
Dither function from RGB666/RGB565 to RGB888
Gamma correction with R/G/B channel independence

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+ \$ u& J+ ^+ z% E1 ^$ z+ FVideo Engine
Video Decoding


Supports video decoder for H.264 and JPEG/MJPEG
! K9 I4 T$ n  X1 ^2 K- KSupports H.264 BP/MP/HP up to 1080p@30fps
Supports H.264 output formats :NV21,NV12,YU12,YV12
5 H7 @  {: u9 J4 YSupports JPEG/MJPEG up to 1080p@30fps


Video Encoding

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  `8 s$ I7 H& {; |9 h/ \3 ^2 M7 _; tSupports H.264 video encoding up to 720p@60fps
& r' k6 E3 M9 J% v; S' n7 JJPEG baseline: picture size up to 8192x8192
" e) u" J; I) U, ~8 P; C8 z. S/ s: `Supports input picture size up to 4800x4800
( v1 H+ m* r1 p! x! ~Supports input format: YU12/YV12/NV12/NV21/YUYV/YVYU/UYVY/VYUY
Supports Alpha blending
6 u  q8 J, e  wSupports thumb generation
, c" a" R: B% j& g9 X6 PSupports 4x2 scaling ratio: from 1/16 to 64 arbitrary non-integer ratio
Supports rotated input


Image Subsystem
Image Input

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  o" }* \* G/ D) S1 k& ?3 f. ISupports 8/10-bit CMOS sensor parallel interface
8 {/ z9 w) b" J1 Q  K% o2 `Supports 8-bit CCIR656 protocol for NTSC and PAL
Supports ITU-R BT 1120 protocol for HD-CIF system
Supports 16-bit interface with separate syncs
) G8 u8 P# o* x0 \1 N: Q$ oMIPI-CSI2 interface compliant with MIPI-DPHY v1.0 and MIPI-CSI2 v1.0
Supports MIPI-CSI2 1/2 data lanes configuration
Supports Format:
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' \/ q- o6 z/ F* g8 q- YUV422-8/10 bits
- YUV420-8/10 bits(for MIPI-CSI2 only)
# t: g1 \+ G' Y3 t0 J, B" \# C- RAW-8/10 bits
- RGB888/RGB565(for MIPI-CSI2 only)
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8 w3 Q6 Z- X6 E" r  o  g& YPerformance:

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( m( k  n! g/ d+ N) ?9 b% F- Still capture resolution up to 5M with parallel interface
- Video capture resolution up to 1080p@30fps with parallel interface
- Still capture resolution up to 5M with MIPI-CSI2 interface
) z6 u' X2 Z' Y# E' P- G$ z' b0 \- Video capture resolution up to 1080p@30fps with MIPI-CSI2 interface
- MIPI-DPHY maximum data rate up to 1Gbps per lane
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, W4 Q% i- t8 v# x& CISP
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Supports input formats:8/10-bit RAW RGB,8-bit YCbCr
Supports output formats: YCbCr420 semi-planar,YCrCb420 semi-planar, YCbCr422 semi-planar,YCrCb422 semi-planar,YUV420 planar,YUV422 planar
+ M  t: t9 Y- P0 D3 {+ x6 @2 CSupports image mirror flip and rotation
Supports two output channels
4 [9 }2 r, R5 j& B* r# N! ySpeed up to 8MPixels@24fps
+ X' A2 U- [4 }8 X/ h+ YDefect pixel correction
5 @& ]/ ~& D4 K; e5 sSuper lens shading correction
Anisotropic non-linear Bayer interpolation with false color suppression
/ l' U" r! n% r' jProgrammable color correction
3 P$ ]# {2 W+ B0 S, tAdvanced contrast enhance and sharping
1 o4 G) `6 K1 R- u' j5 M) HAdvanced saturation adjust
" @+ }: l2 M( f6 PAdvanced spatial(2D) de-noise filter
4 z& e9 k6 H! J6 aAdvanced chrominance noise reduction
Zone-based AE/AF/AWB statistics
9 `" ~/ t* F7 Z8 c5 @# {3 ZAnti-flick detection statistics
Histogram statistics


Audio Subsystem
Audio Codec
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Two audio digital-to-analog(DAC) channels
Supports analog/digital volume control
, k& y& ^* Z$ Z# M6 MOne low-noise analog microphone bias output
Analog low-power loop from microphone to headphone outputs
Supports Dynamic Range Controller adjusting the DAC playback output
One Microphone input
  y+ w# {3 H3 [3 t: aOne Stereo Lineout output
. c% ^, c8 F. @$ }& G( q# uTwo audio analog-to-digital(ADC) channels
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- 92dB SNR@A-weight
- Supports ADC Sample Rates from 8kHz to 48kHz
: D$ B1 Q. V2 v: qSupports Automatic Gain Control(AGC) and Dynamic Range Control(DRC) adjusting the ADC recording input
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External Peripherals
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USB

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, N: C4 F4 J7 s( mOne USB 2.0 OTG controller with integrated PHY
& t" l9 Y- n0 s: @" TComplies with USB2.0 Specification
2 C; R/ I# t& B4 S8 }# _/ ]Supports High-Speed(HS,480 Mbit/s),Full-Speed(FS,12 Mbit/s),and Low-Speed(LS,1.5 Mbit/s) in host mode
Complies with Enhanced Host Controller Interface (EHCI) Specification, Version 1.0,and the Open Host Controller
Interface(OHCI) Specification,Version 1.0a for host mode
$ ~3 I* {# T: u2 o, r) qUp to 8 User-Configurable Endpoints in device mode
6 V$ c. X$ q4 `3 ZSupports point-to-point and point-to-multipoint transfer in both host and peripheral mode

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* u' L4 f2 m* E" xI2S/PCM


: g& @$ E! O7 S  d; g$ rCompliant with standard Inter-IC sound(I2S) bus specification
Compliant with left-justified, right-justified, PCM mode, and TDM(Time Division Multiplexing) format
- T- _3 V1 b" g* G# dFull-duplex synchronous work mode
+ l! S1 y, G& G/ X9 [: UMaster and slave mode configured
+ P9 O2 d5 ]4 Q8 k6 JAdjustable audio sample resolution from 8-bit to 32-bit
- d; G4 l5 ?, k8 ?Sample rate from 8 kHz to 192 kHz
( c6 W) M' B7 h6 ^0 X# {Supports 8-bit u-law and 8-bit A-law companded sample

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EMAC

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" ]7 L8 U+ _; z- e9 tSupports 10/100/1000 Mbit/s data transfer rate
Supports RGMII/MII/RMII interface
5 C& t; W' ~, ZFull-duplex and half-duplex operation
Linked-list descriptor list structure
3 g  p. E- Q* p, XProgrammable frame length to support Standard or Jumbo Ethernet frames with sizes up to 16 KB
" b3 z- |& l9 R; b/ |Supports a variety of flexible address filtering modes
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3 P" i. g( ~2 n& S" tUART
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Up to three UART controllers
64-Bytes Transmit and receive data FIFOs for all UART
Compliant with industry-standard 16550 UARTs
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! ^3 F" k# `# o- X/ p# w; l9 K不直接翻译了，且资料内容太多了，想要看完整的，可参考全志R11 datasheet
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