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改进如下：6 T6 S8 y( ?& M+ P
, W* V- J2 ] T5 w) o# h+ T' bHOTFIX VERSION: 015. g9 k, j# \* M# _) @; e
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; O* o& k8 m& p' _! v, a8 R: @CCRID PRODUCT PRODUCTLEVEL2 TITLE
* T4 ^: d, [: j3 n========================================================================================================. }! Z3 q& E7 a
264893 APD EDIT_SHAPE Shape Edit Boundary toggle invokes S pattern not flip
Z# x2 Z$ `) A609206 APD OTHER parallel command fails to run on mcm files
' P' C3 U8 b7 J8 p) n646375 PCB_LIBRARIAN CORE Saving a design or Export Physical takes a long time
/ \# `6 Z7 p0 b650721 PSPICE DEHDL Pins shorted due to update in unnamed netnames
% J x( @; j: D6 R# J665343 APD EDIT_ETCH Diff pair is routed with gap less then primary gap for a smal" w! L5 Q: A! E# w7 O) L
666736 ALLEGRO_EDITOR ARTWORK There are some shapes not filled when RS274X garber is import# N3 B4 Q( C. j& [8 }& p
669411 CONSTRAINT_MGR CONCEPT_HDL DEHDL Constraint Manager crashes when SigXP is opened for a n
( T& R ^: \! v! W669769 PSPICE DEHDL Edit Model on page border causes crash
5 n l6 d) F# _" D/ T! M671583 ALLEGRO_EDITOR SCHEM_FTB PartLogic does not work with library level ptf files.
{2 M% ?/ E6 t672656 CONCEPT_HDL CORE Using Select cut/paste commands crashes concepthdl
$ e# c' ]8 q; R, j6 Y672806 F2B PACKAGERXL Export physical fails if datasheet hyperlink is defined as ke; {2 ~8 k5 U L7 w K6 L% d
672995 CONSTRAINT_MGR CONCEPT_HDL Changing target on net in RPD groups does not clear the pinpa8 p5 N) V0 G/ x' r5 t
676268 ALLEGRO_EDITOR EDIT_ETCH MIN/MAX heads up meter not working for some nets9 k$ V- N( D9 o7 ?8 b& b9 U
677049 ALLEGRO_EDITOR SHAPE Wrong DRCs created on sliding Nets
( Q% }2 j* G0 b" [8 i: V: j) k& z677123 ALLEGRO_EDITOR SHAPE Shape does not void cline in slide mode.
8 }: {7 m0 @6 p678030 SPECCTRA LICENSING Cannot start Allegro PCB Router with SIP525 license9 F' h& _5 I3 z8 A: q
678075 CONSTRAINT_MGR ANALYSIS Wrong buffer delays are used in switch/settle times in CM
$ X+ J( J' S( l, K% b678794 SCM PACKAGER Unable to package subdesign
/ C- n- Y" `& }% O- h) u) L# u678851 SIG_INTEGRITY OTHER Difference in lengths in 16.01 and 16.2
M) W3 y3 R1 {6 Y; p678884 ALLEGRO_EDITOR DATABASE dbdoctor fixes corruption and then it's reintroduced
4 v. T4 m6 l7 n$ Z& r679224 ALLEGRO_EDITOR DATABASE dbdoctor states it fixes an error but the error returns2 d- x5 P- {) ^
679228 CONSTRAINT_MGR DATABASE Wire Length over Parent Die ADRC is not updated dynamically i: L2 x7 Y v, f* |# o
679288 CONSTRAINT_MGR SCHEM_FTB ECSets on some of the nets are missing after importing the lo# Z1 S5 B8 U5 ], @% f5 C
679954 ALLEGRO_EDITOR DATABASE Unable to keep changes to the VIA list in constraint manager./ x0 t" f* v; L2 v
679990 APD VIA_STRUCTURE In Via Structure > Replace after selecting the Old and New st3 ^, T8 O' O. J) M
681074 ALLEGRO_EDITOR SHAPE void is not correct with pin having multidri
" ^9 p. m; y4 U681140 SIG_INTEGRITY TRANSLATOR Spc2spc crashes on attached testcase) x6 G7 V, G/ t' g& _' U% u
681975 APD SKILL axlExtentDB and axlExtentLayout functions will return nil if
: s* Z1 h+ [, f/ _. }4 i. I, n682587 ALLEGRO_EDITOR OTHER Allegro moves all text when any text on symbol is out of exte
6 C* i; L" @5 I z683479 ALLEGRO_EDITOR DRC_CONSTR Modifying design pad to multiple drill creates unexpacted P-L
9 v1 d& `8 D" k' R683515 APD DRC_CONSTRAINTS DRC is possibly bogus as it seems to be confusing layers |
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发表于 2009-7-27 21:04
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支持！
反对！
没有人告诉啊，