Verilog锁存器，锁存6组数据后为什么读取时第一组数据为什么是锁存的第二组数据？？？

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Verilog锁存器，锁存6组数据后为什么读取时第一组数据为什么是锁存的第二组数据？？？

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/* en为使能端，get为锁存/显示数据按键，rst为置零按键 */
% O! W6 i5 u# k6 |module suocun(

en,get,rst,s1_1,s2_1,s3_1,s1_2,s2_2,s3_2,key,n1_1,n2_1,n3_1,n1_2,n2_2,n3_2

);

input en,get,rst;
* P, L' Z3 @% U% Zinput [3:0] s1_1,s2_1,s3_1,s1_2,s2_2,s3_2;

output reg key;
& j4 x- |& b& U" a$ y+ o& Soutput reg[3:0] n1_1,n2_1,n3_1,n1_2,n2_2,n3_2;

reg[2:0] cnt1;
" h3 a, P4 L- p1 M( |reg[2:0] cnt2;

reg[3:0] data1_1_1,data1_1_2,data1_2_1,data1_2_2,data1_3_1,data1_3_2;
! _$ w. n) H# k& u& N) lreg[3:0] data2_1_1,data2_1_2,data2_2_1,data2_2_2,data2_3_1,data2_3_2;
, z& c( |" ], j( E* ireg[3:0] data3_1_1,data3_1_2,data3_2_1,data3_2_2,data3_3_1,data3_3_2;
reg[3:0] data4_1_1,data4_1_2,data4_2_1,data4_2_2,data4_3_1,data4_3_2;
reg[3:0] data5_1_1,data5_1_2,data5_2_1,data5_2_2,data5_3_1,data5_3_2;
reg[3:0] data6_1_1,data6_1_2,data6_2_1,data6_2_2,data6_3_1,data6_3_2;

always @(posedge get or negedge rst)
begin
2 G+ N0 j3 E) ]: \  q# A9 Aif(!rst)
begin
, }7 h+ _. V  N" m# j% F; ~cnt1<=3'd0;
cnt2<=3'd0;
end
else
& n4 d8 J! M# d. @begin
if(en)
begin
+ ~6 U# |# o2 c; o' W/ i1 ]' k+ c( Iif(cnt1==3'd7)
' V5 N# n. _- {, d2 e3 j+ Acnt1<=3'd0;
  ^, s$ U7 U8 }, ~% {6 }4 u1 M, ielse
cnt1<=cnt1+1'b1;
end
else
/ d# g( e/ w" p" h- ~begin
if(cnt2==3'd7)
+ \9 }7 }  S9 p4 P. e! `" ?cnt2<=3'd0;
& G% t# C6 k' h$ \! @3 Y6 G3 i% c8 b2 [else
2 J& ], T6 v! {4 K4 rcnt2<=cnt2+1'b1;
- T% i1 K% S) s& iend
end
- S& ~- W/ g7 B0 ]9 {8 X2 g% c& bend

always @(*)
begin
if(!rst)
  @3 z' I) x: v; t7 qbegin
9 z& C0 b! t7 m; ~$ i2 U3 M% Jdata1_1_1<=0;data1_1_2<=0;data1_2_1<=0;data1_2_2<=0;data1_3_1<=0;data1_3_2<=0;
& Y, V- `- l9 Fdata2_1_1<=0;data2_1_2<=0;data2_2_1<=0;data2_2_2<=0;data2_3_1<=0;data2_3_2<=0;
, s2 A( O4 Y7 C8 vdata3_1_1<=0;data3_1_2<=0;data3_2_1<=0;data3_2_2<=0;data3_3_1<=0;data3_3_2<=0;
% A# C! e7 B  N+ m- s! ndata4_1_1<=0;data4_1_2<=0;data4_2_1<=0;data4_2_2<=0;data4_3_1<=0;data4_3_2<=0;
data5_1_1<=0;data5_1_2<=0;data5_2_1<=0;data5_2_2<=0;data5_3_1<=0;data5_3_2<=0;
data6_1_1<=0;data6_1_2<=0;data6_2_1<=0;data6_2_2<=0;data6_3_1<=0;data6_3_2<=0;
( H3 L& ^5 B5 L- J  tend
else
, _+ u1 [) e' F, |begin
if(en)
begin
9 K. H7 B! ]9 y  X& o! L$ E) B9 u, Jcase(cnt1)
3'd1:
; T* d( ~- L: X) J7 _0 |$ h, Bbegin
data1_1_1<=s1_1;data1_1_2<=s1_2;data1_2_1<=s2_1;
: d: k$ R: g7 \data1_2_2<=s2_2;data1_3_1<=s3_1;data1_3_2<=s3_2;
2 J: P2 a! [& F) K$ ]& s0 h, Iend
3'd2:
' }  ]8 x2 B# j9 obegin
% x+ W# ?# x+ U1 ]/ O! Z! o6 Ddata2_1_1<=s1_1;data2_1_2<=s1_2;data2_2_1<=s2_1;
) m6 Y3 S$ P4 t5 B, c1 Adata2_2_2<=s2_2;data2_3_1<=s3_1;data2_3_2<=s3_2;
3 B) X0 a# _) b/ h; J! nend
2 a) A4 \5 X" r4 U, q  c' M' h6 F) @3'd3:
1 |/ V$ N1 K7 X$ A. pbegin
5 N9 N8 @: B  F( a1 ?" Q# ?, o) qdata3_1_1<=s1_1;data3_1_2<=s1_2;data3_2_1<=s2_1;
' Z. L4 @) Q4 A  adata3_2_2<=s2_2;data3_3_1<=s3_1;data3_3_2<=s3_2;
end
7 @' t; n% E% T9 N+ M& J- ^# V3'd4:
begin
7 ]% i# ]5 V% [9 p) X2 ndata4_1_1<=s1_1;data4_1_2<=s1_2;data4_2_1<=s2_1;
data4_2_2<=s2_2;data4_3_1<=s3_1;data4_3_2<=s3_2;
end
9 I4 V4 E7 [1 R3'd5:
; o- @% x% ^4 Z) Jbegin
data5_1_1<=s1_1;data5_1_2<=s1_2;data5_2_1<=s2_1;
* W$ U' Q  _2 f! A0 C" D( ?data5_2_2<=s2_2;data5_3_1<=s3_1;data5_3_2<=s3_2;
5 t7 S9 G5 J; A# h- t# M% H6 i) `- }end
  {, B- ^5 _" u. D( \. _0 N3'd6:
begin
; w5 a; d: l6 R0 v# Hdata6_1_1<=s1_1;data6_1_2<=s1_2;data6_2_1<=s2_1;
3 [/ _) l2 v$ p6 idata6_2_2<=s2_2;data6_3_1<=s3_1;data6_3_2<=s3_2;
end
default: ;
- ?" T/ N& O+ V" pendcase
- ]- t) k8 S4 j4 c& J6 Iend
6 `! z: o& H% c7 Fend
, e! a. n! y2 n1 q. G( Pend

always @(*)
begin
if(!en)
) W0 R  ~* ^" Z; m4 kbegin
case(cnt2)
% X: u, u" a& U3'd1:
# d. n4 V' J& ^begin
n1_1<=data1_1_1;n1_2<=data1_1_2;n2_1<=data1_2_1;
5 h  \! Q0 ~/ U3 ?" Y8 z4 `4 \n2_2<=data1_2_2;n3_1<=data1_3_1;n3_2<=data1_3_2;
: Z$ \9 C/ X9 p0 _" M9 ]end
3'd2:
begin
# K9 o- n4 K5 T/ o- on1_1<=data2_1_1;n1_2<=data2_1_2;n2_1<=data2_2_1;
* h, d) m" `$ z, Y* Y: Mn2_2<=data2_2_2;n3_1<=data2_3_1;n3_2<=data2_3_2;
end
3'd3:
begin
n1_1<=data3_1_1;n1_2<=data3_1_2;n2_1<=data3_2_1;
$ j# _4 ?! Z- w, l7 [4 ?n2_2<=data3_2_2;n3_1<=data3_3_1;n3_2<=data3_3_2;
end
3'd4:
2 ?7 }& R# c9 zbegin
" K, r7 K) G2 c0 ]* @# a- h1 w2 j7 |n1_1<=data4_1_1;n1_2<=data4_1_2;n2_1<=data4_2_1;
* X8 F8 ~& t- C" C6 m8 H! j1 a/ Rn2_2<=data4_2_2;n3_1<=data4_3_1;n3_2<=data4_3_2;
end
8 S' U" S% Z6 Y3'd5:
begin
" _. ]5 X$ R6 p- |n1_1<=data5_1_1;n1_2<=data5_1_2;n2_1<=data5_2_1;
n2_2<=data5_2_2;n3_1<=data5_3_1;n3_2<=data5_3_2;
" I8 m. A$ D& T! q6 l/ T  w) e- b) Send
3'd6:
  A  `: B8 m, p4 W# wbegin
1 S, B$ v/ X8 u$ T4 an1_1<=data6_1_1;n1_2<=data5_1_2;n2_1<=data6_2_1;
! b1 E8 E+ i$ Z1 Hn2_2<=data6_2_2;n3_1<=data5_3_1;n3_2<=data6_3_2;
/ Y4 T( C8 z$ k0 z" Bend
& n. w, }+ g& J+ }  w9 ]default:
% l' L+ ~5 _) ^: H& F7 k& dbegin
9 ]4 D0 N$ _) G. v3 gn1_1<=s1_1;n1_2<=s1_2;n2_1<=s2_1;
+ p3 c6 q9 e+ l/ D& A) W" gn2_2<=s2_2;n3_1<=s3_1;n3_2<=s3_2;
9 ]- @4 m; M5 Aend
; X) h% X2 e- L4 Kendcase
0 t, U3 ?( |. }7 L* rend
else
begin
n1_1<=s1_1;n1_2<=s1_2;n2_1<=s2_1;
) S1 Q7 t/ x0 o# ^7 Yn2_2<=s2_2;n3_1<=s3_1;n3_2<=s3_2;
end
5 P$ t7 c) ]0 }% G' f) fend

always @(*)
begin
3 x4 a* G" C0 O6 h/ ]5 dif(cnt1==3'd5 || cnt2==3'd6)
% y" ]. s# m- R' c4 |, qkey=1'd1;
% t' o8 ^8 x0 W) a5 [& Qelse
key=1'd0;
end

endmodule

helendcany

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