Verilog写的异步FIFO程序

Allevi · 发表于 2019-5-31 10:09

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Verilog写的异步FIFO程序
//-----------------------------------------------------
2 // Design Name : syn_fifo
3 // File Name : syn_fifo.v
4 // Function : Synchronous (single clock) FIFO
5 // Coder    : Deepak Kumar Tala
6 //-----------------------------------------------------
7 module syn_fifo (
8 clk    , // Clock input
9 rst    , // Active high reset
  10 wr_cs , // Write chip select
  11 rd_cs , // Read chipe select
  12 data_in  , // Data input
  13 rd_en , // Read enable
  14 wr_en , // Write Enable
  15 data_out , // Data Output
  16 empty , // FIFO empty
  17 full    // FIFO full
  18 );
  19
  20 // FIFO constants
  21 parameter DATA_WIDTH = 8;
  22 parameter ADDR_WIDTH = 8;
  23 parameter RAM_DEPTH = (1 << ADDR_WIDTH);
  24 // Port Declarations
  25 input clk ;
  26 input rst ;
  27 input wr_cs ;
  28 input rd_cs ;
  29 input rd_en ;
  30 input wr_en ;
  31 input [DATA_WIDTH-1:0] data_in ;
  32 output full ;
  33 output empty ;
  34 output [DATA_WIDTH-1:0] data_out ;
  35
  36 //-----------Internal variables-------------------
  37 reg [ADDR_WIDTH-1:0] wr_pointer;
  38 reg [ADDR_WIDTH-1:0] rd_pointer;
  39 reg [ADDR_WIDTH :0] status_cnt;
  40 reg [DATA_WIDTH-1:0] data_out ;
  41 wire [DATA_WIDTH-1:0] data_ram ;
  42
  43 //-----------Variable assignments---------------
  44 assign full = (status_cnt == (RAM_DEPTH-1));
  45 assign empty = (status_cnt == 0);
  46
  47 //-----------Code Start---------------------------
  48 always @ (posedge clk or posedge rst)
  49 begin : WRITE_POINTER
  50 if (rst) begin
  51    wr_pointer <= 0;
  52 end else if (wr_cs && wr_en ) begin
  53    wr_pointer <= wr_pointer + 1;
  54 end
  55 end
  56
  57 always @ (posedge clk or posedge rst)
  58 begin : READ_POINTER
  59 if (rst) begin
  60    rd_pointer <= 0;
  61 end else if (rd_cs && rd_en ) begin
  62    rd_pointer <= rd_pointer + 1;
  63 end
  64 end
  65
  66 always  @ (posedge clk or posedge rst)
  67 begin : READ_DATA
  68 if (rst) begin
  69    data_out <= 0;
  70 end else if (rd_cs && rd_en ) begin
  71    data_out <= data_ram;
  72 end
  73 end
  74
  75 always @ (posedge clk or posedge rst)
  76 begin : STATUS_COUNTER
  77 if (rst) begin
  78    status_cnt <= 0;
  79 // Read but no write.
  80 end else if ((rd_cs && rd_en) && ! (wr_cs && wr_en)
  81             && (status_cnt ! = 0)) begin
  82    status_cnt <= status_cnt - 1;
  83 // Write but no read.
  84 end else if ((wr_cs && wr_en) && ! (rd_cs && rd_en)
  85             && (status_cnt ! = RAM_DEPTH)) begin
  86    status_cnt <= status_cnt + 1;
  87 end
  88 end
  89
  90 ram_dp_ar_aw #(DATA_WIDTH,ADDR_WIDTH)DP_RAM (
  91 .address_0 (wr_pointer) , // address_0 input
  92 .data_0 (data_in) , // data_0 bi-directional
  93 .cs_0    (wr_cs)    , // chip select
  94 .we_0    (wr_en)    , // write enable
  95 .oe_0    (1'b0)    , // output enable
  96 .address_1 (rd_pointer) , // address_q input
  97 .data_1 (data_ram) , // data_1 bi-directional
  98 .cs_1    (rd_cs)    , // chip select
  99 .we_1    (1'b0)    , // Read enable
100 .oe_1    (rd_en)       // output enable
101 );
102
103 endmodule

helendcany · 发表于 2019-5-31 16:06

这个代码要怎么用啊

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Verilog写的异步FIFO程序

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