滑动滤波函数FPGA实用程序

Allevi · 发表于 2019-5-21 09:32

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滑动滤波函数FPGA实用程序

滑动滤波函数FPGA实用程序，对输入数据进行滑动滤波，可以减少干扰信号带来的影响。本实用程序设计上取4096个点进行滑动滤波，采样周期可以自行设定或修改。程序如下：
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_signed.all;
entity get_filter is
port
(
   clk: in std_logic;
   rst: in std_logic;
   clk1ms: in std_logic;
   data: in std_logic_vector(15 downto 0);
   filter_result: out std_logic_vector(15 downto 0)
--  get_filter_state:buffer std_logic_vector(3 downto 0)
);
end get_filter;
architecture arch_get_filter of get_filter is
component  altsyncram
generic (
  operation_mode    : string;
  width_a       : natural;
  widthad_a    : natural;
  width_b       : natural;
  widthad_b    : natural;
  width_byteena_a    : natural;
  outdata_reg_b    : string;
  address_reg_b    : string;
  rdcontrol_reg_b    : string;
  read_during_write_mode_mixed_ports  : string;
  init_file    : string
);
port
  (
wren_a : in std_logic ;
clock0 : in std_logic ;
clock1 : in std_logic ;
address_a  : in std_logic_vector (widthad_a-1 downto 0);
address_b  : in std_logic_vector (widthad_b-1 downto 0);
rden_b : in std_logic ;
q_b : out std_logic_vector (width_b-1 downto 0);
data_a : in std_logic_vector (width_a-1 downto 0)
);
end component;
signal sum: std_logic_vector(31 downto 0);
signal get_filter_wraddr: std_logic_vector(11 downto 0);
signal get_filter_rdaddr:std_logic_vector(11 downto 0);
signal get_filter_rd,get_filter_wr: std_logic;
signal get_filter_wrdata: std_logic_vector(15 downto 0);
signal get_filter_rddata: std_logic_vector(15 downto 0);
signal get_filter_state: std_logic_vector(3 downto 0);
   begin
-------all rx data  buffer---------------------------------------
get_filter_ram : altsyncram
generic map
(
  operation_mode    => "dual_port",
  width_a             => 16,
  widthad_a       => 12,
  width_b             => 16,
  widthad_b       => 12,
  width_byteena_a          => 1,
  outdata_reg_b    => "unregistered",
  address_reg_b    => "clock1",
  rdcontrol_reg_b          => "clock1",
  read_during_write_mode_mixed_ports  => "old_data",
  init_file    =>"E:\JstHvfZkSoft\wavesim\get_pf.mif"
)
port map (
  wren_a       => get_filter_wr,
  clock0       => clk,
  clock1       => clk,
  address_a       => get_filter_wraddr,
  address_b       => get_filter_rdaddr,
  rden_b       => get_filter_rd,
  data_a       => get_filter_wrdata,
  q_b       => get_filter_rddata
);
process(clk,rst)
begin
if (rst='0') then
   get_filter_wraddr<=(others=>'1');
   get_filter_rdaddr<=(others=>'0');
   get_filter_wrdata<=(others=>'0');
   get_filter_rd<='0';
   get_filter_wr<='0';
   get_filter_state<=(others=>'0');
elsif clk'event and clk='1' then
   if (get_filter_state="0000") then
      sum<=(others=>'0');
      get_filter_rd<='1';
      get_filter_rdaddr<=get_filter_rdaddr+'1';
      get_filter_state<="0001";
   elsif (get_filter_state="0001") then
      get_filter_rdaddr<=get_filter_rdaddr+'1';
      get_filter_state<="0010";
   elsif (get_filter_state="0010") then
      get_filter_wr<='1';
      get_filter_wraddr<=get_filter_wraddr+'1';
      if (get_filter_rdaddr/=x"fff")then
      get_filter_rdaddr<=get_filter_rdaddr+'1';
      end if;
      get_filter_wrdata<=get_filter_rddata;
      sum<=sum+(get_filter_rddata(15)& get_filter_rddata(15)&get_filter_rddata(15)&get_filter_rddata(15)
      &get_filter_rddata(15)&get_filter_rddata(15)&get_filter_rddata(15)&get_filter_rddata(15)&get_filter_rddata);
   --- filter_result<=get_filter_rddata; -----used in test!
      if (get_filter_wraddr=x"ffd") then
            get_filter_state<="0011";
            get_filter_rd<='0';
      end if;
   elsif (get_filter_state="0011") then
      sum<=sum+(data(15)& data(15)&data(15)&data(15)
      &data(15)&data(15)&data(15)&data(15)&data);
   --- filter_result<=data;             -----used in test!
      get_filter_rdaddr<=(others=>'0');
      get_filter_wraddr<=get_filter_wraddr+'1';
      get_filter_wrdata<=data;
      get_filter_state<="0100";

   elsif (get_filter_state="0100") then
      filter_result<=sum(27 downto 12);
      -- if (clk1ms='1') then
         get_filter_state<="0000";
   --  end if;
   else
         get_filter_state<="0000";
   end if;
   end if;
end process;
end arch_get_filter;

帝君 · 发表于 2019-5-21 10:24

大神啊

雷北城 · 发表于 2022-8-18 16:03

滑动滤波函数FPGA实用程序

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滑动滤波函数FPGA实用程序

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